LTC6416IDDB-TRPBF

FEATURES n n n n n n n n n n n n n n LTC6416 2 GHz Low Noise Differential 16-Bit ADC Buffer DESCRIPTION The LTC®6416 is a differential unity gain buffer designed to drive 16-bit ADCs with extremely low output noise and excellent linearity beyond 300MHz. Differential input impedance is 12kΩ, allowing 1:4 and 1:8 transformers to be used at the input to achieve additional system gain. With no external biasing or gain setting components and a flow-through pinout, the LTC6416 is very easy to use. It can be DC-coupled and has a common mode output offset of –40mV. If the input signals are AC-coupled, the LTC6416 input pins are internally biased to provide an output common mode voltage that is set by the voltage on the VCM pin. In addition the LTC6416 has high speed, fast recovery clamping circuitry to limit output signal swing. Both the high and low clamp voltages are internally biased to allow maximum output swing but are also user programmable via the CLLO and CLHI pins. Supply current is nominally 42mA and the LTC6416 operates on supply voltages ranging from 2.7V to 3.9V. The LTC6416 is packaged in a 10-lead 3mm × 2mm DFN package. Pinout is optimized for placement directly adjacent to Linear’s high speed 12-, 14- and 16-bit ADCs. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. 2GHz –3dB Small Signal Bandwidth 300MHz ±0.1dB Bandwidth 1.8nV/√Hz Output Noise 46.25dBm Equivalent OIP3 at 140MHz 40.25dBm Equivalent OIP3 Up to 300MHz –81dBc/–72dBc HD2/HD3 at 140MHz, 2VP-P Out –84.5dBc IM3 at 140MHz, 2VP-P Out Composite –74dBc/–67.5dBc HD2/HD3 at 300MHz, 2VP-P Out –72.5dBc IM3 at 300MHz, 2VP-P Out Composite Programmable High Speed, Fast Recovery Output Clamping DC-Coupled Signal Path Operates on Single 2.7V to 3.9V Supply Low Power: 150mW on 3.6V 2mm × 3mm 10-Pin DFN Package APPLICATIONS n n n n n Differential ADC Driver IF Sampling Receivers Impedance Transformer SAW Filter Interface CCD Buffer TYPICAL APPLICATION LTC6416 Driving LTC2208 ADC – 140MHz IF AMPLITUDE (dBFS) 3.6V 680pF 0.1μF CLHI 1:8 50Ω 200Ω IN+ IN– GND 0.1μF CLLO V+ LTC6416 Driving LTC2208 ADC with 1:8 Transformer fIN =140MHz, fS = 130MHz, –1dBFS, PGA = 1 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 PGA = 1 6416 TA01a 2.2μF 1.5pF AIN+ 1pF AIN– 25Ω 1.5pF LTC2208 3.3V V+ = 3.6V HD2 = –94dBc HD3 = –89.1dBc SFDR = 89.1dB SNR = 70.7dB MEASURED USING DC1257B WITH MINI-CIRCUIT TCM8-1+ 1:8 TRANSFORMER VCM OUT+ OUT– GND 25Ω + – MINI-CIRCUITS TCM8-1+ LTC6416 200Ω 16 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 6416 TA01b CLOCK (130MHz) 6416f 1 LTC6416 ABSOLUTE MAXIMUM RATINGS (Note 1) PIN CONFIGURATION TOP VIEW VCM 1 CLHI 2 IN+ 3 IN– 4 CLLO 5 11 10 V+ 9 8 7 6 GND OUT+ OUT– GND Total Supply Voltage (V+ to GND)................................4V Input Current (CLLO, CLHI, VCM, IN+, IN–)...........±10mA Output Current (OUT+, OUT–) ...........................±22.5mA Operating Temperature Range (Note 2).... –40°C to 85°C Specified Temperature Range (Note 3) .... –40°C to 85°C Storage Temperature Range................... –65°C to 150°C Junction Temperature ........................................... 150°C DDB PACKAGE 10-LEAD (3mm 2mm) PLASTIC DFN TJMAX = 150°C, θJA = 76°C/W, θJC = 13.5°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C LTC6416CDDB#TRMPBF LTC6416CDDB#TRPBF LDDY 10-Lead (3mm × 2mm) Plastic DFN LTC6416IDDB#TRMPBF LTC6416IDDB#TRPBF LDDY 10-Lead (3mm × 2mm) Plastic DFN TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.6V, GND = 0V, No RLOAD, CLOAD = 6pF VCM = 1.25V, . CLHI = V+, CLLO = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as (OUT+ + OUT–)/2. VINDIFF is defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic. SYMBOL GDIFF TCGDIFF VSWINGDIFF VSWINGMIN VSWINGMAX IOUT VOS TCVOS VIOCM PARAMETER Differential Gain Differential Gain Temperature Coefficient Differential Output Voltage Swing Output Voltage Swing Low Output Voltage Swing High Output Current Drive Differential Input Offset Voltage Differential Input Offset Voltage Drift Common Mode Offset Voltage, Input to Output VOUTCM – VINCM VOUTDIFF, VINDIFF = ±2.3V Single-Ended Measurement of OUT+, OUT–. VINDIFF = ±2.3V Single-Ended Measurement of OUT+, OUT–. VINDIFF = ±2.3V Single-Ended Measurement of OUT+, OUT– IN+ = IN– = 1.25V, V GDIFF OS = VOUTDIFF/ 3.6V ELECTRICAL CHARACTERISTICS CONDITIONS VINDIFF = ±1.2V Differential MIN –0.3 –0.4 3.7 3.3 TYP –0.15 –0.00033 4.2 0.2 MAX 0 0 UNITS dB dB dB/°C VP-P VP-P Input/Output Characteristics l l l l l l l l l 0.3 0.35 V V V V mA 2.15 2 ±20 –5 –10 –65 –75 2.3 –0.5 1 –47 5 10 –15 –5 mV mV μV/°C mV mV 6416f 2 LTC6416 The l denotes the specifications which apply over the full . operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.6V, GND = 0V, No RLOAD, CLOAD = 6pF VCM = 1.25V, CLHI = V+, CLLO = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as (OUT+ + OUT–)/2. VINDIFF is defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic. SYMBOL IVRMIN IVRMAX IB RINDIFF CINDIFF RINCM CMRR eN iN GCM VINCMDEFAULT VOS (VCM – VINCM) VOUTCMDEFAULT VOS (VCM – VOUTCM) VOUTCMMIN VOUTCMMAX VCMDEFAULT RVCM CVCM IBVCM VCLHIDEFAULT VCLLODEFAULT RCLHI IBCLHI RCLLO IBCLLO Power Supply VS IS PSRR Supply Voltage Range Supply Current Power Supply Rejection Ratio VS = 2.7V to 3.6V l l l 3.6V ELECTRICAL CHARACTERISTICS PARAMETER Input Voltage Range, IN+, IN– (Minimum) (Single-Ended) Input Voltage Range IN+, IN– (Maximum) (Single-Ended) Input Bias Current, IN+, IN– Differential Input Resistance Differential Input Capacitance Input Common Mode Resistance Common Mode Rejection Ratio Input Noise Voltage Density Input Noise Current Density VCM Pin Common Mode Gain Default Input Common Mode Voltage Offset Voltage, VCM to VINCM Default Output Common Mode Voltage Offset Voltage, VCM to VOUTCM Output Common Mode Voltage Range (Minimum) Output Common Mode Voltage Range (Maximum) VCM Pin Default Voltage VCM Pin Input Resistance VCM Pin Input Capacitance VCM Pin Bias Current Default Output Clamp Voltage, High Default Output Clamp Voltage, Low CLHI Pin Input Resistance CLHI Pin Bias Current CLLO Pin Input Resistance CLLO Pin Bias Current CONDITIONS Defined by Output Voltage Swing Test Defined by Output Voltage Swing Test IN+ = IN– = 1.25V VINDIFF = ±1.2V IN+ = IN– = 0.65V to 1.85V IN+ = IN– = 0.65V to 1.85V, CMRR = (VOUTDIFF/GDIFF/1.2V) f = 100kHz f = 100kHz VCM = 0.65V to 1.85V VINCM. IN+, IN–, VCM Pin Floating VCM – VINCM, VCM = 1.25V Inputs Floating, VCM Pin Floating VCM – VOUTCM, VCM = 1.25V VCM = 0.1V VCM = 2.7V l l l l l l l l l l l l l l l l l l l l l l l MIN TYP MAX 0.1 UNITS V V 2.4 –15 9 –5 12 1 6 63.5 59.6 83 1.8 6.5 0.9 1.3 –70 1.25 –60 0.96 1.38 –28 1.34 15 0.37 2.3 2.25 1.325 2.5 –50 2.3 –55 0.125 –120 3 –25 1.5 –25 2.7 33 57.5 42 80 2.46 1.36 3.8 1 –32 2.45 13 0.265 –70 4.1 –1 2.3 4.5 1.425 5.1 50 2.6 55 0.425 0 5 25 3.2 25 3.9 51 54 1.05 1.45 70 1.45 60 0.5 0.55 15 15 μA kΩ pF kΩ dB dB nV/√Hz pA/√Hz V/V V mV V mV V V V V V kΩ pF μA V mV V mV kΩ μA kΩ μA V mA mA dB Output Common Mode Voltage Control VCM = 1.25V DC Clamping Characteristics VOS (CLHI – VOUTCM) Offset Voltage, CLHI to VOUTCM VOS (CLLO – VOUTCM) Offset Voltage, CLLO to VOUTCM VCLHI = 2.45V VCLHI = 2.45V VCLLO = 0.275V VCLLO = 0.275V 6416f 3 LTC6416 The l denotes the specifications which apply over the full . operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V, GND = 0V, No RLOAD, CLOAD = 6pF VCM = 1.25V, CLHI = V+, CLLO = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as (OUT+ + OUT–)/2. VINDIFF is defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic. SYMBOL GDIFF TCGDIFF VOUTDIFF VOUTMIN VOUTMAX IOUT VOS TCVOS VIOCM IVRMIN IVRMAX IB RINDIFF CINDIFF RINCM CMRR eN iN GCM VINCMDEFAULT VOS (VCM – VINCM) VOUTCMDEFAULT VOS (VCM – VOUTCM) VOUTCMMIN VOUTCMMAX VCMDEFAULT RVCM CVCM IBVCM PARAMETER Differential Gain Differential Gain Temperature Coefficient Differential Output Voltage Swing Output Voltage Swing Low Output Voltage Swing High Output Current Drive (Note 4) Differential Input Offset Voltage Differential Input Offset Voltage Drift Common Mode Offset Voltage, Input to Output Input Voltage Range, IN+, IN– (Minimum) (Single-Ended) Input Voltage Range, IN+, IN– (Maximum) (Single-Ended) Input Bias Current, IN+, IN– Differential Input Resistance Differential Input Capacitance Input Common Mode Resistance Common Mode Rejection Ratio Input Noise Voltage Density Input Noise Current Density VCM Pin Common Mode Gain Default Input Common Mode Voltage Offset Voltage, VCM to VINCM Default Output Common Mode Voltage Offset Voltage, VCM to VOUTCM Output Common Mode Voltage (Minimum) Output Common Mode Voltage (Maximum) VCM Pin Default Voltage VCM Pin Input Resistance VCM Pin Input Capacitance VCM Pin Bias Current VCM = 1.25V l 3.3V ELECTRICAL CHARACTERISTICS CONDITIONS VINDIFF = ±1.2V MIN –0.3 –0.4 3.5 3.2 TYP –0.15 –0.00033 4 0.2 MAX 0 0 UNITS dB dB dB/°C VP-P VP-P Input/Output Characteristics l l VINDIFF = ±2.3V Single-Ended Measurement of OUT+, OUT–. VINDIFF = ±2.3V Single-Ended Measurement of OUT+, OUT–. VINDIFF = ±2.3V Single-Ended Measurement of OUT+, OUT– IN+ = IN– = 1.25V, V GDIFF VOUTCM – VINCM OS = VOUTDIFF/ l l l l l l l 0.3 0.35 V V V V mA 2.05 1.95 ±20 –5 –10 –65 –75 2.2 –0.1 1 –40 5 10 –15 –5 0.1 mV mV μV/°C mV mV V V Defined by Output Voltage Swing Test l Defined by Output Voltage Swing Test l IN+ = IN– = 1.25V VINDIFF = ±1.2V IN+ = IN– = 0.65V to 1.85V IN+ = IN– = 0.65V to 1.85V = ΔVINCM, CMRR = (VOUTDIFF/GDIFF/ΔVINCM) f = 100kHz f = 100kHz VCM = 0.65V to 1.85V VINCM. IN+, IN–, VCM Pin Floating VCM – VINCM, VCM = 1.25V Inputs Floating, VCM Pin Floating VCM – VOUTCM, VCM = 1.25V VCM = 0.1V VCM = 2.4V l l l l l l l l l l l l 2.4 –15 9 –4 12 1 6 63.5 59.6 83 1.8 6.5 0.9 1.2 –70 1.15 –60 0.96 1.28 –26 1.24 14 0.34 2.05 2 1.2 2.5 –10 2.16 1.25 3.8 1 0.2 10 1.3 5.1 1.05 1.35 70 1.35 60 0.5 0.55 15 15 μA kΩ pF kΩ dB dB nV/√Hz pA/√Hz V/V V mV V mV V V V V V kΩ pF μA 6416f Output Common Mode Voltage Control 4 LTC6416 3.3V ELECTRICAL CHARACTERISTICS SYMBOL VCLHIDEFAULT VOS (CLHI – VOUTCM) VCLLODEFAULT RCLHI IBCLHI RCLLO IBCLLO Power Supply VS IS PSRR Supply Voltage Range Supply Current Power Supply Rejection Ratio VS = 2.7V to 3.6V l l l The l denotes the specifications which apply over the full . operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V, GND = 0V, No RLOAD, CLOAD = 6pF VCM = 1.25V, CLHI = V+, CLLO = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as (OUT+ + OUT–)/2. VINDIFF is defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic. PARAMETER Default Output Clamp Voltage, High Offset Voltage, CLHI to VOUTCM Default Output Clamp Voltage, Low CLHI Pin Input Resistance CLHI Pin Bias Current CLLO Pin Input Resistance CLLO Pin Bias Current VCLHI = 2.25V VCLHI = 2.25V VCLLO = 0.25V VCLLO = 0.25V CONDITIONS l l l l l l l l MIN 2.1 –55 0.1 –120 3 –25 1.5 –25 2.7 33 57.5 TYP 2.23 4 0.25 –72 4.1 –1 2.3 3 MAX 2.4 55 0.4 0 5 25 3.2 25 3.9 UNITS V mV V mV kΩ μA kΩ μA V mA mA dB DC Clamping Characteristics VOS (CLLO – VOUTCM) Offset Voltage, CLLO to VOUTCM 42 80 51 54 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V and 3.6V unless otherwise noted, GND = 0V, No RLOAD, CLOAD = 6pF VCM = 1.25V, CLHI = VCC, CLLO = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as . (OUT+ + OUT–)/2. VINDIFF is defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic. SYMBOL –3dBBW 0.1dBBW 0.5dBBW 1/f SR tS1% –3dBBWVCM SRCM tOVDR AC Linearity 70MHz Signal HD2 Second Harmonic Distortion V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P V+ = 3.3V, VCM = 1.25V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.05V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P –83.5 –71 –78.5 –88.5 dBc dBc dBc dBc PARAMETER –3dB Bandwidth ±0.1dB Bandwidth ±0.5dB Bandwidth 1/f Noise Corner Slew Rate 1% Settling Time VCM Pin Small Signal –3dB BW Common Mode Slew Rate Overdrive Recovery Time Differential 2VP-P,OUT VCM = 0.1VP-P, Measured Single-Ended at Output Measured Single-Ended at Output 1.9VP-P,OUT CONDITIONS 200mVP-P,OUT Differential 200mVP-P,OUT Differential 200mVP-P,OUT Differential MIN TYP 2 0.3 1.4 25 3.4 1.8 9 40 5 MAX UNITS GHz GHz GHz kHz V/ns ns MHz V/μs ns Differential AC Characteristics AC ELECTRICAL CHARACTERISTICS Common Mode AC Characteristics (VCM Pin) AC Clamping Characteristics 6416f 5 LTC6416 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V and 3.6V unless otherwise noted, GND = 0V, No RLOAD, CLOAD = 6pF VCM = 1.25V, CLHI = VCC, CLLO = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as . (OUT+ + OUT–)/2. VINDIFF is defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic. SYMBOL HD3 PARAMETER Third Harmonic Distortion CONDITIONS V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P V+ = 3.3V, VCM = 1.25V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.05V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.25V MIN TYP –73 –60 –94.5 –83 –76.5 –86 42.25 47 14.1 MAX UNITS dBc dBc dBc dBc dBc dBc dBm dBm dBm AC ELECTRICAL CHARACTERISTICS IM3 OIP3 P1dB Output Third Order Intermodulation Distortion Output Third Order Intercept (Equivalent) (Note 5) Output 1dB Compression Point (Equivalent) (Note 5) Second Harmonic Distortion 140MHz Signal HD2 V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P V+ = 3.3V, VCM = 1.25V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.05V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P V+ = 3.3V, VCM = 1.25V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.05V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.25V –79.5 –75.5 –73 –81 –64 –55 –70 –72 –75 –84.5 41.5 46.25 14.1 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBm dBm dBm HD3 Third Harmonic Distortion IM3 OIP3 P1dB Output Third Order Intermodulation Distortion Output Third Order Intercept (Equivalent) (Note 5) Output 1dB Compression Point (Equivalent) (Note 5) Second Harmonic Distortion 300MHz Signal HD2 V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P V+ = 3.3V, VCM = 1.25V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.05V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P V+ = 3.3V, VCM = 1.25V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.05V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P V+ = 3.6V, VCM = 1.25V 36 –75 –65 –69.5 –74 –59 –51.5 –63 –67.5 –68.5 –72.5 38.25 40.25 12.9 –64 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBm dBm dBm HD3 Third Harmonic Distortion IM3 OIP3 P1dB Output Third Order Intermodulation Distortion Output Third Order Intercept (Equivalent) (Note 5) Output 1dB Compression Point (Equivalent) (Note 5) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC6416C/LTC6416I is guaranteed functional over the operating temperature range of –40°C to 85°C. Note 3: The LTC6416C is guaranteed to meet specified performance from 0°C to 70°C. It is designed, characterized and expected to meet specified performance from –40°C and 85°C but is not tested or QA sampled at these temperatures. The LT6416I is guaranteed to meet specified performance from –40°C to 85°C. Note 4: This parameter is pulse tested. Note 5: Since the LTC6416 is a voltage-output buffer, a resistive load is not required when driving an AD converter. Therefore, typical output power is very small. In order to compare the LTC6416 with amplifiers that require a 50Ω output load, the LTC6416 output voltage swing driving a given RL is converted to OIP3 and P1dB as if it were driving a 50Ω load. Using this modified convention, 2VP-P is by definition equal to 10dBm, regardless of actual RL. 6416f 6 LTC6416 TYPICAL PERFORMANCE CHARACTERISTICS Differential Forward Gain (S21) vs Frequency 2 0 DIFFERENTIAL GAIN (dB) –2 –4 S11 (dB) –6 –8 –10 –12 –14 –16 10 100 1000 FREQUENCY (MHz) 10000 6416 G01 Differential Input Return Loss (S11) vs Frequency 0 –5 –10 –15 –20 –25 –30 –35 DIFFERENTIAL OUTPUT RETURN LOSS (dB) V+ = 3.3V 0 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 Differential Output Return Loss (S22) vs Frequency V+ = 3.3V V+ = 3.3V 10 100 FREQUENCY (MHz) 1000 6416 G02 10 100 FREQUENCY (MHz) 1000 6416 G03 Differential Reverse Isolation (S12) vs Frequency –20 DIFFERENTIAL REVERSE ISOLATION (dB) –30 –40 HD2, HD3 (dBc) –50 –60 –70 –80 –90 10 100 FREQUENCY (MHz) 1000 6416 G04 Second and Third Harmonic Distortion vs Frequency –50 HD3 –60 HD2, HD3 (dBc) –50 Second and Third Harmonic Distortion vs Frequency V+ = 3.6V VCM = 1.25V RLOAD = 400Ω –60 V OUT = 2VP-P DIFFERENTIAL –70 HD3 V+ = 3.3V –70 HD2 –80 V+ = 3.3V VCM = 1.25V RLOAD = 400Ω VOUT = 2VP-P DIFFERENTIAL 10 100 FREQUENCY (MHz) 500 6416 G05 –80 HD2 –90 –90 –100 –100 –100 10 100 FREQUENCY (MHz) 500 6416 G06 6416f 7 LTC6416 TYPICAL PERFORMANCE CHARACTERISTICS Second and Third Harmonic Distortion vs Output Common Mode Voltage (75MHz) –50 V+ = 3.6V RLOAD = 400Ω VOUT = 2VP-P DIFFERENTIAL HD2, HD3 (dBc) –50 Second and Third Harmonic Distortion vs Output Common Mode Voltage (140MHz) V+ = 3.6V RLOAD = 400Ω VOUT = 2VP-P DIFFERENTIAL HD2, HD3 (dBc) –50 Second and Third Harmonic Distortion vs Output Common Mode Voltage (250MHz) V+ = 3.6V RLOAD = 400Ω VOUT = 2VP-P DIFFERENTIAL HD3 –60 HD2, HD3 (dBc) –60 –60 –70 HD3 –80 HD2 –90 –70 HD3 –80 HD2 –90 –70 HD2 –80 –90 –100 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 VCM (V) 6416 G07 –100 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 VCM (V) 6416 G08 –100 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 VCM (V) 6416 G09 Second and Third Harmonic Distortion vs Output Common Mode Voltage (300MHz) –50 V+ = 3.6V RLOAD = 400Ω VOUT = 2VP-P DIFFERENTIAL HD3 HD2, HD3 (dBc) IM3 (dBc) –50 Third Order Intermodulation Distortion (IM3) vs Frequency and Supply Voltage –50 IM3 VCC = 3.3V –60 –60 Third Order Intermodulation Distortion (IM3) vs Output Common Mode Voltage (140MHz) IM3 V+ = 3.3V –60 HD2 –80 IM3 VCC = 3.6V –80 V+ = 3.3V, 3.6V; VCM = 1.25V RLOAD = 400Ω VOUT = 2VP-P DIFFERENTIAL (COMPOSITE) f = 1MHz 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) 6416 G11 IM3 (dBc) –70 –70 –70 IM3 V+ = 3.6V –80 –90 –90 –100 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 VCM (V) 6416 G10 –100 + –90 V = 3.3V, 3.6V RLOAD = 400Ω VOUT = 2VP-P DIFFERENTIAL (COMPOSITE) f = 1MHz –100 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 VCM (V) 6416 G12 Output Third Order Intercept (OIP3EQUIV) vs Frequency and Supply Voltage 50 50 Output Third Order Intercept (OIP3EQUIV) vs Output Common Mode Voltage and Supply Voltage (140MHz) 15.0 P1dB COMPRESSION (EQUIVALENT) (dBm) 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 Output 1dB Compression (Equivalent) vs Frequency, VCM and Supply Voltage V+ = 3.3V V+ = 3.6V 45 OIP3EQUIV (dBm) OIP3 VCC = 3.6V OIP3EQUIV (dB) 40 OIP3 VCC = 3.3V 35 V+ = 3.3V, 3.6V 30 VCM = 1.25V RLOAD = 400Ω VOUT = 2VP-P DIFFERENTIAL (COMPOSITE) f = 1MHz 25 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) 6416 G13 45 OIP3EQUIV V+ = 3.6V 40 VCM = 1.25V 35 OIP3EQUIV V+ = 3.3V VCM = 1.05V + 30 V = 3.3V, 3.6V RLOAD = 400Ω VOUT = 2VP-P DIFFERENTIAL (COMPOSITE) f = 1MHz 25 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 VCM (V) 6416 G14 V+ = 3.3V, 3.6V 10.5 RLOAD = 400Ω VOUT = 2VP-P DIFFERENTIAL 10.0 0 50 100 150 200 250 300 350 400 FREQUENCY (MHz) 6416 G15 6416f 8 LTC6416 TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Supply Voltage 50 45 40 SUPPLY CURRENT (mA) 35 30 25 20 15 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 SUPPLY VOLTAGE (V) 3.5 4.0 INPUT REFERRED NOISE VOLTAGE (nV√Hz) 14 12 10 8 6 4 2 0 NF Noise Figure and Input Referred Noise Voltage vs Frequency 14 12 10 8 6 4 2 0 NOISE FIGURE (dB) 90 80 70 60 PSRR (dB) 50 40 30 20 10 PSRR vs Frequency V+ = 3.6V eN 1k 10k 100k 1M 10M FREQUENCY (Hz) 100M 1G 0 0.1 1 10 FREQUENCY (MHz) 100 1000 6416 G29 6416 G16 6416 G17 Positive Overdrive Recovery (VCLHI Pin) 200mV/DIV IN+ OUT+ 200mV/DIV Negative Overdrive Recovery (VCLLO Pin) 10mV/DIV Small Signal Transient Response, Rising Edge OUT+ IN+ 20ns/DIV 6416 G18 20ns/DIV 6416 G19 500ps/DIV 6416 G30 Small Signal Transient Response, Falling Edge 10mV/DIV AMPLITUDE (dBFS) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 LTC6416 Driving LTC2208 16-Bit ADC, 64K Point FFT, fIN = 30MHz, –1dBFS, PGA = 0 V+ = 3.6V HD2 = –104.9dBc HD3 = –86.1dBc SFDR = 86.05dB SNR = 76.5dB SEE FIGURE 5/ TABLE 1 1:1 BALUN 3 2 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 LTC6416 Driving LTC2208 16-Bit ADC, 64K Point FFT, fIN = 30MHz, –1dBFS, PGA = 1 V+ = 3.6V HD2 = –101.9dBc HD3 = –96.2dBc SFDR = 96.2dBc SNR = 74.2dB SEE FIGURE 5/ TABLE 1 1:1 BALUN 500ps/DIV 6416 G31 AMPLITUDE (dBFS) 3 2 0 10 20 30 40 FREQUENCY (MHz) 50 60 6416 G20 0 10 20 30 40 FREQUENCY (MHz) 50 60 6416 G21 6416f 9 LTC6416 TYPICAL PERFORMANCE CHARACTERISTICS LTC6416 Driving LTC2208 16-Bit ADC, 64K Point FFT, fIN = 70MHz, –1dBFS, PGA = 0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 V+ = 3.6V HD2 = –95dBc HD3 = –86dBc SFDR = 86dBc SNR = 74.6dBFS SEE FIGURE 5/TABLE 1 1:1 BALUN 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 LTC6416 Driving LTC2208 16-Bit ADC, 64K Point FFT, fIN = 70MHz, –1dBFS, PGA = 1 V+ = 3.6V HD2 = –99dBc HD3 = –91dBc SFDR = 91dBc SNR = 73dBFS SEE FIGURE 5/TABLE 1 1:1 BALUN 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 LTC6416 Driving LTC2208 16-Bit ADC, 64K Point FFT, fIN = 140MHz, –1dBFS, PGA = 0 V+ = 3.6V HD2 = –85.6dBc HD3 = –95.5dBc SFDR = 85.6dBc SNR = 72.6dBFS SEE FIGURE 5/TABLE 1 1:1 BALUN AMPLITUDE (dBFS) AMPLITUDE (dBFS) 3 2 AMPLITUDE (dBFS) 2 3 5 3 2 0 10 20 30 40 FREQUENCY (MHz) 50 60 6416 G22 0 10 20 30 40 FREQUENCY (MHz) 50 60 6416 G23 0 10 20 30 40 FREQUENCY (MHz) 50 60 6416 G24 LTC6416 Driving LTC2208 16-Bit ADC, 64K Point FFT, fIN = 140MHz, –1dBFS, PGA = 1 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 V+ = 3.6V HD2 = –91.8dBc HD3 = –93.6dBc SFDR = 91.8dBc SNR = 70.9dBFS SEE FIGURE 5/TABLE 1 1:1 BALUN 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 LTC6416 Driving LTC2208 16-Bit ADC, 64K Point FFT, fIN = 30MHz and 31MHz, –7dBFS/Tone, PGA = 0 V+ = 3.6V IM3 = 86dBc SEE FIGURE 5/ TABLE 1 1:1 BALUN AMPLITUDE (dBFS) 2 3 0 10 20 30 40 FREQUENCY (MHz) AMPLITUDE (dBFS) 50 60 6416 G25 0 10 20 30 40 FREQUENCY (MHz) 50 60 6416 G26 LTC6416 Driving LTC2208 16-Bit ADC, 64K Point FFT, fIN = 70MHz and 71MHz, –7dBFS/Tone, PGA = 0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 V+ = 3.6V IM3 = 81.7dBc SEE FIGURE 5/TABLE 1 1:1 BALUN AMPLITUDE (dBFS) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 LTC6416 Driving LTC2208 16-Bit ADC, 64K Point FFT, fIN = 139.5MHz and 140.5MHz, –7dBFS/Tone, PGA = 0 V+ = 3.6V IM3 = 81.7dBc SEE FIGURE 5/TABLE 1 1:1 BALUN AMPLITUDE (dBFS) 0 10 20 30 40 FREQUENCY (MHz) 50 60 6416 G27 0 10 20 30 40 FREQUENCY (MHz) 50 60 6416 G28 6416f 10 LTC6416 PIN FUNCTIONS VCM (Pin 1): This pin sets the output common mode voltage seen at OUT+ and OUT– by driving IN+ and IN– through an internal buffer with a high output resistance of 6k. The VCM pin has a Thevenin equivalent resistance of approximately 3.8k and can be overdriven by an external voltage. If no voltage is applied to VCM, it will float to a default voltage of approximately 1.25V on a 3.3V supply or 1.36V on a 3.6V supply. The VCM pin should be bypassed with a high-quality ceramic bypass capacitor of at least 0.1μF . CLHI (Pin 2): High Side Clamp Voltage. The voltage applied to the CLHI pin defines the upper voltage limit of the OUT+ and OUT– pins. This voltage should be set at least 300mV above the upper voltage range of the driven ADC. On a 3.3V supply, the CLHI pin will float to a 2.23V default voltage. On a 3.6V supply, the CLHI pin will float to a 2.45V default voltage. CLHI has a Thevenin equivalent of approximately 4.1kΩ and can be overdriven by an external voltage. The CLHI pin should be bypassed with a high-quality ceramic bypass capacitor of at least 0.1μF . IN+,IN– (Pins 3, 4): Non-inverting and inverting input pins of the buffer, respectively. These pins are high impedance, approximately 6kΩ. If AC-coupled, these pins will self bias to the voltage present at the VCM pin. CLLO (Pin 5): Low Side Clamp Voltage. The voltage applied to the CLLO pin defines the lower voltage limit of the OUT+ and OUT– pins. This voltage should be set at least 300mV below the lower voltage range of the driven ADC. On a 3.3V supply, the CLLO pin will float to a 0.25V default voltage. On a 3.6V supply, the CLLO pin will float to a 0.265V default voltage. CLLO has a Thevenin equivalent resistance of approximately 2.3k and can be overdriven by an external voltage. The CLLO pin should be bypassed with a high quality ceramic bypass capacitor of at least 0.1μF . GND (Pins 6, 9, 11): Negative power supply, normally tied to ground. Both pins and the exposed paddle must be tied to the same voltage. GND may be tied to a voltage other than ground as long as the voltage between V+ and GND is 2.7V to 4V. If the GND pins are not tied to ground, bypass them with 680pF and 0.1μF capacitors as close to the package as possible. OUT–, OUT+ (Pins 7, 8): Outputs. The LTC6416 outputs are low impedance. Each output has an output impedance of approximately 9Ω at DC. V+ (Pin 10): Positive Power Supply. Typically 3.3V to 3.6V. Split supplies are possible as long as the voltage between V+ and GND is 2.7V to 4V. Bypass capacitors of 680pF and 0.1μF as close to the part as possible should be used between the supplies. Exposed Pad (Pin 11): Ground. The exposed pad must be soldered to the printed circuit board ground plane for good heat transfer. If GND is a voltage other than ground, the Exposed Pad must be connected to a plane with the same potential as the GND pins – Not to the system ground plane. DC TEST CIRCUIT SCHEMATIC V+ 10 V+ VCM VINDIFF = IN+ – IN– IN+ + IN– 2 IN+ IN– CLLO CLHI VINCM = 1 VCM 8 2 CLHI OUT+ 3 + LTC6416 IN – OUT 4– IN 7 5 CLLO 11 9 6 OUT CLOAD RLOAD 6416 DC – OUT+ VOUTDIFF = OUT+ – OUT– + – VOUTCM = OUT + OUT 2 6416f 11 LTC6416 BLOCK DIAGRAM LTC6416 Simplified Schematic V+ 1 VCM R5 13.5k x1 2 3 CLHI IN+ R1 6k R11 6k Q13 Q11 Q14 R12 9Ω Q3 Q1 Q12 OUT– 7 Q4 R2 9Ω R3 6k I1 I11 I13 10 Q2 OUT+ 8 4 IN– 5 CLLO R6 2.5k R4 13k Q5 I2 I12 GND (6, 9) 6416 BD 6416f 12 LTC6416 APPLICATIONS INFORMATION Circuit Operation The LTC6416 is a low noise and low distortion fully differential unity-gain ADC driver with operation from DC to 2GHz (–3dB bandwidth), a differential input impedance of 12kΩ, and a differential output impedance of 18Ω. The LTC6416 is composed of a fully differential buffer with output common mode voltage control circuitry and high speed voltage-limiting clamps at the output. Small output resistors of 9Ω improve the circuit stability over various load conditions. They also simplify possible external filtering options, which are often desirable when the load is an ADC. Lowpass or bandpass filters are easily implemented with just a few external components. The LTC6416 is very flexible in terms of I/O coupling. It can be AC- or DCcoupled at the inputs, the outputs or both. When using the LTC6416 with DC-coupled inputs, best performance is obtained with an input common mode voltage between 1V and 1.5V. For AC-coupled operation, the LTC6416 will take the voltage applied to the VCM pin and use it to bias the inputs so that the output common mode voltage equals VCM, thus no external circuitry is needed. The VCM pin has been designed to directly interface with the VCM pin found on Linear Technology’s 16-, 14- and 12-bit high speed ADC families. Input Impedance and Matching The LTC6416 has a high differential input impedance of 12kΩ. The differential inputs may need to be terminated to a lower value impedance, e.g. 50Ω, in order to provide an impedance match for the source. Figure 1 shows input 0.1μF 3 1:1 50Ω VIN 24.9Ω 0.1μF IN+ OUT+ 8 matching using a 1:1 balun, while Figure 2 shows matching using a 1:4 balun. These circuits provide a wideband impedance match. The balun and matching resistors must be placed close to the input pins in order to minimize the rejection due to input mismatch. In Figure 1, the capacitor center-tapping the two 24.9Ω resistors improves high frequency common mode rejection. As an alternative to this wideband approach, a narrowband impedance match can be used at the inputs of the LTC6416 for frequency selection and/or noise reduction. The noise performance of the LTC6416 also depends upon the source impedance and termination. For example, the input 1:4 balun in Figure 2 improves SNR by adding 6dB of voltage gain at the inputs. A trade-off between gain and noise is obvious when constant noise figure circle and constant gain circle are plotted within the same input Smith Chart. This technique can be used to determine the optimal source impedance for a given gain and noise requirement. Output Match and Filter The LTC6416 provides a source resistance of 9Ω at each output. For testing purposes, Figure 3 and Figure 4 show the LTC6416 driving a differential 400Ω load impedance using a 1:1 or 1:4 balun, respectively. The LTC6416 can drive an ADC directly without external output impedance matching, but improved performance can usually be obtained with the addition of a few external components. Figure 5 shows a typical topology used for driving the LTC2208 16-bit ADC. • • LTC6416 + – 0.1μF 24.9Ω 4 IN– OUT– 6416 F01 7 Figure 1. Input Termination for Differential 50Ω Input Impedance Using a 1:1 Balun 6416f 13 LTC6416 APPLICATIONS INFORMATION 0.1μF 3 1:4 50Ω VIN 0.1μF 100Ω LTC6416 IN+ OUT+ 8 • + – • 0.1μF 100Ω 4 IN– OUT– 6416 F02 7 Figure 2. Input Termination for Differential 50Ω Input Impedance Using a 1:4 Balun 3 IN+ OUT+ 8 165Ω 0.1μF 1:1 0.1μF 50Ω LTC6416 • • 0.1μF 4 IN– 7 OUT– 165Ω 6416 F03 Figure 3. Output Termination for Differential 400Ω Load Impedance Using a 1:1 Balun 3 IN+ 8 OUT+ 90.9Ω 0.1μF 4:1 0.1μF 50Ω LTC6416 • • 0.1μF 4 IN– OUT– 7 90.9Ω 6416 F04 Figure 4. Output Termination for Differential 400Ω Load Impedance Using a 4:1 Balun 3.6V 680pF T1 TCM4-19+ 4 50Ω 0.1μF CLHI 3 2 R36 100Ω R15 100Ω IN+ IN– GND C39 CLLO 0.01μF V+ 2.2μF 1.5pF 1pF AIN– 25Ω 1.5pF VCM AIN+ LTC2208 3.3V VCM OUT+ GND OUT– 25Ω + – LTC6416 16 DATA 6 1 6416 F05 CLOCK (130MHz) Figure 5. DC1257B Simplified Schematic with Suggested Output Termination for Driving an LTC2208 16-Bit ADC at 140MHz 6416f 14 LTC6416 APPLICATIONS INFORMATION As seen in Table 1, suggested component values for the filter will change for differing IF frequencies. Table 1. INPUT FREQUENCY 30MHz 70MHz 140MHz 250MHz LTC6416 OUTPUT RESISTORS 50Ω 25Ω 25Ω 5Ω FILTERING CAPACITORS 5.6pF/6.8pF/5.6pF 5.6pF/6.8pF/5.6pF 1.5pF/1pF/1.5pF -/-/- to 2.23V. On a 3.6V supply, CLLO self-biases to 0.265V while CLHI self-biases to 2.45V. Both CLLO and CLHI pins should be bypassed with a 0.1μF capacitor as close to the LTC6416 as possible. Interfacing the LTC6416 to A/D Converters The LTC6416 has been specifically designed to interface directly with high speed A/D converters. It is possible to drive the ADC directly from the LTC6416. In practice, however, better performance may be obtained by adding a few external components at the output of the LTC6416. Figure 5 shows the LTC6416 being driven by a 1:8 transformer which provides 9dB of voltage gain while also performing a single-ended to differential conversion. The differential outputs of the LTC6416 are lowpass filtered, then drive the differential inputs of the LTC2208 ADC. In many applications, an anti-alias filter like this is desirable to limit the wideband noise of the amplifier. This is especially true in high performance 16-bit designs. The minimum recommended network between the LTC6416 and the ADC is simply two 5Ω series resistors, which are used to help eliminate resonances associated with the stray capacitance of PCB traces and the stray inductance of the internal bond wires at the ADC input, and the driver output pins. Single-Ended Signals The LTC6416 has not been designed to convert singleended signals to differential signals. A single-ended input signal can be converted to a differential signal via a balun connected to the inputs of the LTC6416. Power Supply Considerations For best linearity, the LTC6416 should have a positive supply of V+ = 3.6V. The LTC6416 has an internal edge-triggered supply voltage clamp. The timing mechanism of the clamp enables the LTC6416 to withstand ESD events. This internal clamp is also activated by voltage overshoot and rapid slew rate on the positive supply V+ pin. The LTC6416 should not be hot-plugged into a powered socket. Bypass capacitors of 680pF and 0.1μF should be placed to the V+ pin, as close as possible to the LTC6416. 6416f Output Common Mode Adjustment The output common mode voltage is set by the VCM pin. Because the input common mode voltage is approximately the same as the output common mode voltage, both are approximately equal to VCM. The VCM pin has a Thevenin equivalent resistance of 3.8k and can be overdriven by an external voltage. The VCM pin floats to a default voltage of 1.25V on a 3.3V supply and 1.36V on a 3.6V supply. The output common mode voltage is capable of tracking VCM in a range from 0.34V to 2.16V on a 3.3V supply. The VCM pin can be floated, but it should always be bypassed close to the LTC6416 with a 0.1μF bypass capacitor to ground. When interfacing with A/D converters such as the LTC22xx families, the VCM pin can be connected to the VCM output pin of the ADC, as shown in Figure 5. CLLO and CLHI Pins The CLLO and CLHI pins are used to set the clamping voltage for high speed internal circuitry. This circuitry limits the single-ended minimum and maximum voltage excursion seen at each of the outputs. This feature is extremely important in applications with input signals having very large peak-to-average ratios such as cellular basestation receivers. If a very large peak signal arrives at the LTC6416, the voltages applied to the CLLO and CLHI pins will determine the minimum and maximum output swing respectively. Once the input signal returns to the normal operating range, the LTC6416 returns to linear operation within 5ns. Both CLLO and CLHI are high impedance inputs. CLLO has an input impedance of 2.3k, while CLHI has an input impedance of 4.1k. On a 3.3V supply, CLLO self-biases to 0.25V while CLHI self-biases 15 LTC6416 APPLICATIONS INFORMATION Test Circuits Due to the fully differential design of the LTC6416 and its usefulness in applications both with and without ADCs, two test circuits are used to generate the information in this data sheet. Test circuit A is Demo Board DC1287A, a two-port demonstration circuit for the LTC6416. The board layout and the schematic are shown in Figures 6 and 7. This circuit includes input and output 1:1 baluns for single-ended-to-differential conversion, allowing direct analysis using a 2-port network analyzer. In this circuit implementation, there are series resistors at the output to present the LTC6416 with a 382Ω differential load, thereby optimizing distortion performance. Including the 1:1 input and output baluns, the –3dB bandwidth is approximately 2GHz. Test circuit B is Demo Circuit DC1257B. It consists of an LTC6416 driving an LTC2208 ADC. It is intended for use in conjunction with demo circuit DC890B (computer interface board) and proprietary Linear Technology evaluation software to evaluate the performance of both parts together. Both the DC1257B board layout and the schematic can be seen in Figures 8 and 9. Figure 6. Demo Board DC1287A Layout VCM C1 0.1μF C2 680pF C3 0.1μF V+ 2.7V TO 4V GND CLHI T1 MABA-007190-000000 C7 0.1μF C8 OPT 5 1 R2 24.9Ω R6 24.9Ω C4 0.1μF R4 0Ω 1 2 3 4 VCM CLHI IN+ V+ GND 10 9 R1 165Ω J1 IN+ T2 MABA-007190-000000 3 2 C6 4 OPT C5 0.1μF J3 OUT+ 2 4 3 J2 IN– C10 OPT R5 0Ω C15 0.1μF LTC6416 OUT+ 8 7 OUT– IN– 5 6 CLLO GND GND 11 • R3 165Ω 1 C14 0.1μF • 5 C11 0.1μF J4 OUT– C9 OPT GND 6416 TA04 • • C12 0.1μF CLLO C13 0.1μF Figure 7. Demo Board DC1287A Schematic (Test Circuit A) 6416f 16 LTC6416 APPLICATIONS INFORMATION Figure 8. Demo Board DC1257B Layout 6416f 17 1 HI 2 2 R5 R6 OPT OPT OFF 3 LOW R2 10Ω R3 10Ω LTC6416 R4 1k 3 EXTREF E7 C10 0.1μF VDD VCC C9 0.1μF OVP C12 0.1μF 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 R9 1k VCC OFA DA9 DA8 PGA LVDS DA15 DA14 DA13 DA12 DA11 DA10 DA7 RAND MODE OGND OVDD C14 0.1μF R7, 100Ω C8 0.1μF 1 VDD GND SHDN DITH DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 OGND OVDD CLLO 17 18 19 20 21 22 23 24 25 26 27 27 29 30 31 32 E3 R18 OPT C27 0.1μF 65 GND 1 • 2 1 R26 51.1Ω 3 C30 0.1μF 3 R21 100Ω SHDN EN 2 ON OFF 2 J4 5 C29 0.1μF 1 18 VDD JP1 PGA VDD VDD JP2 RAND J1 EDGE-CON (GOLD FINGER) 1 SENSE DA6 DA5 DA4 DA3 DA2 DA1 DA0 LTC2208CUP CLKCOUTB OFB DB15 DB14 DB13 DB12 DB11 DB10 33 OVP 34 35 36 37 38 39 40 CLKCOUTA 41 42 43 44 45 46 47 GND VCM GND VDD VDD GND A+ IN R8 OPT VCM E1 VCC 48 R10 OPT C13 0.1μF R11 OPT C16 2.2μF 2 VCM 3 4 C20 1.5pF 6 7 8 C22 1pF 9 10 GND GND ENC+ ENC− GND VDD VDD 11 12 13 14 15 16 C24 1.5pF AIN− R15 24.9Ω R13 24.9Ω 5 LTC6416CDDB 1 VCM CLHI GND OUT+ OUT− GND 11 GND 6 7 8 IN+ IN− CLLO 9 V+ 2 3 4 5 10 C17 680pF CLHI C19 0.1μF E2 R12 OPT C18 0.1μF J2 C21 OPT T1 1 APPLICATIONS INFORMATION 4 2 R14A 100Ω 5 C23 OPT TCM4−19+ • • 3 R14B 100Ω J3 C25 0.1μF C26 0.1μF VCC R17 OPT C11 0.1μF OVP R16 5.1k C28 0.1μF JP3 SHDN ADC JP4 DITH CLK 4 3 T2 MABA-007159-000000 VDD R19 51.1Ω • 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 VS VS 3.6V TO 20V E4 1 C32 10μF 25V E6 LT1963AEST-3.3 IN GND 2 OUT 3 C33 10μF 6.3V L1(opt.) BLM18PG221SN1D VCC OPT VDD L2 BLM18PG221SN1D E5 24LC025 1 OVP L3 BLM18PG221SN1D 2 R27 2k 3 4 8 7 6 5 C31 0.1μF R28 4.99k A0 A1 A2 VSS VCC WP SCL SDA R24 4.99k R25 4.99k GND R29 OPT 6416 F09 Figure 9. Demo Board DC1257B Schematic (Test Circuit B) 6416f LTC6416 PACKAGE DESCRIPTION DDB Package 10-Lead Plastic DFN (3mm × 2mm) (Reference LTC DWG # 05-08-1722 Rev Ø) 0.64 ± 0.05 (2 SIDES) 0.70 ± 0.05 2.55 ± 0.05 1.15 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.39 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 BAR TOP MARK (SEE NOTE 6) 2.00 ± 0.10 (2 SIDES) 0.64 ± 0.05 (2 SIDES) 5 0.25 ± 0.05 2.39 ± 0.05 (2 SIDES) BOTTOM VIEW—EXPOSED PAD PIN 1 R = 0.20 OR 0.25 × 45° CHAMFER (DDB10) DFN 0905 REV Ø 3.00 ± 0.10 (2 SIDES) R = 0.05 TYP R = 0.115 TYP 6 0.40 ± 0.10 10 1 0.200 REF 0.75 ± 0.05 0.50 BSC 0 – 0.05 6416f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC6416 TYPICAL APPLICATION DC1257B Simplified Schematic with Suggested Output Termination for Driving an LTC2208 16-Bit ADC at 140MHz 3.6V 680pF T1 TCM4-19+ 4 50Ω 0.1μF CLHI 3 2 R36 100Ω R15 100Ω IN+ – 2.2μF V+ 1.5pF 1pF AIN– 25Ω 1.5pF VCM AIN+ LTC2208 3.3V VCM OUT+ OUT– GND 25Ω + – LTC6416 IN GND C39 CLLO 0.01μF 16 DATA 6 1 6416 F05 CLOCK (130MHz) RELATED PARTS PART NUMBER LT1993-2/LT1993-4/ LT1993-10 DESCRIPTION 800MHz Differential Amplifier/ADC Drivers COMMENTS –72dBc IM3 at 70MHz 2VP-P Composite, AV = 2V/V, 4V/V, 10V/V –71dBc IM3 at 240MHz 2VP-P Composite, IS = 90mA, AV = 8dB, 14dB, 20dB, 26dB –74dBc IM3 at 140MHz 2VP-P Composite, IS = 50mA, AV = 8dB, 14dB, 20dB, 26dB –71dBc IM3 at 20MHz 2VP-P Composite, AV = 6dB, 12dB, 20dB Dual Version of the LTC6400-XX, AV = 8dB, 14dB, 20dB, 26dB Dual Version of the LTC6401-XX, AV = 8dB, 14dB, 20dB, 26dB Fixed Gain IF Amplifiers/ADC Drivers LTC6400-8/LTC6400-14/ 1.8GHz Low Noise, Low Distortion Differential LTC6400-20/LTC6400-26 ADC Drivers LTC6401-8/LTC6401-14/ 1.3GHz Low Noise, Low Distortion Differential LTC6401-20/LTC6401-26 ADC Drivers LT6402-6/LT6402-12/ LT6402-20 LTC6420-XX LTC6421-XX 300MHz Differential Amplifier/ADC Drivers Dual 1.8GHz Low Noise, Low Distortion Differential ADC Drivers Dual 1.3GHz Low Noise, Low Distortion Differential ADC Drivers Ultra-Low Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain Low Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain High Dynamic Range 7-bit Digitally Controlled IF VGA/ADC Driver Low Noise, Low Distortion Differential Amplifier/ ADC Driver Low Noise Rail-to-Rail Output Differential Amplifier/ ADC Driver Low Noise Rail-to-Rail Output Differential Amplifier/ ADC Driver 3GHz Rail-to-Rail Input Differential Amplifier/ ADC Driver Low Power Differential ADC Driver/Dual Selectable Gain Amplifier IF Amplifiers/ADC Drivers with Digitally Controlled Gain LT5514 LT5524 LT5554 OIP3 = 47dBm at 100MHz, Gain Range 10.5dB to 33dB 1.5dB steps OIP3 = 40dBm at 100MHz, Gain Range 4.5dB to 37dB 1.5dB steps OIP3 = 46dBm at 200MHz, Gain Range 1.725 to 17.6dB 0.125dB steps 16-Bit SNR and SFDR at 1MHz, Rail-to-Rail Outputs 16-Bit SNR and SFDR at 3MHz, Rail-to-Rail Outputs, eN = 2.8nV/√Hz 16-Bit SNR and SFDR at 10MHz, Rail-to-Rail Outputs, eN = 1.5nV/ √Hz, LTC6404-1 is unity-gain stable, LTC6404-2 is Gain-of-2 Stable –65dBc IM3 at 50MHz 2VP-P Composite, Rail-to-Rail Inputs, eN = 1.6nV/√Hz, 18mA –83dBc IM3 at 70MHz 2VP-P Composite, AV = 1, –1 or 2, 16mA, Excellent for Single-Ended to Differential Conversion 6416f LT 1108 • PRINTED IN USA Baseband Differential Amplifiers LT1994 LTC6403-1 LTC6404-1/LTC6404-2 LTC6406 LT6411 20 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008