LTC6601CUF-1-TRPBF

FEATURES n n n n n n LTC6601-1 Low Noise, 0.5% Tolerance, 5MHz to 28MHz, Pin Configurable Filter/ADC Driver DESCRIPTION The LTC®6601-1 is a very easy-to-use fully differential 2nd order active RC filter and driver. On-chip resistors, capacitors, and amplifier bandwidth are trimmed to provide consistent and repeatable filter characteristics. The filter characteristics are pin-strap configurable. Cutoff frequencies range from 5MHz to 28MHz. Gain is pin-strap programmable between –17dB and +17dB. A three-state BIAS pin is provided to adjust amplifier power consumption. Select between high performance, low power (50% power reduction), and standby modes with the BIAS pin. The LTC6601-1 is available in a compact 4mm × 4mm 16-pin leadless QFN package. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6271719. n n n n Pin Configurable Gain and Filter Response Up to 28MHz Few External Components Required Resistors Trimmed to 0.5% Typical Capacitors Trimmed to 0.5% Typical Very Low Noise: 80dB S/N in 100MHz Bandwidth Very Low Distortion (2VP-P): 1MHz: –100dBc 2nd, –123dBc 3rd 10MHz: –72dBc 2nd, –103dBc 3rd Adjustable Output Common Mode Voltage Rail-to-Rail Output Swing Power Configurability and Low Power Shutdown Tiny 0.75mm 20-Lead (4mm × 4mm) QFN Package APPLICATIONS n n n n n Differential Input A/D Converter Driver Antialiasing/Reconstruction Filter Single-Ended to Differential Conversion/Amplification Low Voltage, Low Noise, Differential Signal Processing Common Mode Voltage Translation TYPICAL APPLICATION 19MHz, 2nd Order Lowpass Filter. Gain = 6dB 10 20 1 19 18 17 16 15 5 0 Frequency Response LTC6601-1 – 3V 0.1μF GAIN (dB) –5 –10 –15 –20 –25 –30 1 10 FREQUENCY (MHz) 100 66011 TA01b + VIN 3V 2 3 4 5 + – 14 13 12 11 VOUT – + 0.1μF 6 7 8 9 10 66011 TA01a 66011f 1 LTC6601-1 ABSOLUTE MAXIMUM RATINGS (Note 1) PIN CONFIGURATION TOP VIEW IN4+ C5 C6 C7 C8 15 OUT– 14 V+ 21 13 V– 12 VOCM 11 OUT+ 6 IN4– 7 C1 8 C2 9 10 C3 C4 20 19 18 17 16 IN2+ 1 IN1+ – Total Supply Voltage (V + to V – ) ...............................5.5V Input Voltage (Any Pin) (Note 2) ..V + + 0.3V to V – – 0.3V Input Current (VOCM, BIAS)..................................±10mA Input Current (Pins 1, 5) (Note 2) ........................±20mA Input Current (Pins 2, 4) (Note 2) ........................±30mA Input Current (Pins 6, 20) (Note 2) ......................±15mA Input Current (Pins 7, 8, 9, 10, 16, 17, 18, 19) (Note 2)................................................................±10mA Output Short-Circuit Duration (Note 3) ............ Indefinite Operating Temperature Range (Note 4)....–40°C to 85°C Specified Temperature Range (Note 5) ....–40°C to 85°C Junction Temperature ........................................... 150°C Storage Temperature Range...................–65°C to 150°C 2 BIAS 3 IN1 4 IN2– 5 UF PACKAGE 20-LEAD (4mm 4mm) PLASTIC QFN TJMAX = 150°C, θJA = 37°C/W, θJC = 2°C/W EXPOSED PAD (PIN 21) IS V–, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC6601CUF-1#PBF LTC6601IUF-1#PBF TAPE AND REEL LTC6601CUF-1#TRPBF LTC6601IUF-1#TRPBF PART MARKING* 66011 66011 PACKAGE DESCRIPTION 20-Lead (4mm × 4mm) Plastic QFN 20-Lead (4mm × 4mm) Plastic QFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ DC ELECTRICAL CHARACTERISTICS + The l denotes the specifications which apply over the full operating – + SYMBOL VOSDIFF (Note 6) ΔVOSDIFF/ΔT (Note 6) RIN (Note 14) PARAMETER Amplifier Differential Offset Voltage (Input Referred) Ampifier Differential Offset Voltage Drift (Input Referred) CONDITIONS VS = 2.7V to 5.25V, BIAS = V+ BIAS = Floating VS = 2.7V to 5.25V l l temperature range, otherwise specifications are at TA = 25°C. V = 3V, V = 0V, VINCM = VOCM = mid-supply, BIAS tied to V or floating, ILOAD = 0, RBAL = 100k. The filter is configured for a gain of 1 unless otherwise noted. VS is defined as (V+ – V–). VOUTCM is defined as (VOUT+ + VOUT–)/2. VINCM is defined as (VINP + VINM)/2. VOUTDIFF is defined as (VOUT+ – VOUT–). VINDIFF is defined as (VINP – VINM). See Figure 1. MIN TYP ±0.25 ±0.25 1 MAX ±1 ±1.5 UNITS mV mV μV/°C Input Resistance, BIAS = V+ Single Ended Input Resistance, Pin 2 or Pin 4 VS = 3V Differential Input Resistance VS = 3V 133 200 Ω Ω 66011f 2 LTC6601-1 DC ELECTRICAL CHARACTERISTICS + The l denotes the specifications which apply over the full operating – + SYMBOL ΔRIN (Note 14) IB (Note 7) IOS (Note 7) VINCM (Note 8) PARAMETER CONDITIONS l temperature range, otherwise specifications are at TA = 25°C. V = 3V, V = 0V, VINCM = VOCM = mid-supply, BIAS tied to V or floating, ILOAD = 0, RBAL = 100k. The filter is configured for a gain of 1 unless otherwise noted. VS is defined as (V+ – V–). VOUTCM is defined as (VOUT+ + VOUT–)/2. VINCM is defined as (VINP + VINM)/2. VOUTDIFF is defined as (VOUT+ – VOUT–). VINDIFF is defined as (VINP – VINM). See Figure 1. MIN TYP ±0.25 –50 –25 –25 –12.5 ±1 ±1 0 0 ±10 ±5 MAX UNITS Ω μA μA μA μA Input Resistance Match, BIAS = V+ Single Ended Input Resistance, Pin 2 or Pin 4 VS = 3V Internal Amplifier Input Bias Internal Amplifier Input Offset Input Signal Common Mode Range (VINP + VINM)/2 BIAS = V+, VOCM = 1.5V BIAS = V+, VOCM = 2.5V BIAS Pin Floating, VOCM = 1.5V BIAS Pin Floating, VOCM = 2.5V CMRRI (Notes 9, 14) CMRRO (Notes 9, 14) PSRR (Note 10) Input Common Mode Rejection Ratio (Amplifier Input Referred) ΔVINCM/ΔVOSDIFF ΔVINCM = 2.5V Output Common Mode Rejection Ratio (Amplifier Input Referred) ΔVOCM/ΔVOSDIFF ΔVOCM = 1V Power Supply Rejection Ratio (Amplifier Input Referred) ΔVS /ΔVOSDIFF BIAS = V+ BIAS Pin Floating VS = 2.7V to 5V VS = 2.7V to 5V BIAS = V+ BIAS = Floating BIAS = V+ BIAS = Floating l l l l VS = 3V VS = 5V VS = 3V VS = 5V l l l l 0 0 0 0 1.7 4.7 1.8 4.8 V V V V VS = 5V 74 dB VS = 5V 70 dB VS = 2.7V to 5V VS = 2.7V to 5V l l l 66 60 46 95 95 60 1 dB dB dB V/V ±0.3 –40 –40 ±15 ±20 % dB dB mV mV μV/°C μV/°C 1.7 4 1.8 4 V V V V kΩ V PSRRCM (Note 10) Common Mode Power Supply Rejection Ratio (ΔVS /ΔVOSCM) VS = 2.7V to 5V gcm Common Mode Gain (ΔVOUTCM/ΔVOCM) ΔVOCM = 2V Common Mode Gain Error = 100 • (gcm – 1) ΔVOCM = 2V BAL Output Balance (ΔVOUTCM/ΔVOUTDIFF) Single-Ended Input Differential Input Common Mode Offset Voltage (VOUTCM – VOCM) Common Mode Offset Voltage Drift (VOUTCM – VOCM) Output Signal Common Mode Range (Voltage Range for the VOCM Pin) VS = 5V VS = 5V ΔVOUTDIFF = 2V VS = 5V VS = 5V VS = 2.7V to 5V VS = 2.7V to 5V VS = 2.7V to 5V VS = 2.7V to 5V VS = 3V VS = 5V VS = 3V VS = 5V VS = 3V VS = 3V BIAS = V+ BIAS = Floating BIAS = V+ BIAS = Floating BIAS = V+ BIAS = V+ BIAS Pin Floating BIAS Pin Floating l l l l l l l l l l l l l ±0.1 –62 –63 ±5 ±8 5 20 1.1 1.1 1.1 1.1 12.5 1.475 18 1.5 VOSCM ΔVOSCM/ΔT VOUTCMR (Note 8) RINVOCM VMID Input Resistance, VOCM Pin Voltage at the VOCM PIn 23.5 1.525 66011f 3 LTC6601-1 DC ELECTRICAL CHARACTERISTICS + The l denotes the specifications which apply over the full operating – + SYMBOL VOUT PARAMETER Output Voltage, High, Either Output Pin (Note 11) CONDITIONS VS = 3V, IL = 0mA VS = 3V, IL = –5mA VS = 3V, IL = –20mA VS = 5V, IL = 0mA VS = 5V, IL = –5mA VS = 5V, IL = –20mA BIAS = V+ BIAS = V+ BIAS = V+ BIAS = V+ BIAS = V+ BIAS = V+ l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l temperature range, otherwise specifications are at TA = 25°C. V = 3V, V = 0V, VINCM = VOCM = mid-supply, BIAS tied to V or floating, ILOAD = 0, RBAL = 100k. The filter is configured for a gain of 1 unless otherwise noted. VS is defined as (V+ – V–). VOUTCM is defined as (VOUT+ + VOUT–)/2. VINCM is defined as (VINP + VINM)/2. VOUTDIFF is defined as (VOUT+ – VOUT–). VINDIFF is defined as (VINP – VINM). See Figure 1. MIN TYP 245 285 415 350 390 550 240 290 470 370 430 650 120 135 195 175 200 270 110 120 170 150 170 225 ±45 ±60 2.7 32.9 33.1 33.9 16.0 16.2 16.9 0.34 0.35 0.55 V– V– + 1.0 V– + 2.3 100 V– + 1.05 150 V– + 1.12 400 400 ±65 ±90 5.25 43 43.5 45 25 25.5 26.5 0.9 1 1.6 V– + 0.4 V– + 1.5 V+ 200 V– + 1.25 MAX 450 525 750 625 700 1000 450 525 850 675 775 1100 225 250 350 325 360 475 200 225 300 270 300 400 UNITS mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mA mA V mA mA mA mA mA mA mA mA mA V V V kΩ V ns ns VS = 3V, IL = 0mA, BIAS Pin Floating VS = 3V, IL = –5mA, BIAS Pin Floating VS = 3V, IL = –20mA, BIAS Pin Floating VS = 5V, IL = 0mA, BIAS Pin Floating VS = 5V, IL = –5mA, BIAS Pin Floating VS = 5V, IL = –20mA, BIAS Pin Floating Output Voltage, Low, Either Output Pin (Note 11) VS = 3V, IL = 0mA VS = 3V, IL = 5mA VS = 3V, IL = 20mA VS = 5V, IL = 0mA VS = 5V, IL = 5mA VS = 5V, IL = 20mA BIAS = V+ BIAS = V+ BIAS = V+ BIAS = V+ BIAS = V+ BIAS = V+ VS = 3V, IL = 0mA, BIAS Pin Floating VS = 3V, IL = 5mA, BIAS Pin Floating VS = 3V, IL = 20mA, BIAS Pin Floating VS = 5V, IL = 0mA, BIAS Pin Floating VS = 5V, IL = 5mA, BIAS Pin Floating VS = 5V, IL = 20mA, BIAS Pin Floating ISC VS IS Output Short-Circuit Current, Either Output Pin (Note 12) Supply Voltage Range Supply Current, BIAS Pin Tied to V+ VS = 2.7V VS = 3V VS = 5V VS = 2.7V VS = 3V VS = 5V VS = 2.7V VS = 3V VS = 5V VS = 2.7V to 5V VS = 2.7V to 5V VS = 2.7V to 5V VS = 2.7V to 5V VS = 2.7V to 5V VS = 3V, VSHDN = 0.25V to 3V VS = 3V, VSHDN = 3V to 0.25V VS = 3V VS = 5V Supply Current, BIAS Pin Floating ISHDN Supply Current, BIAS Pin Tied to V– VBIASSD VBIASLP (Note 13) VBIASHP RBIAS VBIAS tON tOFF BIAS Input Pin Range for Shutdown BIAS Input for Half Power Operation BIAS Input for High Performance Operation BIAS Input Resistance BIAS Float Voltage Turn-On Time Turn-Off Time 66011f 4 LTC6601-1 AC ELECTRICAL CHARACTERISTICS + The l d–enotes the specifications which apply over the full operating + SYMBOL GAIN PARAMETER Filter Gain, See Figure 2, BIAS Pin Tied to V+, AC Gain Measurements Relative to 1MHz CONDITIONS ΔVIN = ±0.25V, fTEST = DC (Note 14) VIN = 600mVP-P, fTEST = 1MHz VIN = 600mVP-P, fTEST = 2MHz VIN = 600mVP-P, fTEST = 5MHz VIN = 600mVP-P, fTEST = 10MHz VIN = 600mVP-P, fTEST = 14.45MHz VIN = 600mVP-P, fTEST = 20MHz VIN = 600mVP-P, fTEST = 50MHz ΔVIN = ±0.25V, fTEST = DC VIN = 600mVP-P, fTEST = 1MHz VIN = 600mVP-P, fTEST = 2MHz VIN = 600mVP-P, fTEST = 5MHz VIN = 600mVP-P, fTEST = 10MHz VIN = 600mVP-P, fTEST = 14.45MHz VIN = 600mVP-P, fTEST = 20MHz VIN = 600mVP-P, fTEST = 50MHz BW = 100MHz BW = 20MHz BW = 100MHz BW = 20MHz HD2, Single-Ended Input HD3, Single-Ended Input HD2, Differential Input HD3, Differential Input ΔVIN = ±0.25V, fTEST = DC (Note 14) VIN = 600mVP-P, fTEST = 1MHz VIN = 600mVP-P, fTEST = 2MHz VIN = 600mVP-P, fTEST = 5MHz VIN = 600mVP-P, fTEST = 10MHz VIN = 600mVP-P, fTEST = 14.45MHz VIN = 600mVP-P, fTEST = 20MHz VIN = 600mVP-P, fTEST = 50MHz ΔVIN = ±0.25V, fTEST = DC VIN = 600mVP-P, fTEST = 1MHz VIN = 600mVP-P, fTEST = 2MHz VIN = 600mVP-P, fTEST = 5MHz VIN = 600mVP-P, fTEST = 10MHz VIN = 600mVP-P, fTEST = 14.45MHz VIN = 600mVP-P, fTEST = 20MHz VIN = 600mVP-P, fTEST = 50MHz BW = 100MHz BW = 20MHz BW = 100MHz BW = 20MHz HD2, Single-Ended Input HD3, Single-Ended Input HD2, Differential Input HD3, Differential Input l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l temperature range, otherwise specifications are at TA = 25°C. V = 3V, V = 0V, VINCM = VOCM = mid-supply, VBIAS is tied to V or floating, unless otherwise noted. (See Figure 2 for the AC test configuration.) VS is defined as (V+ – V–). VOUTCM is defined as (VOUT+ + VOUT–)/2. VICM is defined as (VINP + VINM)/2. VOUTDIFF is defined as (VOUT+ – VOUT–). VINDIFF is defined as (VINP – VINM). MIN –0.25 –0.08 –0.01 –0.54 –2.75 –7.14 –23.70 –6.0 –12.0 –30.7 –67.6 –100.1 –127.3 TYP ±0.05 0 0.02 0.11 –0.34 –2.35 –6.24 –21.70 0 –5.4 –10.8 –28.2 –62.6 –94.1 –122.3 –169.3 71 54 80 82.3 –70 –103 –72 –103 –120 –0.25 –0.08 –0.01 –0.54 –2.90 –7.43 –23.90 –6.0 –12.4 –31.8 –70.2 –103.5 –130.1 ±0.05 0 0.02 0.11 –0.34 –2.50 –6.53 –21.90 0 –5.5 –11.2 –29.3 –65.2 –97.5 –125.1 –173.6 78 58 79 81.7 –64 –71 –70 –72 –120 0.25 0.12 0.23 –0.14 –2.10 –5.63 –19.90 –4.8 –10.0 –26.8 –60.2 –91.5 –120.1 MAX 0.25 0.12 0.23 –0.14 –1.95 –5.34 –19.70 –4.8 –9.6 –25.7 –57.6 –88.1 –117.3 UNITS dB dB dB dB dB dB dB dB Deg Deg Deg Deg Deg Deg Deg Deg μVRMS μVRMS dB dB dBc dBc dBc dBc ppm/°C dB dB dB dB dB dB dB dB Deg Deg Deg Deg Deg Deg Deg Deg μVRMS μVRMS dB dB dBc dBc dBc dBc ppm/°C PHASE Filter Phase, See Figure 2, BIAS Pin Tied to V+ NOISE SNR Wide Band Output Noise, 14.45MHz Cutoff, BIAS Pin Tied to V+ BIAS Pin Tied to V+ DISTORTION VIN = 2VP-P , 10MHz, BIAS Pin Tied to V+ fO TC GAIN Cutoff Frequency Temperature Coefficient Filter Gain, See Figure 2, BIAS Pin Floating (Remaining AC Measurements Relative to 1MHz) PHASE Filter Phase, See Figure 2, BIAS Pin Floating NOISE SNR Distortion Output Noise, See Figure 2, BIAS Pin Floating BIAS Pin Floating VIN = 2VP-P , 10MHz, BIAS Pin Floating fO TC Cutoff Frequency Temperature Coefficient 66011f 5 LTC6601-1 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All pins are protected by steering diodes to either supply. If any pin is driven beyond the part’s supply voltage, the excess input current (current in excess of what it takes to drive that pin to the supply rail) should be limited to less than 10mA. Note 3: A heat sink may be required to keep the junction temperature below the Absolute Maximum Rating when the output is shorted indefinitely. Long-term application of output currents in excess of the Absolute Maximum Ratings may impair the life of the device. Note 4: The LTC6601C/LTC6601I are guaranteed functional over the operating temperature range –40°C to 85°C. Note 5: The LTC6601C is guaranteed to meet specified performance from 0°C to 70°C. The LTC6601C is designed, characterized, and expected to meet specified performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. The LTC6601I is guaranteed to meet specified performance from –40°C to 85°C. Note 6: Output referred voltage offset is a function of the low frequency gain of the LTC6601. To determine output referred voltage offset, or output voltage offset drift, multiply this specification by the noise gain (1 + GAIN). See Applications Information for more details. Note 7: Input bias current is defined as the average of the currents flowing into the noninverting and inverting inputs of the internal amplifier and is calculated from measurements made at the pins of the IC. Input offset current is defined as the difference of the currents flowing into the noninverting and inverting inputs of the internal amplifier and is calculated from measurements made at the pins of the IC. Note 8: Input common mode range is tested using the test circuit of Figure 1 by measuring the differential DC gain with VICM = mid-supply, and with VICM at the input common mode range limits listed in the Electrical Characteristics table, verifying the differential gain has not deviated from the mid-supply common mode input case by more than 1%, and the common mode offset (VOCMOS) has not deviated from the mid-supply common mode offset by more than ±10mV. The voltage range for the output common mode range is tested using the test circuit of Figure 1 by measuring the differential DC gain with VOCM = mid-supply, and again with a voltage set on the VOCM pin at the Electrical Characteristics table limits, checking the differential gain has not deviated from the mid-supply common mode input case by more than 1%, and that the common mode offset (VOCMOS) has not deviated by more than ±10mV from the mid-supply case. Note 9: Input CMRR is defined as the ratio of the change in the input common mode voltage at the amplifier input to the change in differential input referred voltage offset. Output CMRR is defined as the ratio of the change in the voltage at the VOCM pin to the change in differential input referred voltage offset. Note 10: Power supply rejection (PSRR) is defined as the ratio of the change in supply voltage to the change in differential input referred voltage offset. Common mode power supply rejection (PSRRCM) is defined as the ratio of the change in supply voltage to the change in the common mode offset, VOUTCM /VOCM. Note 11: Output swings are measured as differences between the output and the respective power supply rail. Note 12: Extended operation with the output shorted may cause junction temperatures to exceed the 150°C limit and is not recommended. Note 13: Floating the BIAS pin will reliably place the part into the halfpower mode. The pin does not have to be driven. Care should be taken, however, to prevent external leakage currents in or out of this pin from pulling the pin into an undesired state. Note 14: The variable contact resistance of the high speed test equipment limits the accuracy of this test. These parameters only show a typical value, or conservative minimum and maximum value. 66011f 6 LTC6601-1 TYPICAL PERFORMANCE CHARACTERISTICS Low Power Supply Current vs Temperature and Supply Voltage 18.0 VINCM = VOCM = MID-SUPPLY BIAS PIN FLOATING 17.5 17.0 ICC (mA) 16.5 3V 16.0 15.5 15.0 –50 31 0.1 –25 25 75 0 50 TEMPERATURE (°C) 100 125 30 –50 –25 25 75 0 50 TEMPERATURE (°C) 100 125 0 –50 –25 25 75 0 50 TEMPERATURE (°C) 100 125 2.7V 34 5V 3V ICC (mA) 2.7V 32 ICC (mA) 33 35 VINCM = VOCM = MID-SUPPLY BIAS PIN TIED TO V+ 5V High Performance Supply Current vs Temperature and Supply Voltage 0.8 0.7 0.6 0.5 0.4 Shutdown Supply Current vs Temperature and Supply Voltage VINCM = VOCM = MID-SUPPLY BIAS PIN TIED TO V – 5V 3V 0.3 0.2 2.7V 66011 G01 66011 G02 66011 G03 Supply Current vs Bias Pin Voltage and Temperature 50 VINCM = VOCM = MID-SUPPLY VS = 3V 40 1 Shutdown Supply Current vs Supply Voltage and Temperature 100 125°C 10 –40°C 0.1 25°C ICC (mA) 1 Low Power Mode Supply Current vs Supply Voltage and Temperature 125°C ICC (mA) ICC (mA) 30 20 –40°C 0.1 25°C 0.01 0.01 10 –40°C 25°C 125°C 0 1 2 3 0.5 1.5 2.5 BIAS PIN VOLTAGE WITH RESPECT TO V– (V) 66011 G04 VINCM = VOCM = MID-SUPPLY BIAS PIN TIED TO V– 0.001 0 1 2 4 3 SUPPLY VOLTAGE (V) 5 66011 G05 VINCM = VOCM = MID-SUPPLY BIAS PIN FLOATING 0.001 0 1 2 4 3 SUPPLY VOLTAGE (V) 5 66011 G06 0 High Performance Supply Current vs Supply Voltage and Temperature 100 125°C VOS INPUT REFERRED (mV) 10 –40°C 1.00 High Performance Mode Differential VOS vs Temperature VS = 3V 0.75 VINCM = VOCM = MID-SUPPLY BIAS PIN TIED TO V+ 0.50 5 REPRESENTATIVE UNITS 0.25 0.00 –0.25 –0.50 –0.75 –1.00 –50 –25 0 50 75 25 TEMPERATURE (°C) 100 125 1.00 Low Power Mode Differential VOS vs Temperature VS = 3V 0.75 VINCM = VOCM = MID-SUPPLY BIAS PIN FLOATING 0.50 5 REPRESENTATIVE UNITS 0.25 0.00 –0.25 –0.50 –0.75 –1.00 –50 –25 0 50 75 25 TEMPERATURE (°C) 100 125 ICC (mA) 1 0.1 25°C 0.01 VINCM = VOCM = MID-SUPPLY BIAS PIN TIED TO V+ 0.001 0 1 3 2 4 SUPPLY VOLTAGE (V) 5 66011 G07 66011 G08 VOS INPUT REFERRED (mV) 66011 G09 66011f 7 LTC6601-1 TYPICAL PERFORMANCE CHARACTERISTICS High Performance Common Mode VOS vs Temperature 10 15 10 5 5 VOSCM (mV) VOSCM (mV) 0 0 –5 –5 V = 3V S VINCM = VOCM = MID-SUPPLY BIAS PIN TIED TO V+ 5 REPRESENTATIVE UNITS –10 –50 –25 0 50 75 25 TEMPERATURE (°C) VS = 3V –10 VINCM = VOCM = MID-SUPPLY BIAS PIN FLOATING 5 REPRESENTATIVE UNITS –15 –50 –25 0 50 75 25 TEMPERATURE (°C) –25 VS = 3V VINCM = VOCM = MID-SUPPLY –25 0 50 75 25 TEMPERATURE (°C) 100 125 IBIAS (μA) –15 HIGH PERFORMANCE MODE (BIAS PIN TIED TO V+) Low Power Common Mode VOS vs Temperature –5 Internal Amplifier Input Bias Current vs Temperature LOW POWER MODE (BIAS PIN FLOATING) –10 –20 100 125 100 125 –30 –50 66011 G10 66011 G11 66011 G12 BIAS Pin Input Resistance vs Temperature 200 VS = 3V VINCM = VOCM = MID-SUPPLY 175 FLOAT VOLTAGE (V) RESISTANCE (Ω) 1.15 1.20 BIAS Pin Float Voltage vs Temperature 1.0050 VS = 3V VINCM = VOCM = MID-SUPPLY RESISTANCE/RNOMINAL (Ω/Ω) Filter Input Resistance vs Temperature VS = 3V VINCM = VOCM = MID-SUPPLY RNOMINAL = 200Ω DIFFERENTIAL 1.0025 RNOMINAL = 133.3Ω SINGLE-ENDED SEE FIGURE 1 FOR CONFIGURATION 150 1.10 1.0000 125 1.05 0.9975 SINGLE-ENDED DIFFERENTIAL –25 0 50 75 25 TEMPERATURE (°C) 100 125 100 –50 –25 0 50 75 25 TEMPERATURE (°C) 100 125 1.00 –50 –25 0 50 75 25 TEMPERATURE (°C) 100 125 0.9950 –50 66011 G13 66011 G14 66011 G15 Low Frequency Gain vs Temperature 1.010 VS = 3V VINCM = VOCM = MID-SUPPLY 5 REPRESENTATIVE UNITS 10 High Performance Mode Frequency Response of 12 Possible Filter Configurations 10 Low Power Mode Frequency Response of 12 Possible Filter Configurations 1.005 0 GAIN (V/V) 1.000 GAIN (dB) GAIN (dB) 0 –10 –10 0.995 –20 VS = 3V VINCM = VOCM = MID-SUPPLY BIAS PIN TIED TO V+ 1 10 FREQUENCY (MHz) 100 66011 G17 –20 VS = 3V VINCM = VOCM = MID-SUPPLY BIAS PIN FLOATING 1 10 FREQUENCY (MHz) 100 66011 G18 0.990 –50 –25 0 50 75 25 TEMPERATURE (°C) 100 125 –30 0.1 –30 0.1 66011 G16 66011f 8 LTC6601-1 TYPICAL PERFORMANCE CHARACTERISTICS High Performance Mode Gain and Phase Repeatability of 10 Random Units 0.20 VS = 3V 0.15 VINCM = VOCM = MID-SUPPLY BIAS PIN TIED TO V+ SEE FIGURE 2 0.10 ϕMAX – ϕAVERAGE 0.05 MAX – AVERAGE 0 –0.05 –0.10 –0.15 –0.20 0.1 1 10 FREQUENCY (MHz) MIN – AVERAGE ϕMIN – ϕAVERAGE 4 3 GAIN DEVIATION (dB) 2 1 0 –1 –2 –3 –4 100 66011 G19 Low Power Mode Gain and Phase Repeatability of 10 Random Units 0.20 VS = 3V 0.15 VINCM = VOCM = MID-SUPPLY BIAS PIN FLOATING SEE FIGURE 1 0.10 ϕMAX – ϕAVERAGE 0.05 0 –0.05 –0.10 –0.15 –0.20 0.1 1 10 FREQUENCY (MHz) MIN – AVERAGE ϕMIN – ϕAVERAGE MAX – AVERAGE 4 3 2 1 0 –1 –2 –3 –4 100 66011 G20 PHASE DEVIATION (DEG) PHASE DEVIATION (DEG) GAIN DEVIATION (dB) High Performance Mode Gain Error of 10 Random Units Normalized to 1MHz 3 VS = 3V VICM = VOCM = MID-SUPPLY 2 BIAS PIN TIED TO V+ 10 RANDOM UNITS PLOTTED TA = 25°C 1 +SPECIFICATION 0 –1 –SPECIFICATION –2 –3 –2 –3 1 10 FREQUENCY (MHz) 100 66011 G21 Low Power Mode Gain Error of 10 Random Units Normalized to 1MHz 3 VS = 3V VICM = VOCM = MID-SUPPLY 2 BIAS PIN FLOATING 10 RANDOM UNITS PLOTTED TA = 25°C 1 +SPECIFICATION 0 –SPECIFICATION –1 15 High Performance Mode Phase Error of 10 Random Units VS = 3V VICM = VOCM = MID-SUPPLY 10 BIAS PIN TIED TO V+ 10 RANDOM UNITS PLOTTED TA = 25°C 5 +SPECIFICATION 0 –5 PHASE ERROR (DEG) GAIN ERROR (dB) GAIN ERROR (dB) –SPECIFICATION –10 –15 1 10 FREQUENCY (MHz) 100 66011 G22 1 10 FREQUENCY (MHz) 100 66011 G23 Low Power Mode Phase Error of 10 Random Units 15 VS = 3V VICM = VOCM = MID-SUPPLY 10 BIAS PIN FLOATING 10 RANDOM UNITS PLOTTED TA = 25°C 5 +SPECIFICATION 0 –5 –SPECIFICATION 5 4 3 2 VOUTDIFF (V) 1 0 –1 –2 –3 –4 –15 1 10 FREQUENCY (MHz) 100 66011 G24 Turn On and Turn Off Transient Response VS = 5V 1.6 BIAS PIN 1.4 1.2 VOUTDIFF (V) 1.0 0.8 0.6 0.4 VOUTDIFF 0 1 2 3 4 TIME (μs) 5 6 66011 G25 Pulse Response 2 VS = 3V PHASE ERROR (DEG) 1 VBIAS PIN (V) 0 –1 –10 0.2 0 –2 0 1 2 3 4 5 TIME (μs) 6 7 8 –5 66011 G26 66011f 9 LTC6601-1 TYPICAL PERFORMANCE CHARACTERISTICS Differential Output Noise 100 NOISE SPECTRAL DENSITY (nV/√Hz) VS = 3V FIGURE 2 INTEGRATED NOISE, BIAS PIN FLOATING INTEGRATED NOISE, BIAS TIED TO V+ 10 SPECTRAL DENSITY, BIAS PIN FLOATING 10 100 –60 Distortion vs Frequency VS = 5V VIN = 2VP-P INPUT –70 VICM = VOCM = MID-SUPPLY BIAS PIN TIED TO V+ –80 FIGURE 2 HD2 –90 –100 HD3 –110 –120 –130 0.1 SINGLE ENDED INPUT DIFFERENTIAL INPUT 1 10 100 FREQUENCY (MHz) 66011 G28 Distortion vs Frequency –60 VS = 5V VIN = 2VP-P INPUT –70 V ICM = VOCM = MID-SUPPLY –80 BIAS PIN FLOATING FIGURE 2 –90 –100 –110 –120 –130 0.1 INTEGRATED NOISE (μVRMS) SPECTRAL DENSITY, BIAS TIED TO V+ 1 100 66011 G27 HARMONIC (dBc) HARMONIC (dBc) 1 0.001 SINGLE ENDED INPUT DIFFERENTIAL INPUT 1 10 FREQUENCY (MHz) 100 66011 G29 0.01 0.1 1 FREQUENCY (MHz) 10 % Change of fO vs Temperature 0.5 0.5 0 0 CHANGE OF fO (%) –0.5 GAIN (dB) –0.5 Passband Gain and Phase vs Temperature 0 –15 –30 PHASE (DEG) PHASE –1.0 –1.5 –2.0 VS = 3V VICM = VOCM = MID-SUPPLY –2.5 BIAS PIN TIED TO V+ TEMPERATURES PLOTTED: –45°C, –10°C, 25°C, 70°C, 95°C, 125°C –3.0 1 10 FREQUENCY (MHz) 66011 G31 Gain Error Relative to 1MHz vs Temperature 3 VS = 3V VICM = VOCM = MID-SUPPLY 2 BIAS PIN TIED TO V+ TEMPERATURES PLOTTED: –45°C, –10°C, 25°C, 1 70°C, 95°C, 125°C +SPECIFICATION 0 –1 –SPECIFICATION –2 –3 GAIN –45 –60 –75 –90 –1.0 –1.5 –2.0 –50 –25 0 50 75 25 TEMPERATURE (°C) 100 125 –105 GAIN ERROR (dB) 1 10 FREQUENCY (MHz) 100 66011 G32 66011 G30 Phase Error vs Temperature 15 VS = 3V VICM = VOCM = MID-SUPPLY 10 BIAS PIN TIED TO V+ TEMPERATURES PLOTTED: –45°C, –10°C, 25°C, 5 70°C, 95°C, 125°C +SPECIFICATION 0 –5 900 800 700 FREQUENCY Normalized 100Ω Resistor Trim AVERAGE = 100Ω STD. DEV = 0.19Ω 1000 Normalized 125Ω Resistor Trim AVERAGE = 125Ω 900 STD. DEV = 0.22Ω 800 700 FREQUENCY 600 500 400 300 200 100 0 PHASE ERROR (dB) 600 500 400 300 200 –SPECIFICATION –10 100 –15 1 10 FREQUENCY (MHz) 100 66011 G33 0 0.993 0.997 1.001 1.005 NORMALIZED RESISTANCE 1.009 66011 G34 0.99 0.994 0.998 1.002 1.006 NORMALIZED RESISTANCE 1.01 66011 G35 66011f 10 LTC6601-1 TYPICAL PERFORMANCE CHARACTERISTICS Normalized 200Ω Resistor Trim 1000 AVERAGE = 200Ω 900 STD. DEV = 0.37Ω 800 700 FREQUENCY FREQUENCY 600 500 400 300 200 100 0 0.99 0.994 0.998 1.002 1.006 NORMALIZED RESISTANCE 1.01 66011 G36 Normalized Input 400Ω Resistor Trim 900 AVERAGE = 400.01Ω 800 STD. DEV = 1.0Ω 700 600 FREQUENCY 500 400 300 200 100 0 0.99 0.994 0.998 1.002 1.006 NORMALIZED RESISTANCE 1.01 66011 G37 Normalized Feedback 400Ω Resistor Trim 1000 AVERAGE = 400.01Ω 900 STD. DEV = 0.87Ω 800 700 600 500 400 300 200 100 0 0.99 0.994 0.998 1.002 1.006 NORMALIZED RESISTANCE 1.01 66011 G38 Normalized 21.1pF Capacitor Trim 1200 1000 800 FREQUENCY FREQUENCY 600 400 200 0 AVERAGE = 21.1pF STD. DEV = 0.07pF 1000 Normalized 33.3pF Capacitor Trim AVERAGE = 33.3pF 900 STD. DEV = 0.09pF 800 700 600 500 400 300 200 100 FREQUENCY 1200 1000 800 600 400 200 0 0.988 0.993 0.999 1.005 1.010 NORMALIZED CAPACITANCE 1.016 Normalized 48.2pF Capacitor Trim AVERAGE = 48.2pF STD. DEV = 0.08pF 0.984 0.990 0.997 1.003 1.009 NORMALIZED CAPACITANCE 1.015 66011 G39 0 0.992 0.995 0.998 1.001 1.004 1.007 1.010 NORMALIZED CAPACITANCE 66011 G41 66011 G40 Normalized 81.5pF Capacitor Trim 1000 AVERAGE = 81.5pF 900 STD. DEV = 0.1pF 800 700 FREQUENCY 600 500 400 300 200 100 0 0.993 0.996 0.999 1.002 1.004 1.007 1.010 NORMALIZED CAPACITANCE 66011 G42 Normalized 10.55pF Capacitor Trim 400 AVERAGE = 10.55pF 350 STD. DEV = 0.03pF 300 FREQUENCY FREQUENCY 250 200 150 100 50 0 0.987 0.991 0.996 1.000 1.005 1.009 1.014 NORMALIZED CAPACITANCE 66011 G43 Normalized 16.1pF Capacitor Trim 350 300 250 200 150 100 50 0 0.988 0.992 0.995 0.999 1.003 1.006 1.010 1.014 NORMALIZED CAPACITANCE 66011 G44 AVERAGE = 16.1pF STD. DEV = 0.05pF 66011f 11 LTC6601-1 PIN FUNCTIONS (Refer to the Block Diagram) IN1+, IN2+, IN4+ (Pins 2, 1, 20): Input to a trimmed 100Ω, 200Ω, 400Ω resistor which feeds a noninverting summing node. Can accept an input signal, be floated or tied to OUT–. For best performance, stray capacitance should be kept as low as possible by keeping printed circuit connections as short and direct as possible. If necessary, strip back the surrounding ground plane away from these pins. BIAS (Pin 3): Input to a three-state comparator whose three states allow the user to tailor amplifier power. The pin impedance appears as a 150k resistor whose default open-circuit potential is 1.15V with respect to the V– power supply. If BIAS is driven to within 0.4V of the V– supply, the amplifier is placed into a low power shutdown, consuming typically 350μA. When BIAS is floated, the amplifier operates in its low power active state. Forcing the pin 2.3V above V– places the part into the high performance active state. See Applications Information for more detail. IN1–, IN2–, IN4– (Pins 4, 5, 6): Input to a trimmed 100Ω, 200Ω, 400Ω resistor which feeds an inverting summing node. Can accept an input signal, be floated or tied to OUT+. For best performance, it is highly recommended that stray capacitance be kept to as low as possible by keeping printed circuit connections as short and direct as possible, and if necessary, stripping back nearby surrounding ground plane away from these pins. C1, C2 (Pins 7, 8): Input to a trimmed 16.1pF 33.3pF , capacitor which feeds a noninverting summing node. Typically, either float or tie to OUT–. If either of these pins is tied to a low impedance source other than OUT–, a resistance of at least 25Ω should be placed in series. For best performance, it is highly recommended that stray capacitance be kept to as low as possible by keeping printed circuit connections as short and direct as possible, and if necessary, stripping back nearby surrounding ground plane away from these pins. C3, C4 (Pins 9, 10): Input to a trimmed 10.55pF 21.1pF , capacitor which feeds the amplifier inverting summing node. Typically, either float or tie to OUT+. For best performance, it is highly recommended that stray capacitance be kept to as low as possible by keeping printed circuit connections as short and direct as possible, and if necessary, stripping back nearby surrounding ground plane away from these pins. OUT+, OUT– (Pins 11, 15): Output Pins. Besides driving the internal feedback network, each pin can drive an additional 50Ω to ground with typical short-circuit current limiting of ±65mA. Capacitive loading of these pins should be minimized by resistively decoupling the outputs from the load with at least 25Ω. VOCM (Pin 12): Output Common Mode Reference Voltage. The voltage on VOCM sets the output common mode voltage level (which is defined as the average of the voltages on the OUT+ and OUT– pins). The VOCM pin is the midpoint of an internal resistive voltage divider between the supplies, developing a (default) mid-supply voltage potential to maximize output signal swing. The VOCM pin can be overdriven by an external voltage reference capable of driving the input impedance presented by the VOCM pin. The VOCM pin has an input resistance of approximately 18k to a mid-supply potential. It should be bypassed with a high quality ceramic bypass capacitor (for instance of X7R dielectric) of at least 0.01μF (unless using symmetrical , split supplies, then connect directly to a low impedance, low noise ground plane) to minimize common mode noise from being converted to differential noise by impedance mismatches both externally and internally to the IC. 66011f 12 LTC6601-1 PIN FUNCTIONS (Refer to the Block Diagram) V+, V– (Pins 14, 13): Power Supply Pins. It is critical that close attention be paid to supply bypassing. For single supply applications (Pin 13 grounded), it is recommended that a high quality 0.1μF surface mount ceramic bypass capacitor (X7R dielectric for instance) be placed between Pins 14 and 13, with direct short connections. Pin 13 should be tied directly to a low impedance ground plane with minimal routing. For dual (split) power supplies, it is recommended that at least two additional high quality 0.1μF ceramic capacitors are used to bypass V+ to ground and V– to ground, again with minimal routing. For driving large loads (< 200Ω), additional bypass capacitance may be added for optimal performance. Keep in mind that small geometry (e.g., 0603) surface mount ceramic capacitors have a much lower ESL than do leaded capacitors, and perform best in high speed applications. C7, C8 (Pins 17, 16): Input to a trimmed 10.55pF 21.1pF , capacitor which feeds the amplifier noninverting summing node. Typically, either float or tie to OUT–. For best performance, stray capacitance should be kept as low as possible by keeping printed circuit connections as short and direct as possible.If necessary, strip back the surrounding ground plane away from these pins. C5, C6 (Pins 19, 18): Input to a trimmed 16.1pF 33.3pF , capacitor which feeds an inverting summing node. Typically, either float or tie to OUT+. If either of these pins are tied to a low impedance source other than OUT+, a resistance of at least 25Ω should be placed in series. For best performance, it is highly recommended that stray capacitance be kept to as low as possible by keeping printed circuit connections as short and direct as possible, and if necessary, stripping back nearby surrounding reference plane away from these pins. Exposed Pad (Pin 21): Always tie the underlying Exposed Pad to V– (Pin 13). If split supplies are used, do not tie the pad to ground. Tie it to V–. 66011f 13 LTC6601-1 BLOCK DIAGRAM 20 IN4+ 19 C5 18 C6 17 C7 16 C8 400Ω 16.1pF 33.3pF 81.5pF 400Ω 1 IN2+ 200Ω 10.55pF OUT– 21.1pF IN1+ 100Ω 48.2pF V – + 2.3V 860Ω 180k 3 BIAS 60k BIAS 180k 125Ω 125Ω V– 860Ω 36k 36k V+ 14 15 2 + – 48.2pF 13 VOCM 12 4 IN1– 100Ω 21.1pF OUT+ 10.55pF 5 IN2– 200Ω 400Ω 81.5pF 11 400Ω 16.1pF 33.3pF IN4– 6 7 C1 8 C2 9 C3 C4 10 66011 BD 66011f 14 LTC6601-1 TEST CIRCUITS 20 LTC6601-1 19 18 17 16 1 2 15 VOUT– 25Ω IL + VINP 14 V+ 0.1μF 0.1μF V– 0.1μF VOCM 3nF VOUT+ 25Ω RBAL – BIAS VINM 3 + – 13 VOUT(CM) 5V 6 9 10 11 12 13 VIN 14 15 16 1 2 3 7 17 BIAS –5V 1μF VINM 4 5 3 LT6411 8 5 VINP 1μF + 4 5 6 7 8 9 10 – LTC6601-1 20 19 18 1 2 6 7 8 12 RBAL IL 11 66011 F01 Figure 1. DC Test Circuit 17 16 15 VOUT– 100Ω 1μF 14 V+ 0.1μF 0.1μF V– 0.1μF VOCM 3nF VOUT+ 100Ω COILCRAFT TTWB-4-B + – 13 50Ω 12 1μF 11 9 10 66011 F02 Figure 2. AC Test Circuit (Frequency Response Testing) 66011f 15 LTC6601-1 APPLICATIONS INFORMATION FUNCTIONAL DESCRIPTION The LTC6601 is designed to make the implementation of high frequency fully-differential filtering functions very easy. A very low noise amplifier is surrounded by 8 precision matched resistors and 12 precision matched capacitors so that a myriad of filter transfer functions limited only by possible combinations and imagination can be configured by hard wiring pins. The amplifier itself is a wide band, low noise and low distortion fully-differential amplifier with accurate output phase balancing. It is optimized for driving low voltage, single-supply, differential input, analog-to-digital converters (ADCs). The LTC6601’s outputs are capable of swinging rail-to-rail on supplies as low as 2.7V, which makes the amplifier ideal for converting ground referenced, single-ended signals into VOCM referenced differential signals. Unlike traditional op amps which have a single output, the LTC6601 has two outputs to process signals differentially. This allows for two times the signal swing in low voltage systems when compared to single-ended output amplifiers. The balanced differential nature of the amplifier and matched surrounding components provide even-order harmonic distortion cancellation, and less susceptibility to common mode noise (like power supply noise). The LTC6601 can be used as a single-ended input to differential output amplifier, or as a differential input to differential output amplifier. R2 C2 Figure 3 shows the basic filter architecture. The Laplace transfer function from VINDIFF to VOUTDIFF is given by the following generalized equation for a 2nd order lowpass filter: VOUTDIFF = VINDIFF Gain 1+ s s2 + 2πfO • Q ( 2πf O )2 Both Gain and Q of the filter are based on component ratios, which match and track extremely well over temperature. The corner frequency of the filter is a function of an RC product. This RC product is trimmed to ±1% (typical) and is not expected to drift by more than ±1% from nominal over the entire temperature range –40°C to 85°C. As a result, fully differential filters with tight magnitude, phase tolerance and repeatability are achieved. Although Figure 3 implies a differential input, the LTC6601 easily accepts single-ended inputs to either input, and will faithfully replicate the signal at the output in differential form. The LTC6601’s output common mode voltage, defined as the average of the two output voltages, is independent of the input common mode voltage, and is adjusted by applying a voltage on the VOCM pin. If the pin is left open, there is an internal resistive voltage divider, which develops a fO = Q= 1 2π R2 • R3 • C1• C2 C2 R3 • C1 R2 R2 R1 1 1+ 1+ GAIN • R3 C2 – R2 C1 R1 R3 C1 ( ) GAIN = +– VIN(DIFF) VOUT(DIFF) –+ R1 R3 C1 fO • f3dB = 6089 • (3568 • Q 4 1788 • Q 2 + 447 + 1.287 • 105 • 2 • Q 2 507.6 • Q ) ( 1 ) ( C2 0.2236 • fO • Q= 2.109 • 105 • (9.891• 10 • f (16 • f • (8.29 • 10 • f 12 O 2 9 3dB 4 5.486 • 109 • fO4 + 120 • 5.526 • 109 • f3dB2 + 3.082 • 106 • fO2 2 ) 3dB + 4.127 • 109 • fO2 ) 6.638 • 1010 • f3dB 4 ) ) R2 66011 F03 Figure 3. Basic Filter Topology and Equations 66011f 16 LTC6601-1 APPLICATIONS INFORMATION potential halfway between the V+ and V– pins. Whenever this pin is not hard tied to a low impedance ground plane, a high quality ceramic capacitor should be used to bypass the VOCM pin to a low impedance ground plane (see Layout Considerations). The LTC6601’s internal common mode feedback path forces accurate output phase balancing to reduce even order harmonics, and centers each individual output about the potential set by the VOCM pin. VOUT + + VOUT – VOUTCM = VOCM = 2 The outputs (OUT+ and OUT–) of the LTC6601 are capable of swinging rail-to-rail. They can source or sink up to approximately 75mA of current. Load capacitances should be decoupled with at least 25Ω of series resistance from each output. The LTC6601 Electrical Characteristics table specifies an input referred offset. This specification actually lumps voltage offsets due to offset bias currents (IOS), and amplifier voltage offset into one specification. To refer this specification to the output, you simply multiply the specification by the noise gain the LTC6601 is configured in: VOSODIFF = 1 + Gain where Gain is the closed loop gain in the particular filter application: Gain = R2 R1 (see the Electrical Characteristics table), and can be driven by an external source keeping in mind its equivalent input impedance and equivalent input voltage. If the BIAS pin is floated, care should be taken to control external leakage currents to this pin to under 1μA to prevent putting the LTC6601 an undesired state. If BIAS is tied to the positive supply, the LTC6601 differential filter will be in a fully active state configured for highest performance (lowest noise and lowest distortion). If the BIAS pin is floated or left unconnected, the LTC6601 filter will be in a fully active state, with amplifier currents reduced and performance scaled back to preserve power consumption. If the BIAS pin is tied to the most negative supply (V–), the LTC6601 will be placed into a low power shutdown mode with amplifier outputs disabled. In this state, the LTC6601 draws approximately 350μA. In low power shutdown, all internal biasing current sources are shut off, and the output pins, OUT+ and OUT–, will each appear as open collectors with a non-linear capacitor in parallel and steering diodes to either supply. The turn-on and turn-off time constant between states are on the order of 0.4μs. Using this function to wire-OR outputs together is not recommended. General Design and Usage As levels of integration have increased and correspondingly, system supply voltages decreased, there has been a need for ADCs to process signals differentially in order to maintain good signal-to-noise ratios. These ADCs are typically supplied from a single supply voltage which can be as low as 3V (2.7V min), and will have an optimal common mode input range near mid-supply. The LTC6601 makes interfacing to these ADCs easy, by providing antialias filtering, single-ended to differential conversion and common mode level shifting (translation). Figure 3 shows a general application of this. The low frequency gain to VOUTDIFF from VIN is simply: VOUTDIFF = VOUT + – VOUT – ≈ R2 •V R1 INDIFF COMPONENT INPUT PIN PROTECTION All of the LTC6601 pins with the exception of V+ and V– are protected with steering diodes to either power supply. In the event that a pin is driven beyond the supply rails, the excess current should be limited to under 10mA to prevent damage to the IC. BIAS Pin The LTC6601 has a BIAS pin (Pin 3) whose function is to tailor both performance and power of the LTC6601. The pin has a Thevenin equivalent impedance of approximately 150kΩ to a voltage source whose potential is 1.15V above the V– supply. This pin has fixed logic levels relative to V– The differential output voltage (VOUT+ – VOUT–) is completely independent of input and output common mode voltages, or the voltage at the common mode pin. This makes the 66011f 17 LTC6601-1 APPLICATIONS INFORMATION LTC6601 ideally suited for pre-amplification, level shifting and conversion of single-ended signals to differential output signals for driving differential input ADCs. INPUT IMPEDANCE Calculating the low frequency input impedance of the LTC6601 depends on how the inputs are driven (whether they are driven from a single-ended or a differential source). Figure 4 shows a simplified low frequency equivalent circuit of the LTC6601. For balanced input sources (VINP = –VINM), the low frequency input impedance is given by the equation: RINP = RINM = R1 The differential input impedance is simply: RINDIFF = 2 • R1 For single-ended inputs (VINM = 0), the input impedance actually increases over the balanced differential case due to the fact the summing node (at the junction of R1, R2 and R3) moves in phase with VINP to bootstrap the input impedance. Referring to Figure 4 with VINM = 0, the input impedance looking into either input is: RINP = RINM R1 ⎛ 1 ⎛ R2 ⎞ ⎞ ⎜ 1– 2 • ⎜ R1+ R2 ⎟ ⎟ ⎝ ⎠⎠ ⎝ Input and Output Common Mode Voltage Range The input common mode voltage is defined as the average of the two inputs: VINCM = VINP + VINM 2 The lower limit of the input common mode range is dictated by the ESD protection diodes at the input. While it is possible for the inputs to swing below V–, the diodes will conduct if the inputs are taken a diode drop below V–. The upper limit of the input common mode range varies as a function of the filter configuration (GAIN), VOCM potential, and whether or not the inputs are single-ended or differential. While it is possible to exceed the upper limit of the common mode range, doing so will degrade filter linearity. Referring to Figure 4, for linear operation, the summing junction where R1, R2 and R3 merge together should be prevented from swinging to within 1.4V of the V+ power supply. For the general case, the upper input common mode voltage limit should be constrained to: VOCM • R1 R2 + VINCM • ≤ V + – 1.4V R1+ R2 R1+ R2 Or equivalently: R1 ⎛ R1⎞ VINCM ≤ ⎜ 1+ ⎟ V + − 1.4V − •V ⎝ R2 ⎠ R2 OCM The specifications for input common mode range (VINCMR) are based on these constraints with R1 = R2 = 100Ω, and VOCM = mid-supply. Substituting the numbers for a single 3V power supply, (V+ = 3V, V– = 0V) with VOCM =1.5V, and R1 = R2 = 100Ω, into the above equation, the input common mode range (VINCMR) is between the two limits: 0V ≤ VINCM ≤ 1.7V which is as is specified for a 3V supply. ( ) R2 RINP + VINP R1 R3 – + VOUT– – – VINM R3 R1 RINM R2 VOUTDIFF – + + VOUT+ VOCM 0.1μF 66011 F04 Figure 4. Input Impedance 66011f 18 LTC6601-1 APPLICATIONS INFORMATION Likewise, substituting the numbers for a single 5V power supply, (V+ = 5V, V– = 0V) with VOCM = 2.5V, and R1 = R2 = 100Ω, into the above equation, the input common mode range (VINCMR) is between the two limits: 0V ≤ VINCM ≤ 4.7V The output common mode voltage is defined as the average of the two outputs: VOUTCM = VOCM = VOUT + + VOUT – 2 pin, but must be capable of driving the input impedance of the VOCM pin (RVOCM). This impedance can be assumed to be connected to a mid-supply potential. If an external reference drives the VOCM pin, it should still be bypassed with a high quality 0.01μF or higher capacitor to a low impedance ground plane to filter any thermal noise and to prevent common mode signals on this pin from being inadvertently converted to differential signals. Noise Considerations When comparing the LTC6601 noise to other amplifiers, be sure to compare similar specifications. Competing devices often specify noise referred to the inputs of the amplifier. The input referred voltage noise of the LTC6601-1 is 2.1nV/√Hz. This level is one of the lowest available for amplifiers in this speed and power range. In addition to the noise generated by the amplifier, the surrounding feedback resistors also contribute noise. A noise model is shown in Figure 5. The output spot noise generated by both the amplifier and the feedback components is governed by the equation: The VOCM pin sets this average by an internal common mode feedback loop which internally forces VOUT+ = –VOUT–. The output common mode range extends from 1.1 V above V– to 1V below V+. The VOCM pin sits in the middle of a voltage divider which sets the default midsupply open circuit potential. In single supply applications, where the LTC6601 is used to interface to an ADC, the optimal common mode input to the ADC is often determined by the ADC’s reference. If the ADC makes a reference available for setting the input common mode voltage, it can be directly tied to the VOCM 2 2 2 2 ⎛ ⎛ ⎛ ⎛ ⎛ R2 ⎞ ⎞ ⎞ ⎛ R2 ⎞ ⎞ ⎛ R2 ⎞ ⎞ ⎛ R2 ⎞ ⎞ 2 2 2⎛ eno = ⎜ eni • ⎜ 1+ ⎟ ⎟ + 2 • ⎜ In • ⎜ R2 + R3 • ⎜ 1+ ⎟ ⎟ ⎟ + 2 • ⎜ enR1 • ⎜ ⎟ ⎟ + 2 ⎜ enR3 • ⎜ 1+ ⎟ ⎟ + 2 • enR2 2 ⎝ R1⎠ ⎠ ⎟ ⎝ R1⎠ ⎠ ⎝ R1⎠ ⎠ ⎝ R1⎠ ⎠ ⎜ ⎝ ⎝ ⎝ ⎝ ⎝ ⎠ Substituting the equation for Johnson noise of a resistor (enR2 = 4kTR), and simplifying: 2 2 2 ⎛ ⎛ ⎛ ⎛ R2 ⎞ ⎛ R2 ⎞ ⎞ ⎞ ⎛ R2 ⎞ ⎞ ⎛ R2 ⎞ ⎞ 2 2 2⎛ eno = ⎜ eni • ⎜ 1+ ⎟ ⎟ + 2 • ⎜ In • ⎜ R2 + R3 • ⎜ 1+ ⎟ ⎟ ⎟ + 8 • k • T ⎜ R2 ⎜ 1+ ⎟ + R3 ⎜ 1+ ⎟ ⎟ ⎝ R1⎠ ⎠ ⎟ ⎝ R1⎠ ⎠ ⎝ R1⎠ ⎠ ⎜ ⎝ ⎝ ⎝ ⎝ R1⎠ ⎝ ⎠ 66011f 19 LTC6601-1 APPLICATIONS INFORMATION enR22 R2 * enR12 R1 enR32 In+2 R3 * eni2 * enR32 enR12 R1 R3 In–2 * + eno2 * enR22 – * R2 66011 F05 * Figure 5. Differential Noise Model of the LTC6601 Table 1 lists the amplifier input referred noise for the LTC6601-1. Tables 2 to10 list the noise referred to the input pins of the IC for common configurations of the LTC6601-1. To determine the spot noise at the output, simply multiply the noise by the Gain = R2/R1. To estimate the integrated noise at the output, multiply the noise by the gain, and the square root of the noise bandwidth. The noise bandwidth depends on the filter configuration. For Figure 2, the noise bandwidth is 100MHz, or approximately 7 times the filter bandwidth. Improvements in SNR can be made by adding an additional RC filter at the output to band limit wide band noise before feeding ADCs. See the section “Interfacing the LTC6601 to ADC Converters” for more detail. Table 1. Amplifier (Input Referred) Noise Characteristics for the LTC6601-1 BIAS PIN PULLED TO V+ eni nV/√Hz 2.1 in pA/√Hz 3 BIAS PIN FLOATING eni nV/√Hz 2.6 in pA/√Hz 2.1 ceramic capacitor be used to bypass pin V+ to ground and V– to ground, again with minimal routing. For driving large differential loads (