LTC6602CUF-PBF

FEATURES n n n n LTC6602 Dual Matched, High Frequency Bandpass/Lowpass Filters DESCRIPTION The LTC®6602 is a dual, matched, programmable bandpass or lowpass filter and differential driver. The selectivity of the LTC6602, combined with its phase matching and dynamic range, make it ideal for filtering in RFID systems. With two degree phase matching between channels, the LTC6602 can be used in applications requiring highly matched filters, such as transceiver I and Q channels. Gain programmability, and the fully differential inputs and outputs, simplify implementation in most systems. Both channels of the LTC6602 consist of a programmable lowpass and highpass filter. For bandpass functionality, the lowpass filters are programmed for the upper cutoff frequency. For lowpass functionality, the highpass filters can be bypassed. The filter cutoff frequencies can be set with a guaranteed accuracy of 3% with the use of a single resistor. Alternatively, the filter cutoff frequencies can be controlled with an external clock. The LTC6602 operates on a single 2.7V to 3.6V supply and features a low power shutdown mode. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.. n n n n n n n n n Matched Dual Filter/Driver, Ideal for RFID Readers Guaranteed Phase Matching to Within 2 Degrees Guaranteed Gain Matching to Within 0.2dB Configurable as Lowpass or Bandpass Programmable 5th Order Lowpass: 42kHz to 900kHz Programmable 4th Order Highpass: 4.2kHz to 90kHz Programmable Gain: 1×, 4×, 16×, 32× Simple Pin Programming or SPI Interface Low Noise: –145dBm/Hz (Input Referred) Low Distortion: –75dBc at 200kHz Differential, Rail-to-Rail Inputs and Outputs Input Range Extends from 0V to 5V Low Voltage Operation: 2.7V to 3.6V Shutdown Mode 4mm × 4mm QFN Package APPLICATIONS n n n n n Multiprotocol RFID Readers: EPC-GEN2, ISD and IPX IDEN, PHS, GSM Basestations Repeaters, Radio Links, and Modems Wireless Telemetry JTRS TYPICAL APPLICATION UHF RFID Reader Dual Baseband Filter and Dual ADC 3V 0.1μF 0.1μF 20 100Ω 100pF V+IN +INA I INPUT Q INPUT 38.3k 0.1μF –INA +INB –INB RBIAS VOCM MUTE MUTE INPUT FROM TRANSMITTER LTC6602 V+A V+D –OUTA +OUTA –OUTB +OUTB CLKIO SER CLKCNTL 100Ω 100pF 100pF 100pF BIN– Q OUTPUT 100Ω 2.2μF BIN+ 14-BIT ADC I OUTPUT VCM LTC2297 100Ω 100pF 100pF AIN– AIN+ 14-BIT ADC 10 0 GAIN (dB) –10 –20 –30 –40 –50 45kHz-300kHz BPF –60 1k 10k 100k 1M FREQUENCY (Hz) 10M 6602 TA01b Gain vs Frequency EXTERNAL CLOCK = 90MHz 15kHz-150kHz BPF 90kHz-900kHz BPF GAIN0(D0) HPF0(SDO) GAIN1 GND GND HPF1(SDI) LPF0(SCLK) LPF1(CS) CS SCLK SDI SPI CONTROL INPUT ÷4 CLK IN 6602 TA01 CLOCK INPUT 24MHz TO 128MHz (COVERS THE TAG BACKSCATTER LINK FREQUENCY RANGE OF 40kHz to 640kHz OF THE CLASS 1 GENERATION 2 UHF RFID COMMUNICATION PROTOCOL) 6602fa 1 LTC6602 ABSOLUTE MAXIMUM RATINGS (Note 1) PIN CONFIGURATION TOP VIEW GAIN0(D0) +OUTA 18 –OUTA 17 SER 25 16 V+D 15 CLKIO 14 GND 13 +OUTB 7 +INB 8 –INB 9 10 11 12 LPFO(SCLK) HPFO(SDO) HPF1(SDI) –OUTB GAIN1 MUTE +INA V+IN 1 V+A 2 VOCM 3 RBIAS 4 CLKCNTL 5 LPF1(CS) 6 –INA V+IN to GND ................................................................6V V+A, V+D to GND .........................................................4V Filter Inputs to GND ....................... –0.3V to V+IN + 0.3V All Other Pins to GND.............. –0.3V to V+A, V+D + 0.3V Maximum Input Current .......................................±10mA Output Short Circuit Duration........................... Indefinite Operating Temperature Range (Note 2) LTC6602CUF ........................................ –40°C to 85°C LTC6602IUF ......................................... –40°C to 85°C Specified Temperature Range (Note 3) LTC6602CUF ............................................ 0°C to 70°C LTC6602IUF ......................................... –40°C to 85°C Storage Temperature Range................... –65°C to 150°C 24 23 22 21 20 19 UF PACKAGE 24-LEAD (4mm × 4mm) PLASTIC QFN TJMAX = 150°C, θJA = 37°C/W EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO THE PCB. ORDER INFORMATION LEAD FREE FINISH LTC6602CUF#PBF LTC6602IUF#PBF TAPE AND REEL LTC6602CUF#TRPBF LTC6602IUF#TRPBF PART MARKING* 6602 6602 PACKAGE DESCRIPTION 24-Lead (4mm × 4mm) Plastic QFN 24-Lead (4mm × 4mm) Plastic QFN SPECIFIED TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ The l denotes the specifications which app ly over the full operating temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Filter Gain Either Channel External Clock = 90MHz, Highpass Filter Cutoff = 45kHz, Gain = 0dB Lowpass Filter Cutoff = 300kHz, VIN = 3.6VP-P fIN = 22.5kHz fIN = 45kHz fIN = 150kHz fIN = 300kHz fIN = 900kHz Matching of Filter Gain External Clock = 90MHz, Highpass Filter Cutoff = 45kHz, Lowpass Filter Cutoff = 300kHz, VIN = 3.6VP-P fIN = 45kHz fIN = 150kHz fIN = 300kHz ELECTRICAL CHARACTERISTICS l l l l l –1.8 0.1 –2.7 –32 –1.2 0.5 –2 –44 –30 –0.8 0.8 –1.2 –43 dB dB dB dB dB l l l ±0.2 ±0.2 ±0.2 dB dB dB 6602fa 2 LTC6602 ELECTRICAL CHARACTERISTICS PARAMETER Filter Phase Either Channel CONDITIONS External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 45kHz, Lowpass Filter Cutoff = 300kHz fIN = 50kHz fIN = 250kHz External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 45kHz, Lowpass Filter Cutoff = 300kHz fIN = 50kHz fIN = 250kHz The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted. MIN TYP MAX UNITS l l 125 –134 130 –130 134 –126 deg deg Matching of Filter Phase l l ±2 ±1.5 deg deg Filter Gain Either Channel External Clock = 90MHz, Highpass Filter Cutoff = 15kHz, Gain = 0dB Lowpass Filter Cutoff = 150kHz, VIN = 3.6VP-P fIN = 7.5kHz fIN = 15kHz fIN = 50kHz fIN = 150kHz fIN = 450kHz Matching of Filter Gain External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 15kHz, Lowpass Filter Cutoff = 150kHz fIN = 15kHz fIN = 50kHz fIN = 150kHz External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 15kHz, Lowpass Filter Cutoff = 150kHz fIN = 16.5kHz fIN = 125kHz External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 15kHz, Lowpass Filter Cutoff = 150kHz fIN = 16.5kHz fIN = 125kHz l l l l l –1.6 0.4 –2.3 –32 –1.2 0.7 –1.9 –44 –30 –0.8 0.9 –1.3 –43 dB dB dB dB dB l l l ±0.2 ±0.2 ±0.2 dB dB dB Filter Phase Either Channel l l 137 –142 142 –138 146 –134 deg deg Matching of Filter Phase l l ±2 ±1 deg deg Filter Gain Either Channel External Clock = 90MHz, Highpass Filter Cutoff = 90kHz, Gain = 0dB Lowpass Filter Cutoff = 900kHz, VIN = 3.6VP-P fIN = 45kHz fIN = 90kHz fIN = 300kHz fIN = 900kHz fIN = 2700kHz Matching of Filter Gain External Clock = 90MHz, Highpass Filter Cutoff = 90kHz, Lowpass Filter Cutoff = 900kHz, VIN = 3.6VP-P fIN = 90kHz fIN = 300kHz fIN = 900kHz l l l l l –1.8 –0.1 –2.1 –29 –1.2 0.6 –1.1 –45 –27 –0.7 1.2 –0.5 –44 dB dB dB dB dB l l l ±0.3 ±0.6 ±0.4 dB dB dB Filter Phase Either Chanel External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 90kHz, Lowpass Filter Cutoff = 900kHz fIN = 100kHz fIN = 750kHz Matching of Filter Phase External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 90kHz, Lowpass Filter Cutoff = 900kHz fIN = 100kHz fIN = 750kHz CLKCNTL = 3V (Note 4) RBIAS = 200k, Output Clock = 24.705MHz RBIAS = 54.9k, Output Clock = 90MHz l l 136 –136 141 –131 145 –127 deg deg l l l l ±2 ±1.5 ±3 ±3 deg deg % % Filter Cutoff Accuracy when Self Clocked 6602fa 3 LTC6602 ELECTRICAL CHARACTERISTICS PARAMETER PGA Gain CONDITIONS Lowpass Cutoff = 150kHz, Highpass Filter Bypassed, Measured at DC, 0.6V to 2.4V Each Output Gain Setting = 0dB Gain Setting = 12dB Gain Setting = 24dB Gain Setting = 30dB Lowpass Cutoff = 150kHz, Highpass Filter Bypassed, Measured at DC, 0.6V to 2.4V Each Output Gain Setting = 0dB Gain Setting = 12dB Gain Setting = 24dB Gain Setting = 30dB Voltage Noise Referred to the Input Gain = 0dB Gain = 12dB Gain = 24dB Gain = 30dB Noise Bandwidth = 1.57MHz (Note 5), Referred to the Input Gain = 0dB Gain = 12dB Gain = 24dB Gain = 30dB VIN = 1.5VP-P, fIN = 100kHz Differential Common Mode Differential Offset Voltage at Either Output Differential Offset Voltage at Either Output HPF Bypassed, Lowest LPF Cutoff Differential Offset Voltage at Either Output HPF Bypassed, Highest LPF Cutoff Common Mode Offset Voltage VOCM = 1.5V, Supplies = 3V VOSCM = VOUT-CM – VOCM Common Mode Input from 0 to 3V V+IN = 3V Common Mode Input from 0 to 5V V+IN = 5V V+A = V+D = 3V, Pin 3 Open V+A = V+D = 3V, Pin 3 Open Lowpass Cutoff = 150kHz, Highpass Filter Bypassed, Measured at DC Source 1mA, VOUT High, Relative to V+A Sink 1mA, VOUT Low, Relative to GND Lowpass Cutoff = 150kHz, Highpass Filter Bypassed Sourcing Sinking Internal Clock (RBIAS = 54.9k); Sum of the Currents into V+D, V+A, and V+IN All Supplies Set to 3V HPF = 15k, LPF = 150k HPF = 45k, LPF = 300k HPF = 90k, LPF = 900k l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted. MIN TYP MAX UNITS l l l l 0.4 11.6 23.5 29.1 0.8 12 23.8 29.6 1.2 12.4 24.1 30.1 dB dB dB dB PGA Gain Matching l l l l ±0.2 ±0.2 ±0.3 ±0.3 –119 –131 –142 –146 –62 –74 –85 –89 –75 16 20 ±7 ±10 ±10 –40 ±20 ±15 ±30 ±30 70 dB dB dB dB dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm dBm dBm dBm dB kΩ kΩ mV mV mV mV Noise At 200kHz Integrated Noise THD Input Impedance VOS Differential VOSCM CMR Differential ΔVINCM /ΔVOUTDIFF l l l l 75 75 1.2 300 95 95 1.4 400 1.6 700 dB dB V Ω VOCM Pin Voltage VOCM Pin Input Impedance Output Swing l l l l 200 200 4 10 15 25 500 500 25 50 mV mV mA mA Short-Circuit Current Supply Current l l l 65 100 105 80 125 130 mA mA mA 6602fa 4 LTC6602 ELECTRICAL CHARACTERISTICS PARAMETER Supply Current, Shutdown Mode Supply Voltage PSR RBIAS Resistor Range RBIAS Pin Voltage Clock Frequency Drift Over Temperature Clock Frequency Change Over Supply Output Clock Duty Cycle CLKIO Pin High Level Input Voltage CLKIO Pin Low Level Input Voltage CLKIO Pin Input Current CONDITIONS Sum of the Currents into V+D, V+A, and V+IN; All Supplies Set to 3V Shutdown Via Serial Interface, Control Bit D1 = 1. V+D, V+A Relative to GND V+IN Relative to GND V+D = V+A = V+IN, All from 2.7V to 3.6V V+D = V+A = 3.0V, V+IN from 4.5V to 5.5V Clock Frequency Error ≤ ±3%, CLKCNTL = 3V 54.9k < RBIAS < 200k RBIAS = 54.9k, CLKCNTL Pin Open V+A, V+D from 2.7V to 3.6V, RBIAS = 54.9k, CLKCNTL Pin Open RBIAS = 54.9k CLKCNTL = 0V (Note 6) CLKCNTL = 0V (Note 6) CLKCNTL = 0V CLKIO = 0V (Note 7) CLKIO = V+D V+A = V+D = 3V, CLKCNTL = 3V IOH = –1mA IOH = –4mA V+A = V+D = 3V, CLKCNTL = 3V IOL = 1mA IOL = 4mA V+A = V+D = CLKCNTL = 3V, 20%/80%, CLOAD = 5pF V+A = V+D = CLKCNTL = 3V, 20%/80%, CLOAD = 5pF Pins 17, 20 Pins 17, 20 Pin 17 or Pin 20 = 0V (Note 7) Pin 17 or Pin 20 = V+D Pin 5 Pin 5 CLKCNTL = 0V (Note 7) CLKCNTL = V+D l l l l l l l l l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted. MIN TYP 170 2.7 2.7 50 80 54.9 1.17 40 –0.6 25 V+D – 0.3 0.3 0.1 50 0.6 75 60 95 200 MAX 235 3.6 5.5 UNITS μA V V dB dB kΩ V ppm/ºC %/V % V V l l –1 10 2.95 2.9 0.05 0.1 0.3 0.3 V+D – 0.3 0.3 –10 2 V+D – 0.5 0.5 –25 –15 15 μA μA V V V V ns ns V V μA μA V V μA μA CLKIO Pin High Level Output Voltage CLKIO Pin Low Level Output Voltage CLKIO Rise Time CLKIO Fall Time SER, MUTE High Level Input Voltage SER, MUTE Low Level Input Voltage SER, MUTE Input Current CLKCNTL High Level Input Voltage CLKCNTL Low Level Input Voltage CLKCNTL Input Current 25 6602fa 5 LTC6602 ELECTRICAL CHARACTERISTICS Pin Programmable Control Mode Specifications SYMBOL V+D = 2.7V to 3.6V VIH VIL IIN Digital Input High Voltage Digital Input Low Voltage Digital Input Current Pins 6, 9-11, 21, 22 Pins 6, 9-11, 21, 22 Pins 6, 9-11, 21, 22 (Note 7) l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Specifications apply to pins 6, 9-11, 21 and 22. PARAMETER CONDITIONS MIN 2 0.8 –1 1 TYP MAX UNITS V V μA Serial Port DC and Timing Specifications SYMBOL V+D = 2.7V to 3.6V VIH VIL IIN VOH VOL t1 t2 t3 t4 t5 t6 t7 t8 t9 Digital Input High Voltage Digital Input Low Voltage Digital Input Current Digital Output High Voltage Digital Output Low Voltage SDI Valid to SCLK Setup SDI Valid to SCLK Hold SCLK Low SCLK High CS Pulse Width LSB SCLK to CS CS Low to SCLK SDO Output Delay SCLK Low to CS Low (Note 6) (Note 6) CL = 15pF (Note 6) Pins 6, 9, 10 Pins 6, 9, 10 Pins 6, 9, 10 (Note 7) Pins 11, 21 Sourcing 500μA Pins 11, 21 Sinking 500μA (Note 6) (Note 6) l l l l l l l l l l l l l l PARAMETER CONDITIONS MIN 2 TYP MAX UNITS V 0.8 –1 VSUPPLY -0.3 0.3 60 0 100 100 60 60 30 125 0 1 V μA V V ns ns ns ns ns ns ns ns ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: LTC6602C and LTC6602I are guaranteed functional over the operating temperature range of –40°C to 85°C. Note 3: LTC6602C is guaranteed to meet specified performance from 0°C to 70°C. The LTC6602C is designed, characterized and expected to meet specified performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. The LTC6602I is guaranteed to meet the specified performance limits from –40°C to 85°C. Note 4: This test measures the internal oscillator accuracy (deviation from the fCLK equation). Variations in the internal oscillator frequency cause variations in the filter cutoff frequency. See the “Applications Information” section. Note 5: 1.57MHz is the equivalent noise bandwidth of a 1MHz 1st order RC lowpass filter. Note 6: Guaranteed by design, not subject to test. Note 7: To conform to the Logic IC standard, current out of a pin is arbitrarily given a negative value. 6602fa 6 LTC6602 TYPICAL PERFORMANCE CHARACTERISTICS Gain vs Frequency 20 10 TA = 25°C VS = 3V EXTERNAL CLOCK RBIAS = 54.9k 0 GAIN = 0dB –70 15kHz-150kHz BPF 90kHz-900kHz BPF DISTORTION (dBc) Distortion vs Input Frequency TA = 25°C, VS = 3V, DIFFERENTIAL INPUT, , VIN = 1.5VP-P, 12.4-82.4kHz BPF RBIAS = 200k 45kHz-300kHz BPF RBIAS = 54.9k, GAIN = 0dB , DISTORTION (dBc) HD3 12kHz-82kHz BPF HD2 45kHz-300kHz BPF –30 Distortion vs Output Voltage TA = 25°C V = 3V –40 f S = 100kHz IN DIFFERENTIAL INPUT –50 RBIAS = 54.9k RBIAS = 45kHz-300kHz BPF –60 GAIN = 0dB –70 –80 –90 –100 HD2 HD3 –75 GAIN (dB) –10 –20 –30 –40 –50 45kHz-300kHz BPF –60 1k 10k 100k 1M FREQUENCY (Hz) 10M 6602 G01 –80 –85 HD2 12kHz-82kHz BPF –90 HD3 45kHz-300kHz BPF 300 66062 G02 0 50 100 150 200 250 INPUT FREQUENCY (kHz) 0 1 2 3 4 OUTPUT VOLTAGE (VP-P) 5 6 66062 G03 Distortion vs Gain –70 TA = 25°C VS = 3V fIN = 100kHz DIFFERENTIAL INPUT, VOUT = 1.5VP-P –75 R BIAS = 54.9k 45kHz-300kHz BPF –80 HD3 HD2 –85 –70 Distortion vs Highpass Cutoff Frequency TA = 25°C VS = 3V fIN = 100kHz DIFFERENTIAL INPUT, VIN = 1.5VP-P RBIAS = 54.9k fLP = 300kHz GAIN = 0dB HD3 HD2 –85 –70 Distortion vs Lowpass Cutoff Frequency –75 DISTORTION (dBc) –75 DISTORTION (dBc) HD3 –80 TA = 25°C VS = 3V fIN = 100kHz DIFFERENTIAL INPUT, VIN = 1.5VP-P RBIAS = 54.9k fHP = 45kHz GAIN = 0dB 0 150 300 450 600 750 LOWPASS CUTOFF FREQUENCY (kHz) 900 6602 G06 DISTORTION (dBc) –80 HD2 –85 –90 0 6 12 18 GAIN (dB) 24 30 6602 G04 –90 0 15 30 45 60 75 HIGHPASS CUTOFF FREQUENCY (kHz) 90 6602 G05 –90 Filter Cutoff Accuracy vs Supply Voltage FILTER CUTOFF FREQUENCY DEVIATION (%) FILTER CUTOFF FREQUENCY DEVIATION (%) 0.10 RBIAS = 54.9k 45kHz-300kHz BPF GAIN = 0dB 0.4 Filter Cutoff Accuracy vs Temperature COMMON MODE REJECTION (dB) VS = 3V 0.3 RBIAS = 54.9k 45kHz-300kHz BPF GAIN = 0dB 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 6602 G08 Common Mode Rejection 120 110 100 90 80 70 60 GAIN = 0dB GAIN = 12dB CMR = ΔVIN-CM /ΔVOUT-DIFF 0.05 –40°C 5 TYPICAL UNITS 0.00 25°C 85°C –0.05 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) 6602 G07 TA = 25°C 50 V = 3V S GAIN = 24dB 40 VIN-CM = 0V GAIN = 30dB ΔVIN-CM = 1.25VP-P 30 RBIAS = 54.9k 45kHz-300kHz BPF 20 1k 10k 100k 1M 10M FREQUENCY (Hz) 6602 G09 6602fa 7 LTC6602 TYPICAL PERFORMANCE CHARACTERISTICS Common Mode Rejection 120 110 COMMON MODE REJECTION (dB) 100 90 80 GAIN = 12dB GAIN = 0dB CMR = ΔVIN-CM /ΔVOUT-DIFF COMMON MODE REJECTION (dB) 120 Common Mode Rejection TA = 25°C, VS = 3V, 110 VIN-CM = 0V, ΔVIN-CM = 1.25VP-P , RBIAS = 54.9k, 90kHz-900kHz BPF 100 90 80 70 60 50 40 30 1M 6602 G10 Common Mode Rejection Ratio 120 110 100 90 CMRR (dB) 80 70 60 50 40 GAIN = 0dB GAIN = 12dB GAIN = 30dB GAIN = 24dB 70 GAIN = 24dB GAIN = 30dB 60 TA = 25°C 50 V = 3V S 40 VIN-CM = 0V ΔVIN-CM = 1.25VP-P 30 RBIAS = 54.9k 15kHz-150kHz BPF 20 1k 10k 100k FREQUENCY (Hz) GAIN = 0dB GAIN = 24dB GAIN = 12dB CMR = ΔVIN-CM /ΔVOUT-DIFF 20 10k 100k 1M FREQUENCY (Hz) GAIN = 30dB 10M 6602 G11 TA = 25°C, VS = 3V, 30 VIN-CM = 0V, ΔVIN-CM = 1.25VP-P , RBIAS = 54.9k, 45kHz-300kHz BPF 20 1k 10k 100k 1M FREQUENCY (Hz) 10M 6602 G12 Common Mode Rejection Ratio 120 110 100 90 CMRR (dB) 80 70 60 50 40 TA = 25°C, VS = 3V, 30 VIN-CM = 0V, ΔVIN-CM = 1.25VP-P , RBIAS = 54.9k, 15kHz-150kHz BPF 20 1k 10k 100k FREQUENCY (Hz) GAIN = 0dB GAIN = 12dB CMRR (dB) GAIN = 30dB GAIN = 24dB 120 Common Mode Rejection Ratio TA = 25°C 110 VS = 3V VIN-CM = 0V 100 ΔV IN-CM = 1.25VP-P 90 RBIAS = 54.9k 90kHz-900kHz BPF 80 GAIN = 12dB 70 60 50 40 30 1M 6602 G13 OIP3 vs Average Signal Frequency, fC 48 TA = 25°C VS = 3V f1 = fC –5kHz, f2 = fC +5kHz 46 V OUT = 6dBm PER TONE FOR 2-TONE TEST RBIAS = 54.9k 45kHz-300kHz BPF 44 GAIN = 24dB 42 GAIN = 0dB 40 GAIN = 30dB GAIN = 12dB GAIN = 24dB GAIN = 0dB GAIN = 30dB 20 10k OIP3 (dBm) 10M 6602 G14 100k 1M FREQUENCY (Hz) 38 0 50 100 150 200 250 300 350 CENTER SIGNAL FREQUENCY, fC (kHz) 6602 G15 OIP3 vs Average Signal Frequency, fC 48 GAIN = 12dB GAIN = 24dB OIP3 (dBm) 44 GAIN = 0dB TA = 25°C VS = 3V f1 = fC –5kHz f2 = fC +5kHz VOUT = 6dBm PER TONE FOR 2-TONE TEST RBIAS = 54.9k 15kHz-150kHz BPF 0 20 40 60 80 100 120 140 160 CENTER SIGNAL FREQUENCY, fC (kHz) 6602 G16 OIP3 vs Average Signal Frequency, fC GAIN = 30dB 48 TA = 25°C, VS = 3V f1 = fC –10kHz, f2 = fC +10kHz VOUT = 6dBm PER TONE 46 FOR 2-TONE TEST RBIAS = 54.9k 90kHz-900kHz BPF 44 50 OIP3 vs Temperature VS = 3V VOUT = 6dBm PER TONE FOR 2-TONE TEST 48 RBIAS = 54.9k GAIN = 30dB fIN = 95kHz, 105kHz 15kHz-150kHz BPF 46 fIN = 145kHz, 155kHz 45kHz-300kHz BPF 46 GAIN = 12dB OIP3 (dBm) OIP3 (dBm) 42 42 GAIN = 24dB 40 GAIN = 30dB GAIN = 0dB 38 0 100 200 300 400 500 600 700 800 900 1000 CENTER SIGNAL FREQUENCY, fC (kHz) 6602 G17 44 40 42 fIN = 590kHz, 610kHz 90kHz-900kHz BPF 38 40 –40–30–20–10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) 6602 G18 6602fa 8 LTC6602 TYPICAL PERFORMANCE CHARACTERISTICS Output Impedance vs Frequency 100 TA = 25°C VS = 3V RBIAS = 54.9k SUPPLY CURRENT (mA) 110 Supply Current vs Supply Voltage CLKCNTL PIN FLOATING RBIAS = 54.9k 45kHz-300kHz BPF GAIN = 0dB 85°C 100 25°C –40°C 95 120 Supply Current vs Temperature 90kHz-900kHz BPF 100 SUPPLY CURRENT (mA) 80 15kHz-150kHz BPF 60 40 VS = 3V 20 CLKCNTL PIN FLOATING RBIAS = 54.9k GAIN = 0dB 0 –40–30–20–10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) 6602 G21 OUTPUT IMPEDANCE (Ω) 105 45kHz-300kHz BPF 10 15kHz-150kHz BPF 90kHz-900kHz BPF 1 900kHz LPF 45kHz-300kHz BPF 0.1 1k 10k 100k 1M FREQUENCY (Hz) 10M 6602 G19 90 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) 6602 G20 Clock Output Operating at 90MHz 1.25 RBIAS Pin Voltage vs IRBIAS TA = 25°C VS = 3V RBIAS PIN VOLTAGE (V) 1.20 1V/DIV 0V 1.15 1.10 2.5ns/DIV 6602 G22 0 5 10 15 IRBIAS (μA) 20 25 6602 G23 Input Referred Noise Density 1000 VOLTAGE NOISE DENSITY (nV/√Hz) VOLTAGE NOISE DENSITY (nV/√Hz) GAIN = 0dB INTEGRATED NOISE = 186.5μVRMS GAIN = 12dB INTEGRATED NOISE = 47.1μVRMS 1000 Input Referred Noise Density GAIN = 0dB INTEGRATED NOISE = 189μVRMS 1000 VOLTAGE NOISE DENSITY (nV/√Hz) Input Referred Noise Density GAIN = 0dB INTEGRATED NOISE = 304.2μVRMS GAIN = 12dB INTEGRATED NOISE = 77.6μVRMS 100 100 100 10 GAIN = 30dB INTEGRATED NOISE = 7.5μVRMS 1k GAIN = 24dB INTEGRATED NOISE = 12.6μVRMS 1M 6602 G24 10 GAIN = 24dB INTEGRATED NOISE = 12.5μVRMS 1 1k 10k 100k FREQUENCY (Hz) GAIN = 12dB INTEGRATED NOISE= 47.8μVRMS 10 1 GAIN = 30dB INTEGRATED NOISE = 7.2μVRMS 1M 6602 G25 10k 100k FREQUENCY (Hz) 1 10k GAIN = 24dB INTEGRATED NOISE = 20.7μVRMS GAIN = 30dB INTEGRATED NOISE = 17.5μVRMS 100k 1M FREQUENCY (Hz) 10M 6602 G26 TA = 25°C, VS = 3V, EXTERNAL CLOCK RBIAS = 54.9k, 45kHz-300kHz BPF INTEGRATED NOISE BW = 1.57MHz TA = 25°C, VS = 3V, EXTERNAL CLOCK RBIAS = 54.9k, 15kHz-150kHz BPF INTERNAL NOISE BW = 400kHz TA = 25°C, VS = 3V, EXTERNAL CLOCK RBIAS = 54.9k, 90kHz-900kHz BPF INTERNAL NOISE BW = 2.5MHz 6602fa 9 LTC6602 PIN FUNCTIONS V+IN (Pin 1): Input Voltage Supply (2.7V ≤ V ≤ 5.5V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1μF capacitor unless it is tied to V+A (Pin 2). The bypass should be as close as possible to the IC, but is not as critical as the bypassing of V+A and V+D (Pin16). V+A (Pin 2): Analog Voltage Supply (2.7V ≤ V ≤ 3.6V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1μF capacitor. The bypass should be as close as possible to the IC. VOCM (Pin 3): Output common mode voltage reference. If floated, an internal resistive divider sets the voltage on this pin to half the supply voltage (typically 1.5V), maximizing the dynamic range of the filter. If this pin is floated, it must be bypassed with a quality 0.1μF capacitor to ground. This pin has a typical input impedance of 400Ω and may be overdriven. Driving this pin to a voltage other than the default value will reduce the signal range the filter can handle before clipping. RBIAS (Pin 4): Oscillator Frequency-Setting Resistor Input. The value of the resistor connected between this pin and ground determines the frequency of the master oscillator, and sets the bias currents for the filter networks. The voltage on this pin is held by the LTC6602 to approximately 1.17V. For best performance, use a precision metal film resistor with a value between 54.9k and 200k and limit the capacitance on this pin to less than 10pF This resistor is . necessary even if an external clock is used. CLKCNTL (Pin 5): Clock Control Input. This three-state input selects the function of CLKIO (Pin 15). Tying the CLKCNTL pin to ground allows the CLKIO pin to be driven by an external clock (CLKIO is the master clock input). If the CLKCNTL pin is floated, the internal oscillator is enabled, but the master clock is not present at the CLKIO pin (CLKIO is a no-connect). If the CLKCNTL pin is tied to V+D (Pin 16), the internal oscillator is enabled and the master clock is present at the CLKIO pin (CLKIO is the master clock output). To detect a floating CLKCNTL pin, the LTC6602 attempts to pull the pin toward mid-supply. This is realized with two internal current sources, one tied to V+D and CLKCNTL and the other one tied to ground and CLKCNTL. Therefore, driving the CLKCNTL pin high requires sourcing approximately 15μA. Likewise, driving the CLKCNTL pin low requires sinking 15μA. When the CLKCNTL pin is floated, preferably it should be bypassed by a 1nF capacitor to ground or it should be surrounded by a ground shield to prevent excessive coupling from other PCB traces. LPF1(CS) (Pin 6): Logic Input. When in pin programmable control mode, this pin is the MSB of the lowpass cutoff frequency control code; in serial control mode, this pin is the chip select input (active low). +INB, –INB (Pins 7, 8): Channel B differential inputs. The input range and input resistance are described in the Applications Information section. Input voltages which exceed V+IN (Pin 1) should be avoided. LPF0(SCLK) (Pin 9): Logic Input. When in pin programmable control mode, this pin is the LSB of the lowpass cutoff frequency control code; in serial control mode, this pin is the clock of the serial interface. HPF1(SDI) (Pin 10): Logic Input. When in pin programmable control mode, this pin is the MSB of the highpass cutoff frequency control code; in serial control mode, this pin is the serial data input. HPF0(SDO) (Pin 11): Logic Input. When in pin programmable control mode, this pin is the LSB of the highpass cutoff frequency control code; in serial control mode, this pin is the serial data output. –OUTB, +OUTB (Pins 12, 13): Channel B differential filter outputs. These pins can drive 1k and/or 50pF loads. For larger capacitive loads, an external 100Ω series resistor is recommended for each output. The common mode voltage of the filter outputs is the same as the voltage at VOCM (Pin 3). GND (Pin 14): Ground. Connect to a ground plane for best performance. 6602fa 10 LTC6602 PIN FUNCTIONS CLKIO (Pin 15): When CLKCNTL (Pin 5) is tied to ground, CLKIO is the master clock input. When CLKCNTL is floated, CLKIO is pulled to ground by a weak, 5μA pulldown. When CLKCNTL is tied to V+D (Pin 16), CLKIO is the master clock output. When configured as a clock output, this pin can drive 1k and/or 5pF loads. Heavier loads may cause inaccuracies due to supply bounce at high frequencies. V+D (Pin 16): Digital Voltage Supply (2.7V ≤ V ≤ 3.6V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1μF capacitor. The bypass should be as close as possible to the IC. SER (Pin 17): Interface Selection Input. When tied to V+D (Pin 16), the interface is in pin programmable control mode, i.e. the filter gain and cutoff frequencies are programmed by the GAIN1, GAIN0, HPF1, HPF0, LPF1 and LPF0 pin connections. When SER is tied to ground, the filter gain, the filter cutoff frequencies and shutdown mode are programmed by the serial interface. –OUTA, +OUTA (Pins 18, 19): Channel A differential filter outputs. These pins can drive 1k and/or 50pF loads. For larger capacitive loads, an external 100Ω series resistor is recommended for each output. The common mode voltage of the filter outputs is the same as the voltage at VOCM (Pin 3). MUTE (Pin 20): MUTEX input. Drive to ground to disconnect and mute the inputs. Float or drive to V+D (Pin 16) for normal operation. GAIN0(D0) (Pin 21): Logic Input. When in pin programmable control mode, this pin is the LSB of the gain control code; in serial control mode, this pin is the LSB of the serial control register, an output. GAIN1 (Pin 22): Logic Input. When in pin programmable control mode, this pin is the MSB of the gain control code; in serial control mode, this pin is a no-connect. –INA, +INA (Pins 23, 24): Channel A differential inputs. The input range and input resistance are described in the Applications Information section. Input voltage levels can range from GND to the V+IN supply rail. Exposed Pad (Pin 25): Ground. The Exposed Pad must be soldered to PCB. 6602fa 11 LTC6602 BLOCK DIAGRAM +INA 24 –INA 23 GAIN1 22 GAIN0(D0) 21 MUTE 20 +OUTA 19 V+IN 1 CHANNEL A 18 –OUTA PGA V+A 2 CONTROL VDDA 1.6k VOCM 3 1.6k GND RBIAS 4 BIAS CLKCNTL 5 BIAS/OSC LPF HPF 17 SER BIAS CLK 16 V+D CONTROL LOGIC CLOCK GENERATOR 15 CLKIO CONTROL CLK 14 GND PGA LPF HPF LPF1(CS) 6 CHANNEL B 13 +OUTB 7 +INB 8 –INB 9 LPF0(SCLK) 10 HPF1(SDI) 11 HPF0(SDO) 12 –OUTB 6602 BD 6602fa 12 LTC6602 TIMING DIAGRAM Timing Diagram of the Serial Interface t1 t2 SCLK t9 t4 t3 t6 t7 SDI D3 D2 D1 D0 D7 • • • • D4 D3 t5 CS t8 D4 PREVIOUS BYTE D3 D2 D1 D0 D7 • • • • D4 CURRENT BYTE D3 6602 TD SDO 6602fa 13 LTC6602 APPLICATIONS INFORMATION Theory of Operation (Refer to Block Diagram) The LTC6602 features two matched filter channels, each containing gain control, lowpass, and highpass networks that are controlled by a single control block and clocked by a single clock generator. The gain, lowpass and highpass sections can be independently programmed. The two channels are not independent, i.e. if the gain is set to 24dB, then both channels have a gain of 24dB. The filter can also be programmed to bypass the highpass filter networks, giving a lowpass response. The filter can be clocked with an external clock source, or using the internal oscillator. A resistor connected to the RBIAS pin sets the bias currents for the filter networks and the internal oscillator frequency (unless driven by an external clock). Altering the clock frequency changes the filter bandwidths. This allows the filters to be “tuned” to many different bandwidths. Pin Programmable Interface As shown in Figure 1, connecting SER to V+D allows the filter to be directly controlled through the pin programmable control lines GAIN1, GAIN0, HPF1, HPF0, LPF1 and LPF0. The HPF0(SDO) and GAIN0(D0) pins are bidirectional (inputs in pin programmable control mode, outputs in serial mode). In pin programmable control mode, the voltages at HPF0(SDO) and GAIN0(D0) cannot exceed V+D; otherwise, large currents can be injected to V+D through the internal diodes (see Figure 2). Connecting a 10k resistor at the HPF0(SDO) and GAIN0(D0) pins (see Figure 1) is recommended for current limiting, to less than 10mA. SER has an internal pull-up to V+D. None of the logic inputs have an internal pull-up or pull-down. 3.3V LTC6602 V+IN V+A V+D 3.3V LTC6602 V+IN V+A V+D +OUTA –OUTA 0.1μF 0.1μF + – VIN +INA –INA SER LPF1(CS) LPF0(SCLK) HPF1(SDI) HPF0(SDO) GAIN1 GAIN0(D0) GND + VOUT + – LPF1 LPF0 HPF1 μP HPF0 GAIN1 GAIN0 10k 10k VIN +INA –INA SER LPF1(CS) LPF0(SCLK) HPF1(SDI) HPF0(SDO) GAIN1 GAIN0(D0) GND +OUTA –OUTA + VOUT – – LOWPASS CUTOFF = 900kHz (fCLK = 90MHz) HIGHPASS CUTOFF = 90kHz (fCLK = 90MHz) GAIN = 16 GAIN, BANDWIDTHS ARE SET BY MICROPROCESSOR. 10k RESISTORS ON HPF0(SDO) AND GAIN0(D0) PROTECT THE DEVICE IF VHPF0 > V+D OR VGAIN0 > V+D 6602 F01 Figure 1. Filter in Pin Programmable Control Mode 6602fa 14 LTC6602 APPLICATIONS INFORMATION V+D SHUTDOWN OUT 6-BIT GAIN, BW CONTROL CODE CS HPF0(SDO) 8-BIT LATCH DIN Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 8-BIT SHIFT-REGISTER (INTERNAL NODE) 6602 F02 SCLK SDO 6602 F03 Figure 2. Bidirectional Design of HPFO(SDO) and GAIN0(D0) Pins 3.3V LTC6602 #1 Figure 3. Diagram of Serial Interface (MSB First Out) 3.3V LTC6602 #2 0.1μF V+IN V+A V+D 0.1μF V+IN V+A V+D + VIN1 +INA –INA SER +OUTA –OUTA + – VOUT1 + VIN2 +INA –INA SER LPF1(CS) +OUTA –OUTA + – VOUT2 – – LPF1(CS) μP SCLK LPF1(CS) LPF0(SCLK) GAIN0(D0) HPF0(SDO) OUT1 LPF0(SCLK) HPF1(SDI) GND GAIN0(D0) HPF0(SDO) OUT2 SDO SDI HPF1(SDI) GND SCLK SDI D15 D11 D10 D9 D8 D7 D3 D2 D1 D0 GAIN, BW CONTROL WORD FOR #2 SHUTDOWN FOR #2 CS GAIN, BW CONTROL WORD FOR #1 SHUTDOWN FOR #1 6602 F04 Figure 4. Two Filters in a Daisy Chain Serial Control Register Definition D7 GAIN0 D6 GAIN1 D5 LPF0 D4 LPF1 D3 HPF0 D2 HPF1 D1 SHDN D0 OUT 6602fa 15 LTC6602 APPLICATIONS INFORMATION Serial Interface Connecting SER to ground allows the filter to be controlled through the SPI serial interface. When CS is low, the serial data on SDI is shifted into an 8-bit shift-register on the rising edge of the clock (SCLK), with the MSB transferred first (see Figure 3). Serial data on SDO is shifted out on the clock’s falling edge. A high CS will load the 8 bits of the shift-register into an 8-bit D-latch, which is the serial control register. The clock is disabled internally when CS is pulled high. Note: SCLK must be low before CS is pulled low to avoid an extra internal clock pulse. SDO is always active in serial mode (never tri-stated) and cannot be “wire-or’ed” to other SPI outputs. In addition, SDO is not forced to zero when CS is pulled high. An LTC6602 may be daisy chained with other LTC6602s or other devices having serial interfaces. Daisy chaining is accomplished by connecting the SDO of the lead chip to the SDI of the next chip, while SCLK and CS remain common to all chips in the daisy chain. The serial data is clocked to all the chips then the CS signal is pulled high to update all of them simultaneously. Figure 4 shows an example of two LTC6602s in a daisy chained SPI configuration. GAIN1 and GAIN0 are the gain control bits (register bits D6 and D7 when in serial mode). Their function is shown in Table 1. In serial mode, register bit D1 can be set to ‘1’ to put the device into a low power shutdown mode. Register bit D0 is a general purpose output (Pin 21) when in serial mode. Table 1. Gain Control GAIN 1 0 0 1 1 GAIN 0 0 1 0 1 PASSBAND GAIN (dB) 0 12 24 30 Self-Clocking Operation The LTC6602 features a unique internal oscillator which sets the filter cutoff frequency using a single external resistor connected to the RBIAS pin. The clock frequency is determined by the following simple formula (see Figure 5): fCLK = 494.1MHz • 10k/RBIAS Note: RBIAS ≤ 200k. 200 175 150 RBIAS (kΩ) 125 100 75 50 20 30 40 50 60 70 80 DESIRED CLOCK FREQUENCY (MHz) 90 6602 F05 Figure 5. RBIAS vs Desired Clock Frequency The design is optimized for V+A, V+D = 3V, fCLK = 90MHz, where the filter cutoff frequency error is typically