LTC6605IDJC-7-PBF

FEATURES n LTC6605-7 Dual Matched 7MHz Filter with Low Noise, Low Distortion Differential Amplifier DESCRIPTION The LTC®6605-7 contains two independent, fully differential amplifiers configured as matched 2nd order lowpass filters. The f–3dB of the filters is adjustable in the range of 6.5MHz to 10MHz. The internal op amps are fully differential, feature very low noise and distortion, and are compatible with 16-bit dynamic range systems. The inputs can accept singleended or differential signals. An input pin is provided for each amplifier to set the common mode level of the differential outputs. Internal laser-trimmed resistors and capacitors determine a precise, very well matched (in gain and phase) 7MHz 2nd order filter response. A single optional external resistor per channel can tailor the frequency response for each amplifier. Three-state BIAS pins determine each amplifier’s power consumption, allowing a choice between shutdown, medium power or full power. The LTC6605-7 is available in a compact 6mm × 3mm 22-pin leadless DFN package and operates over a –40°C to 85°C temperature range. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n n n n n n n Two Matched 7MHz 2nd Order Lowpass Filters with Differential Amplifiers Gain Match: ±0.35dB Max, Passband Phase Match: ±1.2° Max, Passband Single-Ended or Differential Inputs < –90dBc Distortion in Passband 2.1nV/√Hz Op Amp Noise Density Pin-Selectable Gain (0dB/12dB/14dB) Pin-Selectable Power Consumption (0.35mA/ 16.2mA/33.1mA) Rail-to-Rail Output Swing Adjustable Output Common Mode Voltage Control Buffered, Low Impedance Outputs 2.7V to 5.25V Supply Voltage Small 22-Pin 6mm × 3mm × 0.75mm DFN Package APPLICATIONS n n n n n WCDMA ADC Driver/Filter Antialiasing Filter Single-Ended to Differential Conversion DAC Smoothing Filter Zero-IF Direct Conversion Receivers TYPICAL APPLICATION Dual, Matched 6.5MHz Lowpass Filter + VINA 3V 1 2 3 4 22 Channel to Channel Phase Matching 120 292 TYPICAL UNITS TA = 25°C fIN = 7MHz + – LTC6605-7 21 20 19 18 17 16 0.1μF 0.1μF 3V – NUMBER OF UNITS VOUTA + 100 80 60 40 20 0 – + VINB 3V 5 6 7 8 9 10 + – 15 0.1μF 14 13 12 66057 TA01 3V – VOUTB + 0.1μF – 11 –1.2 –0.8 0 0.4 0.8 –0.4 PHASE MATCH (DEG) 1.2 66057 TA01b 66057f 1 LTC6605-7 ABSOLUTE MAXIMUM RATINGS (Note 1) PIN CONFIGURATION TOP VIEW +IN4 A +IN1 A BIAS A –IN1 A –IN4 A V– +IN4 B +IN1 B BIAS B 1 2 3 4 5 6 7 8 9 23 22 –OUT A 21 V+ A 20 V– 19 VOCMA 18 +OUT A 17 V– 16 –OUT B 15 V+ B 14 V– 13 VOCMB 12 +OUT B Total Supply Voltage (V+ to V–) ................................5.5V Input Current (Note 2)..........................................±10mA Output Short-Circuit Duration (Note 3) ............ Indefinite Operating Temperature Range (Note 4).... –40°C to 85°C Specified Temperature Range (Note 5) .... –40°C to 85°C Junction Temperature ........................................... 150°C Storage Temperature Range................... –65°C to 150°C –IN1 B 10 –IN4 B 11 DJC PACKAGE 22-LEAD (6mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 46.5°C/W , EXPOSED PAD (PIN 23) IS V – MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC6605CDJC-7#PBF LTC6605IDJC-7#PBF TAPE AND REEL LTC6605CDJC-7#TRPBF LTC6605IDJC-7#TRPBF PART MARKING* 66057 66057 PACKAGE DESCRIPTION 22-Lead (6mm × 3mm) Plastic DFN 22-Lead (6mm × 3mm) Plastic DFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ DC ELECTRICAL CHARACTERISTICS + The l d–enotes the specifications which apply over the full operating + SYMBOL VOS ΔVOS /ΔT IB IOS PARAMETER Differential Offset Voltage (at Op Amp Inputs) (Note 6) Differential Offset Voltage Drift (at Op Amp Inputs) Input Bias Current (at Op Amp Inputs) (Note 7) Input Offset Current (at Op Amp Inputs) (Note 7) CONDITIONS VS = 2.7V to 5V BIAS = V+ BIAS = Floating BIAS = V+ BIAS = Floating l l l l l temperature range, otherwise specifications are at TA = 25°C. V = 3V, V = 0V, VINCM = VOCM = mid-supply, BIAS tied to V , RL = Open, RBAL = 10k. The filter is configured for a gain of 1, unless otherwise noted. VS is defined as (V + – V – ). VOUTCM is defined as (V+OUT + V–OUT)/2. VINCM is defined as (VINP + VINM)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is defined as (VINP – VINM). See Figure 1. MIN TYP ±0.25 ±1 ±1 –60 –30 –25 –12.5 ±1 0 0 MAX ±1 UNITS mV μV/°C μV/°C μA μA μA 66057f 2 LTC6605-7 DC ELECTRICAL CHARACTERISTICS + The l d–enotes the specifications which apply over the full operating + SYMBOL VINCM CMRR PSRR VOSCM VOCM VMID RVOCM VOUT PARAMETER Input Common Mode Voltage Range (Note 8) Common Mode Rejection Ratio (ΔVINCM /ΔVOS) (Note 9) Power Supply Rejection Ratio (ΔVS /ΔVOS) (Note 10) Common Mode Offset Voltage (VOUTCM – VOCM) Output Common Mode Range (Valid Range for VOCM Pin) (Note 8) Self-Biased Voltage at the VOCM Pin Input Resistance of VOCM Pin Output Voltage Swing, High (Measured Relative to V+) VS = 3V; IL = 0mA VS = 3V; IL = 5mA VS = 3V; IL = 20mA VS = 5V; IL = 0mA VS = 5V; IL = 5mA VS = 5V; IL = 20mA Output Voltage Swing, Low (Measured Relative to V –) VS = 3V; IL = 0mA VS = 3V; IL = – 5mA VS = 3V; IL = –20mA VS = 5V; IL = 0mA VS = 5V; IL = – 5mA VS = 5V; IL = –20mA ISC VS IS Output Short-Circuit Current (Note 3) Supply Voltage Supply Current (per Channel) VS = 2.7V to 5V; BIAS = V+ VS = 2.7V to 5V; BIAS = Floating VS = 2.7V to 5V; BIAS = V – Referenced to V – Referenced to V – Referenced to V – V S = 3V VS = 5 V CONDITIONS V S = 3V VS = 5 V VS = 3V; ΔVINCM = 1.5V VS = 5V; ΔVINCM = 2.5V VS = 2.7V to 5V V S = 3V VS = 5 V V S = 3V VS = 5 V V S = 3V l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l temperature range, otherwise specifications are at TA = 25°C. V = 3V, V = 0V, VINCM = VOCM = mid-supply, BIAS tied to V , RL = Open, RBAL = 10k. The filter is configured for a gain of 1, unless otherwise noted. VS is defined as (V + – V – ). VOUTCM is defined as (V+OUT + V–OUT)/2. VINCM is defined as (VINP + VINM)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is defined as (VINP – VINM). See Figure 1. MIN –0.2 –0.2 46 46 66 74 74 95 ±10 ±10 1.1 1.1 1.475 12.5 1.5 18 245 285 415 350 390 550 120 135 195 175 200 270 ±40 ±50 2.7 33.1 16.2 0.35 0 1 2.3 1.05 100 1.15 150 400 400 ±70 ±95 5.25 45 26.5 1.6 0.4 1.5 VS 1.25 200 ±15 ±15 2 4 1.525 23.5 450 525 750 625 700 1000 225 250 350 325 360 475 TYP MAX 1.7 4.7 UNITS V V dB dB dB mV mV V V V kΩ mV mV mV mV mV mV mV mV mV mV mV mV mA mA V mA mA mA V V V V kΩ ns ns BIAS Pin Range for Shutdown BIAS Pin Range for Medium Power BIAS Pin Range for Full Power RBIAS tON tOFF BIAS Pin Input Resistance Turn-On Time Turn-Off Time BIAS Pin Self-Biased Voltage (Floating) Referenced to V – VS = 3V, VBIAS VS = 3V, VBIAS = V– to V+ = V+ to V– 66057f 3 LTC6605-7 AC ELECTRICAL CHARACTERISTICS + The l denotes the specifications which apply over the full operating – + temperature range, otherwise specifications are at TA = 25°C. V = 3V, V = 0V, VINCM = VOCM = mid-supply, VBIAS = V , unless otherwise noted. Filter configured as in Figure 2, unless otherwise noted. VS is defined as (V + – V – ). VOUTCM is defined as (V+OUT + V–OUT)/2. VINCM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is defined as (V+IN + V–IN). SYMBOL Gain PARAMETER Filter Gain CONDITIONS ΔVIN = ±0.125V, DC VINDIFF = 0.5VP-P, f = 3.5MHz VINDIFF = 0.5VP-P, f = 5.25MHz VINDIFF = 0.5VP-P, f = 7MHz VINDIFF = 0.5VP-P, f = 14MHz VINDIFF = 0.5VP-P, f = 35MHz ΔVIN = ±0.125V, DC VINDIFF = 0.5VP-P, f = 3.5MHz VINDIFF = 0.5VP-P, f = 5.25MHz VINDIFF = 0.5VP-P, f = 7MHz ΔVIN = ±0.125V, DC VINDIFF = 0.5VP-P, f = 3.5MHz VINDIFF = 0.5VP-P, f = 5.25MHz VINDIFF = 0.5VP-P, f = 7MHz VINDIFF = 0.5VP-P, f = 3.5MHz VINDIFF = 0.5VP-P, f = 5.25MHz VINDIFF = 0.5VP-P, f = 7MHz ΔVIN = ±0.125V, DC VINDIFF = 1VP-P, f = 3.5MHz BIAS = V+ BIAS = Floating l l l l l l l l l l l l l l MIN –0.25 –1.2 –2.55 –4.25 –11.95 –28 TYP ±0.05 –0.84 –2.08 –3.71 –11.3 –25.9 0 –43.4 –63.8 –81.9 MAX 0.25 –0.5 –1.65 –3.2 –10.7 –25 UNITS dB dB dB dB dB dB Deg Deg Deg Deg Phase Filter Phase ΔGain Gain Match (Channel-to-Channel) –0.2 –0.2 –0.3 –0.35 –1.0 –1.0 –1.2 11.85 ±0.05 ±0.05 ±0.05 ±0.05 ±0.2 ±0.2 ±0.2 12 –100 –55 –180 61 0.2 0.2 0.3 0.35 1.0 1.0 1.2 12.25 dB dB dB dB Deg Deg Deg dB dB ppm/°C ppm/°C μVRMS nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz pA/√Hz pA/√Hz dBc dBc dBc dBc ΔPhase Phase Match (Channel-to-Channel) 4V/V Gain Filter Gain in 4V/V Configuration Inputs at ±IN1 Pins, ±IN4 Pins Floating Channel Separation Filter Cut-Off Frequency Temperature Coefficient Integrated Output Noise (BW = 10kHz to 14MHz) f O TC Noise Input Referred Noise Density (f = 1MHz) BIAS = V+ Figure 4, Gain = 1 Figure 4, Gain = 4 Figure 4, Gain = 5 en in HD2 HD3 Voltage Noise Density Referred to Op Amp Inputs (f = 1MHz) Current Noise Density Referred to Op Amp Inputs (f = 1MHz) 2nd Harmonic Distortion fIN = 3MHz; VIN = 2VP-P Single-Ended 3rd Harmonic Distortion fIN = 3MHz; VIN = 2VP-P Single-Ended BIAS = V+ BIAS = Floating BIAS = V+ BIAS = Floating BIAS = V+ BIAS = Floating, RLOAD = 400Ω BIAS = V+ BIAS = Floating, RLOAD = 400Ω 21 5.2 4.2 2.1 2.6 3 2.1 –96 –80 –114 –95 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All pins are protected by steering diodes to either supply. If any pin is driven beyond the LTC6605-7’s supply voltage, the excess input current (current in excess of what it takes to drive that pin to the supply rail) should be limited to less than 10mA. Note 3: A heat sink may be required to keep the junction temperature below the Absolute Maximum Rating when the output is shorted indefinitely. Long-term application of output currents in excess of the Absolute Maximum Ratings may impair the life of the device. Note 4: Both the LTC6605C and the LTC6605I are guaranteed functional over the operating temperature range –40°C to 85°C. Note 5: The LTC6605C is guaranteed to meet specified performance from 0°C to 70°C. The LTC6605C is designed, characterized and expected to meet specified performance from –40°C to 85°C, but is not tested or QA sampled at these temperatures. The LTC6605I is guaranteed to meet specified performance from –40°C to 85°C. Note 6: Output referred voltage offset is a function of gain. To determine output referred voltage offset, or output voltage offset drift, multiply VOS by the noise gain (1 + GAIN). See Figure 3. Note 7: Input bias current is defined as the average of the currents flowing into the noninverting and inverting inputs of the internal amplifier and is calculated from measurements made at the pins of the IC. Input offset current is defined as the difference of the currents flowing into the noninverting and inverting inputs of the internal amplifier and is calculated from measurements made at the pins of the IC. 66057f 4 LTC6605-7 ELECTRICAL CHARACTERISTICS Note 8: See the Applications Information section for a detailed discussion of input and output common mode range. Input common mode range is tested by measuring the differential DC gain with VINCM = mid-supply, and again with VINCM at the input common mode range limits listed in the Electrical Characteristics table, with ΔVIN = ±0.25V, verifying that the differential gain has not deviated from the mid-supply common mode input case by more than 0.5%, and that the common mode offset (VOSCM) has not deviated from the mid-supply common mode offset by more than ±10mV. Output common mode range is tested by measuring the differential DC gain with VOCM = mid-supply, and again with voltage set on the VOCM pin at the output common range limits listed in the Electrical Characteristics table, verifying that the differential gain has not deviated from the mid-supply common mode input case by more than 0.5%, and that the common mode offset (VOSCM) has not deviated by more than ±10mV from the mid-supply case. Note 9: CMRR is defined as the ratio of the change in the input common mode voltage at the internal amplifier inputs to the change in differential input referred voltage offset (VOS). Note 10: Power supply rejection ratio (PSRR) is defined as the ratio of the change in supply voltage to the change in differential input referred voltage offset (VOS). TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Temperature 37.5 35.0 SUPPLY CURRENT (mA) 32.5 30.0 27.5 25.0 22.5 20.0 17.5 15.0 12.5 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 VS = 2.7V, BIAS = FLOAT VS = 3V, BIAS = FLOAT VS = 5V, BIAS = FLOAT VS = 2.7V, BIAS = V+ VS = 3V, BIAS = V+ VS = 5V, BIAS = V+ VINCM = VOCM = MID-SUPPLY 1.010 Filter Gain vs Temperature 1.005 GAIN (V/V) 1.000 0.995 VS = 3V, BIAS = V+ VINCM = VOCM = MID-SUPPLY 5 REPRESENTATIVE UNITS 0.990 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 66057 G01 66057 G02 –3dB Frequency vs Temperature 1.0 FREQUENCY SHIFT OF f–3dB (%) VS = 3V VINCM = VOCM = 1.5V GAIN MAGNITUDE (dB) 10 0 –10 –20 –30 –40 –50 Filter Frequency Response 0.5 0 –0.5 –1.0 BIAS = FLOAT BIAS = V+ –1.5 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 BIAS = V+ BIAS PIN FLOATING 1 10 100 FREQUENCY (MHz) 1000 66057 G04 –60 0.1 66057 G03 66057f 5 LTC6605-7 TYPICAL PERFORMANCE CHARACTERISTICS Harmonic Distortion vs Frequency, BIAS High –40 –50 –60 DISTORTION (dBc) –70 –80 –90 DIFFERENTIAL INPUT, HD2 DIFFERENTIAL INPUT, HD3 SINGLE-ENDED INPUT, HD2 SINGLE-ENDED INPUT, HD3 DISTORTION (dBc) –40 –50 –60 –70 –80 –90 DIFFERENTIAL INPUT, HD2 DIFFERENTIAL INPUT, HD3 SINGLE-ENDED INPUT, HD2 SINGLE-ENDED INPUT, HD3 DISTORTION (dBc) Harmonic Distortion vs Frequency, BIAS Floating –40 –50 –60 –70 –80 –90 –100 –110 –120 0.1 1 10 100 FREQUENCY (MHz) 66057 G06 VIN = 2VP-P, VS = 3V RL = 400Ω DIFFERENTIAL, GAIN = 1V/V Harmonic Distortion vs Input Amplitude DIFFERENTIAL INPUT, HD2 DIFFERENTIAL INPUT, HD3 SINGLE-ENDED INPUT, HD2 SINGLE-ENDED INPUT, HD3 –100 –110 –120 0.1 1 10 100 FREQUENCY (MHz) 66057 G05 VIN = 2VP-P, VS = 3V RL = 400Ω DIFFERENTIAL, GAIN = 1V/V –100 –110 –120 0 1 2 4 3 VIN (VP-P) 5 6 66057 G07 VS = 3V, BIAS TIED TO V+, VINCM = VOCM = 1.5V RLOAD = 400Ω, fIN = 3MHz, GAIN = 1V/ V Harmonic Distortion vs Input Common Mode Voltage (VS = 3V) –40 –50 –60 DISTORTION (dBc) –70 –80 –90 DIFFERENTIAL INPUT, HD2 DIFFERENTIAL INPUT, HD3 SINGLE-ENDED INPUT, HD2 SINGLE-ENDED INPUT, HD3 –40 –50 –60 DISTORTION (dBc) –70 –80 –90 Harmonic Distortion vs Input Common Mode Voltage (VS = 5V) NOISE SPECTRAL DENSITY (nV/√Hz) DIFFERENTIAL INPUT, HD2 DIFFERENTIAL INPUT, HD3 SINGLE-ENDED INPUT, HD2 SINGLE-ENDED INPUT, HD3 1000 Differential Output Noise vs Frequency VS = 3V BIAS TIED TO V+ 100 INTEGRATED NOISE (μVRMS) 100 10 10 OUTPUT NOISE SPECTRAL DENSITY INTEGRATED OUTPUT NOISE 1 0.01 0.1 1 10 FREQUENCY (MHz) 1 100 66057 G10 –100 –110 –120 –0.5 1.5 0 1 0.5 2 2.5 INPUT COMMON MODE VOLTAGE (V) 3 –100 –110 –120 –0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 INPUT COMMON MODE VOLTAGE (V) VIN = 2VP-P, VOCM = 2.5V BIAS = 5V, f = 3MHz RL = 400Ω DIFFERENTIAL, GAIN = 1V/V 66057 G09 VIN = 2VP-P, VOCM = 1.5V BIAS = 3V, f = 3MHz RL = 400Ω DIFFERENTIAL, GAIN = 1V/V 66057 G08 Channel Separation vs Frequency –20 –30 CHANNEL SEPARATION (dB) –40 –50 –60 –70 –80 –90 –1.0 –1.5 –2.0 1 1000 66057 G11 Overdrive Transient Response 2.O 1.5 1.O VOLTAGE (V) 0.5 0 –0.5 +OUT –OUT –IN4 +IN4 BIAS = V+ BIAS = FLOAT –100 –110 –120 0.1 10 100 FREQUENCY (MHz) VIN = 1VP-P, VS = 3V RL = 400Ω DIFFERENTIAL 50ns/DIV VS = 3V, VOCM = 1.5V BIAS = 3V, RLOAD = 400Ω 66057 G12 66057f 6 LTC6605-7 TEST CIRCUITS LTC6605-7 114.8pF 22 400Ω 1 69.3pF 21 V+ 0.1μF 0.1μF RBAL 400Ω IL V –OUT 25Ω + VINP 100Ω 2 125Ω – +– BIAS 3 BIAS 20 V– 0.1μF VOUTCM –+ – VINM V+ 36k 19 36k VOCM 0.01μF + 100Ω 4 125Ω 69.3pF RBAL 400Ω 5 400Ω 114.8pF V– IL 18 V +OUT 25Ω 66057 TC01 Figure 1. DC Test Circuit (Channel A Shown) LTC6605-7 1μF V +IN 1 114.8pF 22 V –OUT 100Ω 1μF 400Ω 400Ω 100Ω 2 125Ω 69.3pF 21 V+ 0.1μF 0.1μF COILCRAFT TTWB-4-B + VIN BIAS 3 BIAS +– 20 V– 0.1μF 50Ω – 100Ω 4 125Ω –+ 69.3pF V+ 36k 19 36k VOCM 0.01μF 1μF V –IN 5 400Ω 400Ω 114.8pF V– V +0UT 100Ω 1μF 18 66057 TC02 Figure 2. AC Test Circuit (Channel A Shown) 66057f 7 LTC6605-7 PIN FUNCTIONS +IN4 A, –IN4 A, +IN4 B, –IN4 B (Pins 1, 5, 7, 11): Inputs to Trimmed 400Ω Resistors. Can accept an input signal, be floated, tied to an output pin, or connected to external components. +IN1 A, –IN1 A, +IN1 B, –IN1 B (Pins 2, 4, 8, 10): Inputs to Trimmed 100Ω Resistors. Can accept an input signal, be floated, tied to an output pin, or connected to external components. BIAS A, BIAS B (Pins 3, 9): Three-State Input to Select Amplifier Power Consumption. Drive low for shutdown, drive high for full power, leave floating for medium power. BIAS presents an input resistance of approximately 150k to a voltage 1.15V above V –. V – (Pins 6, 14, 17, 20): Negative Supply. All V – pins should be connected to the same voltage, either a ground plane or a negative supply rail. VOCMA, VOCMB (Pins 19, 13): The voltage applied to these pins sets the output common mode voltage of each filter channel. If left floating, VOCM self-biases to a voltage midway between V+ and V –. V+ A, V+ B (Pins 21, 15): Positive Supply for Filter Channel A and B, Respectively. These are not connected to each other internally. –OUT A, +OUT A, –OUT B, +OUT B (Pins 22, 18, 16, 12): Differential Output Pins. Exposed Pad (Pin 23): Always tie the underlying Exposed Pad to V –. If split supplies are used, do not tie the pad to ground. 66057f 8 LTC6605-7 BLOCK DIAGRAM 114.8pF 22 –OUT A +IN4 A 1 400Ω 400Ω 100Ω +IN1 A 2 125Ω 69.3pF + 21 V A –+ BIAS A 3 BIAS 20 V – +– 100Ω –IN1 A 4 125Ω 69.3pF V+ A 36k 19 VOCMA 36k 400Ω –IN4 A 5 400Ω 114.8pF V– 18 +OUT A V– 6 17 V – 114.8pF 16 –OUT B +IN4 B 7 400Ω 400Ω 100Ω +IN1 B 8 125Ω 69.3pF 15 V + B –+ BIAS B 9 BIAS 14 V – +– 100Ω –IN1 B 10 125Ω 69.3pF V+ B 36k 13 VOCMB 36k 400Ω –IN4 B 11 400Ω 114.8pF V– 12 +OUT B 66057 BD 66057f 9 LTC6605-7 APPLICATIONS INFORMATION Functional Description The LTC6605-7 is designed to make the implementation of high frequency fully differential filtering functions very easy. Two very low noise amplifiers are surrounded by precision matched resistors and precision matched capacitors enabling various filter functions to be implemented by hard wiring pins. The amplifiers are wide band, low noise and low distortion fully differential amplifiers with accurate output phase balancing. They are optimized for driving low voltage, single-supply, differential input analog-todigital converters (ADCs). The LTC6605-7 operates with a supply voltage as low as 2.7V and accepts inputs up to 325mV below the V– power rail, which makes it ideal for converting ground referenced, single-ended signals into differential signals that are referenced to the user-supplied common mode voltage. This is ideal for driving low voltage, single-supply, differential input ADCs. The balanced differential nature of the amplifier and matched surrounding components provide even-order harmonic distortion cancellation, and low susceptibility to common mode noise (like power supply noise). The LTC6605-7 can be operated with a single-ended input and differential output, or with a differential input and differential output. The outputs of the LTC6605-7 can swing rail-to-rail. They can source or sink a transient 70mA of current. Load capacitances should be decoupled with at least 25Ω of series resistance from each output. Filter Frequency Response and Gain Adjustment Figure 3 shows the filter architecture. The Laplace transfer function can be expressed in the form of the following generalized equation for a 2nd order lowpass filter: VOUT(DIFF) VIN(DIFF) = GAIN s2 s + 1+ 2π fO • Q (2π f ) 2 O , with GAIN, fO and Q as given in Figure 3. Note that GAIN and Q of the filter are based on component ratios, which both match and track extremely well over temperature. The corner frequency fO of the filter is a function of an RC product. This RC product is trimmed to ±1% and is not expected to drift by more than ±1% from nominal over the entire temperature range –40°C to 85°C. As a result, fully differential filters with tight magnitude, phase tolerance and repeatability are achieved. Various values for resistors R1 and R4 can be formed by pin-strapping the internal 100Ω and 400Ω resistors, and optionally by including one or more external resistors. Note that non-zero source resistance should be combined with, and included in, R1. R2 400Ω C2 114.8pF R3 125Ω R4A VIN(DIFF) REXT C1 69.3pF + R1 +– –+ – VOUT(DIFF) + C1 69.3pF C2 114.8pF R4B – R1 R3 125Ω R2 400Ω R4 = R4A + R4B + REXT 66057 F03 Figure 3. Filter Architecture and Equations 66057f 10 LTC6605-7 APPLICATIONS INFORMATION Setting the passband gain (GAIN = R2/R1) only requires choosing a value for R1, since R2 is a fixed internal 400Ω. Therefore, the following three gains can be easily configured without external components: Table 1. Configuring the Passband Gain Without External Components GAIN (V/V) 1 4 5 GAIN (dB) 0 12 14 R1 (Ω) 400 100 80 INPUT PINS TO USE Drive the 400Ω Resistors. Tie the 100Ω Resistors Together. Drive the 100Ω Resistors. Drive the 400Ω and 100Ω Resistors in Parallel. filters have a Q = 0.59, which is an almost ideal Bessel characteristic with linear phase. Figure 5 shows three filter configurations that use some external resistors, and are tailored for a very flat ±0.4dB 6.7MHz passband. Many other configurations are possible by using the equations in Figure 3. For example, external resistors can be added to modify the value of R1 to configure GAIN ≠ 1. For an even more flexible filter IC with similar performance, consider the LTC6601. BIAS Pin Each channel of the LTC6605-7 has a BIAS pin whose function is to tailor both performance and power. The BIAS pin can be modeled as a voltage source whose potential is 1.15V above the V– supply and that has a Thevenin equivalent resistance of 150k. This three-state pin has fixed logic levels relative to V– (see the Electrical Characteristics table), and can be driven by any external source that can drive the BIAS pin’s equivalent input impedance. If the BIAS pin is tied to the positive supply, the part is in a fully active state configured for highest performance (lowest noise and lowest distortion). If the BIAS pin is floated (left unconnected), the part is in a fully active state, but with amplifier currents reduced and performance scaled back to preserve power consumption. Care should be taken to limit external leakage currents to this pin to under 1μA to avoid putting the part in an unexpected state. If the BIAS pin is tied to the most negative supply (V–), the part is in a low power shutdown mode with amplifier outputs disabled. In shutdown, all internal biasing current sources are shut off, and the output pins each appear as open collectors with a non-linear capacitor in parallel and steering diodes to either supply. Because of the non-linear capacitance, the outputs can still sink and source small amounts of transient current if exposed to significant voltage transients. Using this function to wire-OR outputs together is not recommended. The resonant frequency, fO , is independent of R1, and therefore independent of the gain. For any LTC6605-7 filter configuration that conforms to Figure 3, the fO is fixed at 7.98MHz. The f–3dB frequency depends on the combination of fO and Q. For any specific gain, Q is adjusted by the selection of R4. Setting the f–3dB Frequency Using an external resistor (REXT), the f–3dB frequency is adjustable in the range of 6.5MHz to 10.0MHz (see Figure 3). The minimum f–3dB is set for REXT equal to 0Ω and the maximum f–3dB is arbitrarily set for a maximum passband gain less than 1dB. Table 2. REXT Selection GAIN = 1, R1 = 400Ω, R4A = R4B = 100Ω f–3dB (MHz) 6.5 7 7.5 8 8.5 9 9.5 10 REXT Ω 0 12.7 24.9 39.2 54.9 73.2 95.3 124 Figure 4 shows three filter configurations with an f–3dB = 6.5MHz, without any external components. These 66057f 11 LTC6605-7 APPLICATIONS INFORMATION 1 2 4 5 22 1 2 4 18 5 22 1 2 4 18 5 22 + – + – + – 18 7 8 10 11 16 7 8 10 16 7 8 10 16 + – 12 66057 F04a + – 12 66057 F04b + – 12 66057 F04c 11 11 f–3dB = 6.5MHz GAIN = 1V/ V (0dB) ZIN = 800Ω f–3dB = 6.5MHz GAIN = 4V/ V (12dB) ZIN = 200Ω f–3dB = 6.5MHz GAIN = 5V/ V (14dB) ZIN = 160Ω Gain Response 20 10 GAIN MAGNITUDE (dB) GAIN MAGNITUDE (dB) 0 –10 –20 –30 –40 –50 0.1 20 10 0 –10 –20 –30 –40 –50 0.1 Gain Response 20 10 GAIN MAGNITUDE (dB) 0 –10 –20 –30 –40 –50 0.1 Gain Response 1 100 10 FREQUENCY (MHz) 1000 66057 F04d 1 10 100 FREQUENCY (MHz) 1000 66057 F04e 1 10 100 FREQUENCY (MHz) 1000 66057 F04f Phase and Group Delay Response 0 40 35 –50 PHASE (DEG) GROUP DELAY 30 GROUP DELAY (ns) 25 20 –150 PHASE 15 10 –200 5 –250 0.1 1 10 100 FREQUENCY (MHz) 0 1000 66057 F04g Small Signal Step Response GAIN = 1V/ V –100 100mV/DIV 20ns/DIV 66057 G04h Figure 4. f–3dB = 6.5MHz Filter Configurations without External Components 66057f 12 LTC6605-7 APPLICATIONS INFORMATION 1 2 80.6Ω 4 5 22 1 40.2Ω 2 40.2Ω 4 18 5 22 1 40.2Ω 2 40.2Ω 4 18 5 22 + – + – + – 18 7 8 80.6Ω 10 11 16 7 40.2Ω 8 40.2Ω 10 16 7 40.2Ω 8 40.2Ω 10 16 + – 12 66057 F05a + – 12 66057 F05b + – 12 66057 F05c 11 11 ±0.4dB 6.7MHz PASSBAND GAIN = 1V/ V (0dB) ZIN = 800Ω ±0.4dB 6.7MHz PASSBAND GAIN = 2.85V/ V (9.1dB) ZIN = 280Ω ±0.4dB 6.7MHz PASSBAND GAIN = 3.85V/ V (11.7dB) ZIN = 208Ω Gain Response 20 10 GAIN MAGNITUDE (dB) 0 –10 –20 –30 –40 –50 0.1 GAIN MAGNITUDE (dB) 20 10 Gain Response 20 10 GAIN MAGNITUDE (dB) 0 –10 –20 –30 –40 –50 0.1 Gain Response 0 –10 –20 –30 –40 –50 0.1 1 100 10 FREQUENCY (MHz) 1000 66057 F05d 1 100 10 FREQUENCY (MHz) 1000 66057 F05e 1 10 100 FREQUENCY (MHz) 1000 66057 F05f Phase and Group Delay Response 0 35 30 –50 25 PHASE (DEG) –100 GROUP DELAY 20 15 PHASE –200 5 –250 0.1 0 1000 66057 F05g Small Signal Step Response GAIN = 1V/ V GROUP DELAY (ns) 100mV/DIV –150 10 1 10 100 FREQUENCY (MHz) 20ns/DIV 66057 G05h Figure 5. Flat Passband 6.7MHz Filter Configurations with Some External Resistors 66057f 13 LTC6605-7 APPLICATIONS INFORMATION Input Impedance Calculating the low frequency input impedance depends on how the inputs are driven. Figure 6 shows a simplified low frequency equivalent circuit. For balanced input sources (VINP = –VINM), the low frequency input impedance is given by the equation: RINP = RINM = R1 Therefore, the differential input impedance is simply: RIN(DIFF) = 2 • R1 R2 RINP the ESD protection diodes on the input pins, neither input should swing further than 325mV below the V– power rail. Therefore, the input common mode voltage should be constrained to: V − – 325mV + ⎛ R1 ⎞ VINDIFF ≤ VINCM ≤ ⎜1+ ⎟ 2 ⎝ R2 ⎠ ⎛ R1 ⎞ • V + − 1.4V − ⎜ ⎟ VOCM ⎝ R2 ⎠ ( ) + VINP R1 R3 – + VOUT– – – VINM The specifications in the Electrical Characteristics table are a special case of the general equation above. For a single 3V power supply, (V+ = 3V, V – = 0V) with VOCM = 1.5V, ΔVINDIFF = ±0.25V and R1 = R2, the valid input common mode range is: –200mV ≤ VINCM ≤ 1.7V Likewise, for a single 5V power supply, (V+ = 5V, V – = 0V) with VOCM = 2.5V, ΔVINDIFF = ±0.25V and R1 = R2, the valid input common mode range is: –200mV ≤ VINCM ≤ 4.7V Output Common Mode and VOCM Pin The output common mode voltage is defined as the average of the two outputs: VOUTCM = VOCM = VOUT + + VOUT − 2 R3 R1 RINM R2 VOUTDIFF – + + VOUT+ VOCM 0.1μF 66057 F06 Figure 6. Input Impedance For single-ended inputs (VINM = 0), the input impedance increases over the balanced differential case due to the fact that the summing node (at the junction of R1, R2 and R3) moves in phase with VINP to bootstrap the input impedance. Referring to Figure 6 with VINM = 0, the input impedance looking into either input is: R1 RINP = RINM R2 1 • 1 2 R1+ R2 Input Common Mode Voltage Range The input common mode voltage is defined as the average of the two inputs into resistor R1: VINCM = VINP + VINM 2 As the equation shows, the output common mode voltage is independent of the input common mode voltage, and is instead determined by the voltage on the VOCM pin, by means of an internal feedback loop. If the VOCM pin is left open, an internal resistor divider develops a potential halfway between the V+ and V– voltages. The VOCM pin can be overdriven to another voltage if desired. For example, when driving an ADC, if the ADC makes a reference available for setting the common mode voltage, it can be directly tied to the VOCM pin, as long as the ADC is capable of driving the input impedance presented by the VOCM pin as listed in the Electrical Characteristics table (RVOCM). The Electrical Characteristics table also specifies the valid range that can be applied to the VOCM pin. 66057f The input common mode range is a function of the filter configuration (GAIN), VINDIFF and the VOCM potential. Referring to Figure 6, the summing junction where R1, R2 and R3 merge together should not swing within 1.4V of the V+ power supply. Additionally, to avoid forward biasing 14 LTC6605-7 APPLICATIONS INFORMATION Noise When comparing the LTC6605-7’s noise to that of other amplifiers, be sure to compare similar specifications. Standalone op amps often specify noise referred to the inputs of the op amp. The LTC6605-7’s internal op amp has input referred voltage noise of only 2.1nV/√Hz. In addition to the noise generated by the amplifier, the surrounding feedback resistors also contribute noise. A noise model is shown in Figure 7a. The output spot noise generated by both the amplifier and the feedback components is given in Figure 7b. Substituting the equation for Johnson noise of a resistor (e2nR = 4kTR) into the equation in Figure 7b and simplifying gives the result shown in Figure 7c. Board Layout and Bypass Capacitors For single-supply applications it is recommended that a high quality X5R or X7R, 0.1μF bypass capacitor be placed directly between V+ and the adjacent V– pin. The V– pins, including the Exposed Pad, should be tied directly to a low impedance ground plane with minimal routing. enR22 enR12 R2 R1 enR32 In+2 R3 eni2 + eno2 enR32 enR12 R1 R3 In–2 enR22 – R2 66057 F07a Figure 7a. Differential Noise Model eno = R2 eni • 1+ R1 2 R2 + 2 • In • R2 + R3 • 1+ R1 2 + 2 • e nR1 • R2 R1 2 + 2 • enR3 • 1+ R2 R1 2 + 2 • enR2 2 Figure 7b eno = eni • 1+ R2 R1 2 + 2 • In • R2 + R3 • 1+ R2 R1 2 + 8 • k • T • R2 • 1+ R2 R2 + R3 • 1+ R1 R1 2 Figure 7c 66057f 15 LTC6605-7 APPLICATIONS INFORMATION For split power supplies, it is recommended that additional high quality X5R or X7R, 0.1μF capacitors be used to bypass pin V+ to ground and V– to ground, again with minimal routing. For driving heavy differential loads (< 200Ω), additional bypass capacitance may be needed between V+ and V– for optimal performance. Keep in mind that small geometry (e.g., 0603) surface mount ceramic capacitors have a much higher self-resonant frequency than do leaded capacitors, and perform best in high speed applications. The VOCM pins should be bypassed to ground with a high quality ceramic capacitor (at least 0.01μF). In split-supply applications, the VOCM pin can be either bypassed to ground or directly hard wired to ground. Stray parasitic capacitances to any unused input pins should be kept to a minimum to prevent deviations from the ideal frequency response. The best approach is to remove the solder pads for the unused component pins and strip away any ground plane underneath. Floating unused pins does not reduce the reliability of the part. At the output, always keep in mind the differential nature of the LTC6605-7, because it is important that the load impedances seen by both outputs (stray or intended) be as balanced and symmetric as possible. This will help preserve the balanced operation that minimizes the generation of even-order harmonics and maximizes the rejection of common mode signals and noise. Driving ADCs The LTC6605-7’s rail-to-rail differential output and adjustable output common mode voltage make it ideal for interfacing to differential input ADCs. These ADCs are typically supplied from a single-supply voltage which can be as low as 3V (2.7V minimum), and have an optimal common mode input range near mid-supply. The LTC6605-7 makes interfacing to these ADCs easy, by providing antialiasing, single-ended to differential conversion and common mode level shifting. The sampling process of ADCs creates a transient that is caused by the switching in of the ADC sampling capacitor. This momentarily “shorts” the output of the amplifier as charge is transferred between amplifier and sampling capacitor. The amplifier must recover and settle from this load transient before the acquisition period has ended, for a valid representation of the input signal. The LTC6605-7 will settle quickly from these periodic load impulses. The RC network between the outputs of the driver decouples 66057f 16 LTC6605-7 APPLICATIONS INFORMATION the sampling transient of the ADC (see Figure 8). The capacitance serves to provide the bulk of the charge during the sampling process, while the two resistors at the outputs of the LTC6605-7 are used to dampen and attenuate any charge injected by the ADC. The RC filter gives the additional benefit of band limiting broadband output noise. The selection of the RC time constant is trial and error for a given ADC, but the following guidelines are recommended. Choose an RC time constant that is smaller than the reciprocal of the filter cutoff frequency configured by the LTC6605-7. Time constants on the order of 2ns do a good job of filtering broadband noise. Longer time constants improve SNR at the expense of settling time. The resistors in the decoupling network should be at least 25Ω. Too large of a resistor will leave insufficient settling time. Too small of a resistor will not properly dampen the load transient of the sampling process, prolonging the time required for settling. In 16-bit applications, this will typically require a minimum of eleven RC time constants. The 10Ω resistors at the inputs to the ADC minimize the sampling transients that charge the RC filter capacitors. For lowest distortion, choose capacitors with low dielectric absorption, such as a C0G multilayer ceramic capacitor. 1/2 LTC6605-7 VIN R 22 21 0.1μF 20 3V 1μF C2 + – BIAS 1 2 3 4 5 C1 10Ω 10Ω CONTROL D15 • • + – AIN+ AIN– VCM ADC D0 3.3V GND 2.2μF 1μF 19 18 10nF VOCM R C1 CHANNEL A τ = R • (C1 + 2 • C2) 66057 F08 Figure 8. Driving an ADC 66057f 17 LTC6605-7 TYPICAL APPLICATIONS Dual, Matched, 4th Order 7MHz Lowpass Filter LTC6605-7 1 2 VINA 4 5 22 1 2 243Ω 4 18 5 LTC6605-7 22 + – + VOUTA – 18 7 8 VINB 10 11 16 7 8 243Ω 10 16 + – 12 + VOUTB – 12 66057 TA02 11 THREE GAINS ARE POSSIBLE, AS SHOWN IN FIGURE 4 Gain Magnitude vs Frequency 10 0 –10 –20 GAIN (dB) –30 –40 –50 –60 –70 –80 0.1 1 10 FREQUENCY (MHz) 100 66057 TA03 66057f 18 LTC6605-7 PACKAGE DESCRIPTION DJC Package 22-Lead Plastic DFN (6mm × 3mm) (Reference LTC DWG # 05-08-1714) 0.889 0.70 ± 0.05 R = 0.10 0.889 PACKAGE OUTLINE NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 3. DRAWING IS NOT TO SCALE 3.60 ± 0.05 1.65 ± 0.05 2.20 ± 0.05 (2 SIDES) 0.25 ± 0.05 0.50 BSC 5.35 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 22 6.00 ± 0.10 (2 SIDES) R = 0.10 TYP 0.889 12 0.40 ± 0.05 3.00 ± 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) 1.65 ± 0.10 (2 SIDES) 0.889 11 0.200 REF 0.75 ± 0.05 5.35 ± 0.10 (2 SIDES) 1 0.25 ± 0.05 0.50 BSC (DJC) DFN 0605 PIN #1 NOTCH R0.30 TYP OR 0.25mm × 45° CHAMFER 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 5. EXPOSED PAD SHALL BE SOLDER PLATED 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX) 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION IN JEDEC PACKAGE OUTLINE M0-229 ON TOP AND BOTTOM OF PACKAGE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 66057f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC6605-7 TYPICAL APPLICATION Dual, Matched, 3rd Order 3.5MHz Lowpass Filter 301Ω 1 470pF 1% 301Ω 5 301Ω 7 470pF 1% 301Ω 11 8 10 16 2 4 LTC6605-7 22 + VOUTA VINA – 18 + VOUTB VINB – 12 66057 TA04 Gain Magnitude vs Frequency 10 0 –10 –20 GAIN (dB) –30 –40 –50 –60 –70 –80 0.1 1 10 FREQUENCY (MHz) 100 66057 TA05 RELATED PARTS PART NUMBER LT1568 LTC6404 LTC6406 LT6600-2.5/LT6600-5/ LT6600-10/LT6600-15/ LT6600-20 LTC6601 LT6604-2.5/LT6604-5 DESCRIPTION 4th Order Filter Building Block Rail-to-Rail Output Differential Op Amp 3GHz Rail-to-Rail Input Differential Op Amp Differential 4th Order Lowpass Filters COMMENTS Lowpass and Bandpass Responses Up to 10MHz 1.5nV/√ Hz Noise, –95dBc Distortion at 10MHz 1.6nV/√Hz Noise, –72dBc Distortion at 50MHz, 18mA Cut-Off Frequencies of 2.5MHz/5MHz/10MHz/15MHz/20MHz Differential Pin-Configurable 2nd Order Filter Building Block Dual Differential 4th Order Lowpass Filters 7MHz to 25MHz Pin-Configurable Cut-Off Frequencies of 2.5MHz or 5MHz 66057f 20 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 1208 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008