LTC6801IG

Electrical Specifications Subject to Change LTC6801 Independent Multicell Battery Stack Fault Monitor FEATURES n DESCRIPTION The LTC®6801 is a multicell battery monitoring IC incorporating a 12-bit ADC, a precision independent voltage reference, sampled comparator, and a high voltage input multiplexer. The LTC6801 can monitor as many as 12 series connected battery cells for overvoltage, undervoltage, and overtemperature conditions, indicating whether the cells are within specified parameters. The LTC6801 generates a clock output when no fault conditions exist. Differential clocking provides high noise immunity and ensures that battery stack fault conditions cannot be hidden by frozen bits or short circuit conditions. Each LTC6801 can operate with a battery stack voltage up to 60V and multiple LTC6801 devices can be stacked to monitor each individual cell in a long battery string. When multiple devices are stacked, the status signal of each LTC6801 can be daisy-chained, without opto-couplers or isolators, providing a single status output for the entire battery string. The LTC6801 is configurable by external pin strapping. Adjustable overvoltage and undervoltage thresholds support various Li-Ion chemistries. Selectable measurement times allow users to save power. Monitors Up to 12 Li-Ion Cells in Series (60V Max) n Stackable Architecture Enables > 1000V Systems n Adjustable Overvoltage and Undervoltage Detection n Self Test Features Guarantee Accuracy n Robust Fault Detection Using Differential Signals n Simple Pin-Strapped Configuration Allows Battery Monitoring without a Microcontroller n 15ms to Monitor All Cells in a System n Programmable Response Time nT wo Temperature Monitor Inputs n Low Power Idle Mode n 36-Lead SSOP Package APPLICATIONS n n n n Redundant Battery Monitor Hybrid Electric Vehicles Battery Backup Systems Power Systems Using Multiple Battery Cells L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. BLOCK DIAGRAM NEXT HIGHER CELL PACK 1 V+ 2 3 C12 C11 ERROR (%) CONTROL LOGIC ENABLE INPUT “CELLS GOOD” ISOLATION 20 CLOCK SIGNAL INPUT ENABLES THE LTC6801 LTC6801 0V Detection Level Error 1.0 V+ = 43.2V 0.8 OV = 4.120V 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 6801 TA01b 5 TYPICAL UNITS 12 13 14 C2 C1 V– MUX ADC 12 NEXT LOWER CELL PACK REFERENCE VTEMP1 15 NTC NTC VTEMP2 16 VREF 17 22 STATUS OUTPUT 6801 TA01a CLOCK SIGNAL OUTPUT INDICATES SYSTEM “OK” 6801p 1 LTC6801 ABSOLUTE MAXIMUM RATINGS (Note 1) PIN CONFIGURATION TOP VIEW V+ C12 C11 C10 C9 C8 C7 C6 C5 1 2 3 4 5 6 7 8 9 36 OV1 35 OV0 34 UV1 33 UV0 32 HYST 31 CC1 30 CC0 29 SLT 28 SLTOK 27 DC 26 EOUT 25 EOUT 24 SIN 23 SIN 22 SOUT 21 SOUT 20 EIN 19 EIN Total Supply Voltage (V+ to V–) .................................60V Input Voltage (Relative to V–) C1 ............................................................ –0.3V to 9V C12 ...........................................V+ –0.3V to V+ + 0.3V All Other Pins (Not C Inputs) ................... –0.3V to 7V Voltage Between Inputs Cn to Cn-1* ............................................. –0.3V to 9V C12 to C8 ............................................... –0.3V to 25V C8 to C4 ................................................. –0.3V to 25V C4 to V– ................................................. –0.3V to 25V Operating Temperature Range.................. –40°C to 85°C Specified Temperature Range .................. –40°C to 85°C Junction Temperature ........................................... 150°C Storage Temperature Range................... –65°C to 150°C *n = 2 to 12 C4 10 C3 11 C2 12 C1 13 V– 14 VTEMP1 15 VTEMP2 16 VREF 17 VREG 18 G PACKAGE 36-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 70°C/W ORDER INFORMATION LEAD FREE FINISH LTC6801IG#PBF TAPE AND REEL LTC6801IG#TRPBF PART MARKING LTC6801IG PACKAGE DESCRIPTION 36-Lead Plastic SSOP SPECIFIED TEMPERATURE RANGE –40°C to 85°C Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 6801p 2 LTC6801 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, V+ = 43.2V, V– = 0V unless otherwise noted. SYMBOL VERR PARAMETER Measurement Error CONDITIONS VCELL > 0.8V, 10V < V+ < 50V VCELL > 0.8V, 10V < V+ < 50V VCELL ≤ 0.8V, 10V < V+ < 50V VCELL ≤ 0.8V, 10V < V+ < 50V Full Scale Voltage Range VERR Specifications Met Range of Inputs Cn, n = 3 to 11 Range of Input C2 Range of Input C1 Programmed for 4.128V, Increasing VCELL, 10V < V+ < 50V Programmed for 2.112V, Decreasing VCELL, 10V < V+ < 50V 10V < V+ < 50V 10V < V+ < 50V VREF Pin Loaded With 100k to V– l l l l l l l ELECTRICAL CHARACTERISTICS MIN –0.5 –1 –1.5 –2 TYP MAX 0.5 1 1.5 2 UNITS % % % % V DC Specifications l l VCELL VCM Cell Voltage Range Common Mode Voltage Range Measured Relative to V– 5 1.8 1.2 0 4.079 2.087 –18 –25 3.043 3.038 3.058 3.058 5 50 60 4.120 2.108 5•n 10 5 4.161 2.129 12 25 3.073 3.078 V V V V V mV % V V ppm/˚C ppm ppm/√khr VOV VUV VTV HYS VREF Overvoltage (OV) Detection Level Undervoltage (UV) Detection Level Temperature Input Detection Level Error (Relative to VREF /2) UV/OV Detection Hysteresis Error (Relative to Selected Value) Reference Pin Voltage Reference Voltage Temperature Coefficient Reference Voltage Hysteresis Reference Voltage Long Term Drift l VREG Regulator Pin Voltage Regulator Pin Short Circuit Current Limit 10 < VS < 50, No Load 10 < VS < 50, ILOAD = 4mA VERR Specifications Met In/Out of Pins C1 Thru C12 When Measuring Cells During Self Test When Measuring Cells When Idle Current Into the V+ Pin While Monitoring for UV and OV Conditions, FENA = 10kHz Continuous Monitoring Monitor Every 130ms Monitor Every 500ms Current into the V+ Pin When Idle, FENA = 0 DC = CC1 = CC0 = VREG l l l l 4.5 4.1 5 10 5 4.8 9 5.5 V V mA V μA μA nA VS IB Supply Voltage, V+ Relative to V– Input Bias Current 50 100 l –10 1 10 IM Supply Current, Monitor Mode l 500 700 200 90 30 15.5 1000 μA μA μA μA ms kHz μs % V IQS TCYCLE FENA TENA DCENA VIH VIL VODL VOH VOL Supply Current, Idle Measurement Cycle Time Valid EIN/EIN Frequency Valid EIN/EIN Period = 1/ FENA Valid EIN/EIN Duty Cycle Digital Input Voltage High Digital Input Voltage Low Digital Output Voltage Low, Open Drain Digital Output Voltage High Digital Output Voltage Low l l l l l l l l l l 20 13.5 2 20 40 2 40 17.5 50 500 60 LTC6801 Timing Specifications FENA = 50kHz SLT Pin SLT Pin SLT Pin, 10k to VREG SLTOK Pin, 10k to V– SLTOK Pin, 10k to VREG LTC6801 Single Ended Digital I/O Specifications (SLT, SLTOK Pins) 0.5 0.3 VREG – 0.3 0.3 V V V V 6801p 3 LTC6801 The d the ELECTRICAL CHARACTERISTICS25°C, Vl = enotes V– =specifications which apply over the full operating + 43.2V, temperature range, otherwise specifications are at T = 0V unless otherwise noted. A SYMBOL IPU-ST VIDH VIDL VIL VIH VDHYS VOPEN RINCM RINDIFF VODH VODL V3IH V3IM V3IL IPU IPD PARAMETER Pull-Up Current Minimum Differential Input Voltage High Minimum Differential Input Voltage Low Valid Input Voltage Low Valid Input Voltage High Differential Input Hysteresis Open Circuit Voltage Input Resistance, Common Mode Input Resistance, Differential Digital Output Voltage High Digital Output Voltage Low Three-Level Digital Input Voltage High Three-Level Digital Input Voltage Mid Three-Level Digital Input Voltage Low Pull-Up Current Pull-Down Current CONDITIONS SLT Pin Differential Voltage Applied Between SIN and SIN or EIN and EIN Low Side of Differential Signal, Ref. to V– High Side of Differential Signal, Ref. to V– l l l l l l l MIN 2.5 1.7 TYP 5 MAX 10 UNITS μA V LTC6801 Differential Digital Input Specifications (SIN/SIN, EIN/EIN Pins) (See Figure 1) –1.7 0 2.5 1 2 100 200 2.5 150 300 3 1.2 6 V V V V V kΩ kΩ V 0.3 V V VREF + 0.3 0.3 0.5 0.5 1 1 2 2 V V μA μA Between SIN to SIN, EIN to EIN Output Pins Loaded With 100k to V– Output Pins Loaded With 100k to VREG l LTC6801 Differential Digital Output Specifications (SOUT/SOUT, EOUT/EOUT Pins) l VREG – 0.3 l l VREG – 0.3 l VREF – 0.3 l LTC6801 Three-Level Digital Input Specifications (OV0, OV1, UV0, UV1, HYST, DC, CC0 and CC1 Pins) Pins DC, CC0, CC1, UV0 and UV1 Pins HYST, OV0 and OV1 l l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. EIN MAX, VIH VIDH (VALID HIGH WHEN EIN – EIN ≥ VIDH) TENA MIN, VIH MAX, VIL EIN VIDL (VALID LOW WHEN EIN – EIN ≤ VIDL) V– = 0V 6801 F01 Figure 1. Differential Input Specifications 6801p 4 LTC6801 TYPICAL PERFORMANCE CHARACTERISTICS Supply Current, Monitor Mode 800 DC PIN TIED TO VREG 780 fENA = 10kHz 760 740 ISUPPLY (μA) ISUPPLY (μA) 720 700 680 660 640 620 600 0 10 20 30 V+ (V) 6801 G01 Supply Current, Monitor Mode 250 CC1 = CC0 = VREG fENA = 10kHz 40 35 Supply Current, Idle Mode 85°C 200 30 150 DC PIN = VREF ISUPPLY (μA) 25 25°C 85°C 25°C –40°C 20 15 10 100 DC PIN = V– 50 85°C 25°C –40°C 10 20 30 V+ (V) 6801 G02 –40°C 5 0 10 20 30 V+ (V) 6801 G03 40 50 60 40 50 60 40 50 60 Supply Current, Monitor Mode 800 DC PIN TIED TO VREG 780 fENA = 10kHz 760 740 ISUPPLY (μA) ISUPPLY (μA) 720 700 680 660 640 620 600 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 6801 G04 Supply Current, Monitor Mode 250 CC1 = CC0 = VREG fENA = 10kHz 40 35 30 ISUPPLY (μA) DC PIN = VREF 150 25 20 15 10 V+ = 60V V+ = 35V V+ = 10V 5 Supply Current, Idle Mode V+ = 60V 200 V+ = 60V V+ = 35V V+ = 10V V+ = 35V V+ = 10V 100 DC PIN = V– 50 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 6801 G05 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 6801 G06 UV Detection Level Error 1.0 V+ = 43.2V 1.0 0.8 UV = 2.108V 0.6 0.4 ERROR (%) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 6801 G07 0V Detection Level Error V+ = 43.2V 800 0.8 OV = 4.120V Supply Current V+ = 43.2V 780 CONTINUOUS MEAS MODE 5 TYPICAL UNITS ERROR (%) 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 5 TYPICAL UNITS ISUPPLY (μA) 760 740 720 700 680 660 640 620 600 1 85°C 25°C –40°C –1.0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 6801 G08 10 fENA (kHz) 100 6801 G09 6801p 5 LTC6801 TYPICAL PERFORMANCE CHARACTERISTICS UV/OV Detection Level Error 4.0 ERROR RELATIVE TO RS = 0 (%) MEASUREMENT CYCLE TIME (ms) RS IN SERIES WITH Cn AND Cn-1 – 3.5 10nF FROM Cn, Cn-1 TO V 85°C 3.0 2.5 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10 EXTERNAL SERIES RESISTANCE, RS (kΩ) 6801 G10 Measurement Cycle Time 17.0 16.5 C PIN BIAS CURRENT (μA) 16.0 V+ = 10V 15.5 V+ = 60V 15.0 14.5 14.0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 6801 G11 Cell Input Bias Current when Measuring 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 6801 G12 CONTINUOUS MEAS MODE CC1 = CC0 = VREG CELL INPUT = 3.6V 25°C –40°C Cell Input Bias Current, Idle Mode 50 40 C PIN BIAS CURRENT (nA) 30 20 C12 10 0 C2 TO C11 VTEMP1, VTEMP2 –2 –10 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 6801 G13 Cell Voltage Measurement Hysteresis 12 SOUT CLOCK FREQUENCY (kHz) UV THRESHOLD = 2.108V OV THRESHOLD = 4.120V 10 HYST = V REG 8 VREF (V) 6 4 2 0 OVERVOLTAGE DETECTED 0 1 2 3 CELL VOLTAGE (V) 4 5 6801 G14 VREF Line Regulation 3.070 NO LOAD CELL INPUT = 3.6V 3.065 25°C 3.060 –40°C UNDERVOLTAGE DETECTED C1 85°C 3.055 3.050 10 20 30 V+ (V) 40 50 60 6801 G15 VREF Load Regulation 3.070 VREF Output Voltage 3.070 NO LOAD 5.5 VREG Line Regulation IDLE MODE 5.4 NO LOAD 3.065 VREF (V) VREF (V) 3.065 5 TYPICAL UNITS VREG (V) 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 85°C 25°C –40°C 3.060 –40°C 3.055 25°C 85°C 3.050 0 50 100 150 200 ILOAD (μA) 250 300 6801 G20 3.060 3.055 3.050 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 6801 G16 4.5 10 20 30 V+ (V) 40 50 60 6801 G17 6801p 6 LTC6801 TYPICAL PERFORMANCE CHARACTERISTICS VREG Line Regulation 5.5 IDLE MODE 5.4 4mA LOAD TO V– 5.3 5.2 VREG (V) VREG (V) 5.1 5.0 4.9 4.8 4.7 4.6 4.5 10 20 30 V+ (V) 6801 G18 VREG Load Regulation 5.5 IDLE MODE 5.5 5.4 5.3 5.0 VREG (V) 5.2 5.1 5.0 4.9 4.8 4.7 4.6 4 6 ILOAD (mA) 8 10 6801 G19 VREG Output Voltage IDLE MODE NO LOAD 85°C 4mA LOAD 4.5 25°C –40°C 4.0 40 50 60 0 85°C 25°C –40°C V+ = 60V V+ = 10V 2 4.5 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 6801 G21 V+ = 60V V+ = 35V V+ = 10V Status Output Operating at 10kHz 100k LOAD TO V– 16 14 SOUT 2V/DIV SOUT 12 NUMBER OF UNITS 10 8 6 4 20μs/DIV 6801 G22 UV/OV Detection Level Thermal Hysteresis TA = 85°C TO 25°C 20 18 16 NUMBER OF UNITS –50 0 50 100 150 CHANGE IN DETECTION LEVEL (ppm) 200 14 12 10 8 6 4 2 UV/OV Detection Level Thermal Hysteresis TA = –40°C TO 25°C 2 0 –100 0 –100 –50 0 50 100 150 CHANGE IN DETECTION LEVEL (ppm) 200 6801 G23 6801 G24 6801p 7 LTC6801 PIN FUNCTIONS V+ (Pin 1): Tied to the most positive potential in the battery stack. For example, the same potential as C12 when measuring a stack of 12 cells, or the same potential as C7 when measuring a stack of 7 cells. C12, C11, … C1 (Pin 2 to Pin 13): Cell Voltage Inputs. Up to 12 cells can be monitored. The lowest potential is tied to V–. The next lowest potential is tied to C1 and so forth. Due to internal overvoltage protection, each C input must be tied to a potential equal to or greater than the next lower numbered C input. See the figures in the Applications Information section for more details on connecting batteries to the LTC6801. See Electrical Characteristics table for voltage range and input bias current requirements. V– (Pin 14): Tied to the most negative cell potential (bottom of monitored cell stack). VTEMP1, VTEMP2 (Pin 15, Pin 16): Temperature Sensor Inputs. The ADC will measure the voltages on VTEMP1 and VTEMP2 relative to V–. The ADC measurements are referenced to the VREF pin voltage. Therefore a simple thermistor and resistor combination connected to the VREF pin can be used to monitor temperature. These pins have a fixed undervoltage threshold equal to one half VREF. A filtering capacitor to V– is recommended. Temperature sensor input pins may be tied to VREF to disable. VREF (Pin 17): Reference Output, Nominally 3.072V. Requires a 1μF bypass capacitor to V–. The VREF pin can drive a 100k resistive load connected to V–. VREF must be buffered with an LT6003 amplifier, or similar device to drive heavier loads. VREF becomes high impedance when the IC is disabled or idle between monitoring events. VREG (Pin 18): Regulator Output, Nominally 5V. Requires a 1μF bypass capacitor to V–. The VREG pin is capable of supplying up to 4mA to an external load and is continually enabled. EIN, EIN (Pin 19, Pin 20): Differential Enable Input. A clock signal greater than 2kHz will enable the LTC6801. For operation with a single-ended enable signal (up to 10kHz), drive EIN and connect a 1nF capacitor from EIN to V–. SOUT, SOUT (Pin 21, Pin 22): Differential Status Output. Swings V– to VREG. This output will toggle at the same frequency as EIN/EIN when a valid signal is detected at SIN/SIN and the battery stack being monitored is within specified parameters, otherwise SOUT is low and SOUT high. SIN, SIN (Pin 23, Pin 24): Differential status input from the IC above. To indicate that the stack is good, SIN must be the same frequency and phase as EIN. See applications circuits for interfacing SIN to the SOUT above. EOUT, EOUT (Pin 25, Pin 26): A Buffered Version of EIN/EIN. Swings V– to VREG. Must be capacitively coupled to the EIN/EIN inputs of the next higher voltage LTC6801 in a stack, or looped to SIN/SIN of the same chip (pins 23, 24). DC (Pin 27): Duty Cycle Three-Level Input. This pin may be tied to VREG, VREF or V–. The DC pin selects the duty cycle of the monitoring function and has an internal pullup to VREG. See Table 3. SLTOK (Pin 28): Self Test Logic Output. SLTOK is held HIGH (VREG voltage) upon reset or successful completion of a self test cycle. A LOW output level (V– voltage) indicates the last self test cycle failed. SLT (Pin 29): Self Test Open Collector Input/Output. SLT initiates a self test cycle when it is pulled low externally. When a high to low transition is detected, the next scheduled measurement cycle will be a self test cycle. SLT indicates a self test cycle is in progress when pulled low internally. A self test is automatically initiated after 1024 measurement cycles. This pin has an internal pull-up to VREG. CC0, CC1 (Pin 30, Pin 31): Cell Count Three-Level Inputs. These pins may be tied to VREG, VREF or V–. CC1 and CC0 select the number of cells attached to the device and each pin has an internal pull-up to VREG. See Table 5. HYST (Pin 32): Hysteresis Three-Level Input. This pin may be tied to VREG, VREF or V–. HYST selects the amount of hysteresis applied to the undervoltage and overvoltage threshold settings and has an internal pull-down to V–. See Table 4. 6801p 8 LTC6801 PIN FUNCTIONS UV0, UV1 (Pin 33, Pin 34): Undervoltage Three-Level Inputs. These pins may be tied to VREG, VREF or V–. UV1 and UV0 select the undervoltage threshold and each pin has an internal pull-up to VREG. See Table 2. OV0, OV1 (Pin 35, Pin 36): Overvoltage Three-Level Inputs. These pins may be tied to VREG, VREF or V–. OV1 and OV0 select the overvoltage threshold and each pin has an internal pull-down to V–. See Table 1. Table 1. Overvoltage Inputs OV1 VREG VREG VREG VREF VREF VREF V– V– V– OV0 VREG VREF V– VREG VREF V– VREG VREF V– OVERVOLTAGE THRESHOLD (V) 4.503 4.407 4.311 4.216 4.120 4.024 3.928 3.832 3.737 Table 3. Duty Cycle Select DC VREG VREF V– NOMINAL CYCLE TIME* 15ms Approximately 130ms Approximately 500ms *Cycle time based on LTC6801 measuring 12 cells and 2 temperatures. Table 4. Hysteresis Select HYST VREG VREF V– UV HYSTERESIS* 500mV 250mV 0mV OV HYSTERESIS 200mV 100mV 0mV *UV hysteresis is disabled when the undervoltage threshold is set to 0.766V. Table 5. Cell Count Select CC1 VREG VREG VREG VREF VREF CC0 VREG VREF V– VREG VREF V– VREG VREF V– CELL COUNT 12 11 10 9 8 7 6 5 4 Table 2. Undervoltage Inputs UV1 VREG VREG VREG VREF VREF VREF V– V– V– UV0 VREG VREF V– VREG VREF V– VREG VREF V– UNDERVOLTAGE THRESHOLD (V) 2.874 2.683 2.491 2.299 2.108 1.916 1.725 1.533 0.766 VREF V– V– V– 6801p 9 LTC6801 BLOCK DIAGRAM The LTC6801 measures between 4 and 12 cell voltages and 2 temperature inputs. If all measurements are within an acceptable window, the LTC6801 will produce a differential V+ C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 V– DECODER “GOOD” SELF TEST REFERENCE (REF2) MUX REFERENCE ADC 12 HYST CC1 clock output signal (SOUT, SOUT). If any of the channels exceed user set upper and lower thresholds, a logic low signal is produced at SOUT. VREG REGULATOR + – DIGITAL COMPARATORS UV/OV FLAGS AND CONTROL LOGIC CC0 DC SLT SLTOK – + + – EIN EIN EOUT EOUT SIN SIN SOUT SOUT + – VTEMP1 VTEMP2 VREF OV0 OV1 UV0 UV1 6801 BD 6801p 10 LTC6801 BLOCK DIAGRAM OF ENABLE IN/OUT AND STATUS IN/OUT EOUT EOUT VREG 300k SIN THE FREQUENCY MATCH DETECT OUTPUT GOES HIGH WHEN SIN AND EIN ARE THE SAME FREQUENCY FREQUENCY MATCH DETECT + – VREG 300k 300k SIN 300k THE SIGNAL IS HIGH WHEN ALL READINGS ARE “GOOD” VREG 300k SOUT SOUT SOUT IS ACTIVE WHEN 1) EIN IS ACTIVE 2) SIN AND EIN ARE THE SAME FREQUENCY 3) ALL READINGS ARE “GOOD” EIN + THE CLK DETECT OUTPUT GOES HIGH WHEN EIN IS 2kHz TO 50kHz CLK DETECT – VREG 300k 300k EIN 300k 6801 BDa 6801p 11 LTC6801 APPLICATIONS INFORMATION OVERVIEW The LTC6801 is designed as an easy to implement, lowcost battery stack monitor that provides a simple indication of correct battery stack operation without requiring a microcontroller interface. For battery stack monitoring with cell voltage read back and discharge circuitry, refer to the LTC6802 battery stack monitor data sheet. The LTC6801 contains a 12-bit ADC, a precision voltage reference, sampled comparator, high voltage multiplexer and timer/sequencer. During normal operation, the sequencer multiplexes the ADC inputs between each of the channel input pins in turn, performing a single comparison to the undervoltage and overvoltage thresholds. The VTEMP inputs are also monitored for an undervoltage at a fixed threshold of VREF /2. The presence of a status output clock indicates the system is “OK”. Becase the status output is dynamic, it cannot get stuck in the “OK” state. STACKED OPERATION Each LTC6801 monitors a group of up to 12 series connected cells. Groups of cells can be connected in series or parallel to form a large battery pack. The LTC6801s can be daisychained with simple capacitive or transformer coupling. This allows every cell in a large battery pack to be monitored with a single signal. Figure 2 illustrates monitoring of 36 series connected cells. To cancel systematic duty cycle distortion through the clock buffers, it is recommended that the clock lines are cross-coupled (EOUT goes to EIN etc.) as they route up and down the stack as shown in Figure 2. INDEPENDENT OPERATION Figure 3 shows how three groups of 12 cells can be monitored independently. REGULATED OUTPUTS A regulated voltage is provided at the VREG pin, biased from the battery stack. The VREG pin can supply up to 4mA at 5V and may be used to power small external circuits. The regulated output remains at 5V continually, as long as the total stack voltage is between 10V and 50V. A low current, precision reference voltage is provided at the VREF pin, which can drive loads of greater than 100k. The VREF output is high impedance when the LTC6801 is idle. Both the VREG and VREF pins must be bypassed to V– with a 1μF capacitor. CONTROL INPUTS The LTC6801 thresholds are controlled by the UV1, UV0, OV1 and OV0 pins. These pins are designed to be tied directly to VREG, VREF or V– in order to set the comparison thresholds for all channels simultaneously. The pins are not designed to be variable. In particular, changes made to the pins while the chip is not in idle mode may result in unpredictable behavior. See Tables 1 and 2 for setting and threshold information. 6801p 12 LTC6801 APPLICATIONS INFORMATION ENABLE INPUTS In order to support stacked operation, the LTC6801 is enabled through a differential signal chain encompassing the EIN/EIN, EOUT/EOUT, and SIN/SIN pins. The LTC6801 will be enabled if a differential square wave with a frequency between 2kHz and 50kHz is applied at EIN/EIN. Otherwise, the LTC6801 will default to a low power idle mode. If the differential signal at SIN/SIN is not equal in frequency to the differential signal output at EOUT/EOUT, the LTC6801 will be enabled but SOUT will be held at 0V and SOUT will be held at VREG. For the simplest operation in a single chip configuration, EOUT should be connected directly to SIN and EOUT should be connected directly to SIN, and a square wave with a frequency between 2kHz and 50kHz should be applied differentially to EIN and EIN. For enable clock frequencies up to 10kHz, a single-ended square wave with a 5V swing may be used at EIN while a 1nF capacitor is connected from EIN to V–. STATUS OUTPUT If the chip is properly enabled (EIN/EIN, SIN/SIN are the same frequency), all cells are within the undervoltage and overvoltage thresholds, and the voltage at VTEMP1 and VTEMP2 is over one half VREF, the differential output at SOUT/SOUT will toggle at the same frequency and in phase with the signal at EIN/EIN. Otherwise, SOUT will be low and SOUT will be high. The maximum delay between when a bad cell voltage occurs and when it is detected depends on the measurement duty cycle setting. The SOUT clock turns on or off at the end of each measurement cycle. Figure 4 shows the maximum detection delay in continuous monitor mode (DC pin tied to VREG). FAULT PROTECTION Overview Care should always be taken when using high energy sources such as batteries. There are countless ways that systems can be [mis-]configured during the assembly and service procedures that can impact a battery’s long term performance. Table 6 shows various situations to consider when planning protection circuitry. Battery Interconnection Integrity Please note: The last condition shown in the FMEA table could cause catastrophic IC failures. In this case, the battery string integrity is lost within a cell group monitored by an LTC6801. This condition could place excessive stress on certain cell input signal clamp-diodes and probably lead to IC failure. If this scenario seems at all likely in a particular application, Schottky diodes should be added in parallel with the cells as shown in Figure 5 to form a redundant load current path and a means of limiting stress on the IC inputs. The diodes used in this situation need current ratings sufficient to open a protective fuse in the battery tap signal (otherwise they would have to carry the normal range of cell currents). 6801p 13 LTC6801 APPLICATIONS INFORMATION TOP OF STACK V+ C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 V– VTEMP1 VTEMP2 VREF VREG LTC6801 OV1 TOP OF STACK V+ C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 V– VTEMP1 VTEMP2 VREF VREG LTC6801 OV1 OV0 UV1 UV0 HYST CC1 CC0 SLT SLTOK DC EOUT EOUT SIN SIN SOUT SOUT EIN EIN OV0 UV1 UV0 HYST CC1 CC0 SLT SLTOK DC EOUT EOUT SIN SIN SOUT SOUT EIN EIN PROGRAMMED CONDITIONS: CONTINUOUS MONITOR MODE OV = 4.120V UV = 2.108V HYST = 250mV (UV), 100mV (OV) CC = 12 V+ C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 V– LTC6801 OV1 V+ C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 V– LTC6801 OV1 OV0 UV1 UV0 HYST CC1 CC0 SLT SLTOK DC EOUT EOUT SIN SIN SOUT SOUT EIN EIN OV0 UV1 UV0 HYST CC1 CC0 SLT SLTOK DC EOUT EOUT SIN SIN SOUT SOUT EIN EIN VTEMP1 VTEMP2 VREF VREG VTEMP1 VTEMP2 VREF VREG V+ C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 V– LTC6801 OV1 V+ C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 V– LTC6801 OV1 OV0 UV1 UV0 HYST CC1 CC0 SLT SLTOK DC EOUT EOUT SIN SIN SOUT SOUT EIN EIN CLOCK OUT WHEN ALL CELLS GOOD USER SUPPLIED CLOCK IN OV0 UV1 UV0 HYST CC1 CC0 SLT SLTOK DC EOUT EOUT SIN SIN SOUT SOUT EIN EIN VTEMP1 VTEMP2 VREF VREG ALL CLOCKS OUT WHEN ALL CELLS GOOD VTEMP1 VTEMP2 VREF VREG USER SUPPLIED CLOCK IN 6801 F02 6801 F03 BOTTOM OF STACK BOTTOM OF STACK Figure 2. Serial Connection of Status Lines for Multiple 6801s on the Same PCB (Simplified Schematic, Not All Components Shown) Figure 3. Independent Status Lines for Multiple 6801s on the Same PCB (Simplified Schematic, Not All Components Shown) 6801p 14 COMPLETE MEASUREMENT CYCLE 15.4 ms (~1.1ms PER CELL) C5 C6 C7 C8 C9 C10 C11 C12 T1 T2 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 T1 SOUT STATUS UPDATED SOUT STATUS UPDATED C1 C2 C3 C4 T2 C1 C2 C3 APPLICATIONS INFORMATION SOUT EXAMPLES SOUT REMAINS ACTIVE (SINCE NOTHING ABNORMAL HAS BEEN DETECTED YET) LTC6801 READS A BAD VOLTAGE ON CELL 1 ALL CELLS GOOD WORST CASE ERROR DETECTION DELAY ~29.7ms SOUT STOPS AT END OF MEASUREMENT CYCLE 6801 F04 CELL 1 GOES BAD IMMEDIATELY AFTER IT IS READ NOTE: SOUT IS NOT TO SCALE SEE ELECTRICAL TABLE FOR MIN/MAX SPECIFICATIONS Figure 4. Cell UV/OV Detection Delay in Continuous Monitor Mode LTC6801 15 6801p LTC6801 APPLICATIONS INFORMATION Table 6. Failure Mechanism Effect Analysis (FMEA) SCENARIO Cell input open-circuit (random) Cell input open-circuit (random) Top cell input connection loss (V+) EFFECT Power-up sequence at IC inputs Differential input voltage overstress Power will come from highest connected cell input DESIGN MITIGATION Clamp diodes at each pin to V+ & V– (within IC) provide alternate PowerPath. Zener diodes across each cell voltage input pair (within IC) limit stress. Clamp diodes at each pin to V+ and V– (within IC) provide alternate PowerPath. Error condition will be indicated by all upstream and downstream units (no clock on SOUT/ SOUT). Bottom cell input connection loss (V–) Power will come from lowest connected cell input Clamp diodes at each pin to V+ and V– (within IC) provide alternate PowerPath. Error condition will be indicated by all upstream and downstream units (no clock on SOUT/ SOUT). Loss of supply connections Clamp diodes at each pin to V+ and V– (within IC) provide alternate PowerPath. Error condition will be indicated by all upstream and downstream units (no clock on SOUT/ SOUT). Daisy chain will be broken and error condition will be indicated by all upstream and downstream units (no clock on SOUT/ SOUT). Power input disconnection (amongst stacked units) Status link disconnection (between stacked units) Short between any two configuration inputs Break of “daisy chain” communication (no stress to ICs) Power supplies connected to pins will be shorted If VREF or VREG is shorted to V–, supply will be removed from internal circuitry and error condition will be indicated by all upstream and downstream units (no clock on SOUT/ SOUT). If VREF is shorted to VREG, a self test error will be flagged. Control input will be pulled towards positive or negative potential depending on pin Control input will be pulled to a more stringent condition (larger number of channels, higher UV threshold, lower OV threshold, shorter duty cycle, etc. ensuring either more stringent monitoring or error condition will be indicated by all upstream and downstream units (no clock on SOUT/ SOUT). Full stack potential may appear across status/ enable isolation devices, but will not be seen by the IC. isolation capacitors should therefore be rated to withstand the full stack potential. Add parallel schottky diodes across each cell for current path redundancy. Diode and connections must handle full operating current of stack, will limit stress on IC Open connection on configuration input Cell-pack integrity, break between stacked units Daisy-chain voltage reversal up to full stack potential Cell-pack integrity, break within stacked unit Cell input reverse overstress 6801p 16 LTC6801 APPLICATIONS INFORMATION V+ PROTECT AGAINST BREAKS HERE 6801 F05 LTC6801 C12 EOUT C11 EOUT SIN C10 ZCLAMP SIN SOUT Figure 5. Using Diodes to Form a Redundant Load Path (One Cell Connection Shown) Internal Protection Structure The LTC6801 incorporates a number of protective structures, including parasitic diodes, Zener-like overvoltage suppressors, and other internal features that provide protection against ESD and certain overstress conditions that could arise in practice. Figure 6 shows a simplified internal schematic that indicates the significant protective structures and their connectivity. The various diodes indicate the approximate current versus voltage characteristics that are intrinsic to the part, which is useful in analyzing responses to certain external stresses, such as during a hot-start scenario. SELF TEST CIRCUITRY The LTC6801 has internal circuitry that performs a periodic self test of all measurement functions. The LTC6801 self test circuitry is intended to prevent undetectable failure modes. Accuracy and functionality of the voltage reference and comparator are verified, as well as functionality of the high voltage multiplexer and ADC decimation filter. Additionally, open connections on the cell input pins C1 to C11 are detected (Open connections on V– or C12/V+ will cause an undervoltage failure during the normal measurement cycle). C9 SOUT EIN C8 EIN C7 VTEMP1 VTEMP2 C6 ZCLAMP VREF VREG C5 OV1 OV0 C4 UV1 UV0 C3 HYST C2 CC1 ZCLAMP CC0 C1 SLT SLTOK V– DC 6801 F06 Figure 6. Internal Protection Structures 6801p 17 LTC6801 APPLICATIONS INFORMATION Self Test Pins The SLT pin is used to initiate a self test. It is configured as an open collector input/output. The pin should be normally tied to VREG with a resistor greater than or equal to 100k or floated. The pin may be pulled low at any time to initiate a self test cycle. The device will automatically initiate a self test if SLT has not been externally activated for 1024 measurement cycles, and pull down the SLT pin internally to indicate that it is in self test mode. The SLTOK pin is a simple logic output. If the previous self test failed the output is held low, otherwise the output will be high. The SLTOK pin is high upon power-up. The SLTOK output can be connected to a microcontroller through an isolation path. The LTC6801 status output will remain active while the SLTOK pin is low. The LTC6801 will continue to monitor cells if the self test fails. If the next self test passes, the SLTOK output returns high. Reference and Comparator Verification A secondary internal bandgap voltage reference (REF2) is included in the LTC6801 to aid in verification of the reference and comparator. During the self test cycle, the comparator and main reference are used to measure the REF2 voltage. To verify the comparator functionality, the upper and lower thresholds are first set in a close window around the expected REF2 voltage and the comparator output is verified. Then the upper threshold is set below the REF2 voltage and the comparator output is verified again. Lastly, the lower threshold is set above the REF2 voltage and the comparator output is verified a third time. The self test guarantees that VREF is within 5% of the specified nominal value. Also, this test guarantees the analog portion of the ADC is working. High Voltage Multiplexer Verification The most dangerous failure mode of the high voltage multiplexer would be a stuck bit condition in the address decoder. Such a fault would cause some channels to be measured repeatedly while other channels are skipped. A skipped channel could mean a bad cell reading is not detectable. Other multiplexer failures, like the simultaneous selection of multiple channels, or shorts in the signal path, would result in an undervoltage or overvoltage condition on at least one of the channels. The LTC6801 incorporates circuitry to ensure that all requested channels are measured during each measurement cycle and none are skipped. If a channel is skipped, an error is flagged during the self test cycle. ADC Decimation Filter Verification The ADC decimation filter test verifies that the digital circuits in the ADC are working, i.e. there are no stuck bits in the ADC output register. During each self test cycle, the LTC6801 feeds two test waveforms into the ADC. The internally generated waveforms were designed to generate complementary zebra patterns (alternating 0’s and 1’s) at the ADC output. If either of the waveforms generates an incorrect output value, an error is flagged during the self test cycle. Open Cell Connection Detection The open connection detection algorithm ensures that an open circuit is not misinterpreted as a valid cell reading. 6801p 18 LTC6801 APPLICATIONS INFORMATION In the absence of external noise filtering, the input resistance of the ADC will cause open wires to produce a near zero reading. This reading will cause an undervoltage failure during the normal measurement cycle. Some applications may include external noise filtering to improve the quality of the voltage comparisons. When an RC network is used to filter noise, an open wire may not produce a zero reading because the comparator input resistance is too large to discharge the capacitors on the input pin. Charge may build up on the open pin during successive measurement cycles to the extent that it could indicate a valid cell voltage reading. During each self test cycle, the LTC6801 will sink 100μA to V– from each side of the cell being measured. The undervoltage threshold is not checked during the self test because the 100μA pull-down current would cause false failures in some cases. If an input is open, this current will discharge any filtering capacitors and cause the input to float down to approximately 0.7V below the next lower cell input. In most cases, the cell voltage of the cell above the open input will exceed the overvoltage threshold and flag a self test error. During the normal measurement cycle, the LTC6801 will sink 1μA to V– from each side of the cell being measured. If the cell voltages are low enough that an open wire is not detected as an overvoltage during CSBI CSBO SDO SDOI SDI SCKO + SCKI V VMODE C12 GPIO2 S12 GPIO1 C11 WDTB S11 MMB C10 LTC6802-1 TOS S10 C9 VREG S9 VREF VTEMP2 C8 S8 VTEMP1 C7 NC V– S7 C6 S1 S6 C1 S2 C5 S5 C2 C4 S3 C3 S4 self test, this current will cause the cell input to settle to a voltage low enough to trigger an undervoltage condition during the normal measurement cycle. Note, an open cell connection may not be detected when the UV = 0.766V setting is used. For all other UV settings, an open cell connection will result in either a self test error or no SOUT clock. Using The LTC6801 with Other Battery Monitors When used in combination with an LTC6802-1, it is possible to check the LTC6801 self test result via the LTC6802-1 and its isolated SPI. As shown in Figure 7, the SLTOK output is tied to the GPIO2 pin on the LTC6802-1. SLTOK will remain high as long as it is passing the self test. A self test will occur automatically every 1024 measurement cycles (17 seconds to 9 minutes, depending on measurement duty cycle). A self test can be initiated by a falling edge on SLT, via the LTC6802-1 GPIO1 line. A self test will start after the current measurement cycle is complete, and the SLTOK status will be valid when the self test completes. The worst case delay before SLTOK is valid in continuous monitor mode is approximately 15ms for the current cycle to complete plus 17ms for the self test to complete. The 6802-1 can measure the LTC6801 reference, which will independently test the analog circuitry of the LTC6802. C12 C11 C10 C9 C8 C7 C6 C5 C4 IN OUT 1M CMPD6263 1μF C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VREF 1μF OV1 V+ OV0 C12 UV1 C11 UV0 C10 HYST C9 CC1 C8 LTC6801 CC0 C7 SLT C6 SLTOK C5 DC C4 EOUT C3 EOUT C2 SIN C1 SIN V– SOUT VTEMP1 SOUT VTEMP2 EIN VREF EIN VREG 6801 F07 C3 C2 C1 Figure 7. Interconnection of an LTC6802-1 and LTC6801 for Self Test. 6801p 19 LTC6801 APPLICATIONS INFORMATION CELL-VOLTAGE FILTERING The LTC6801 employs a sampling system to perform its analog-to-digital conversions and provides a conversion result that is essentially an average over the 0.5ms conversion window. If there is significant noise at frequencies near 500kHz there may be aliasing in the delta-sigma modulator. A lowpass filter with 30dB attenuation at 500kHz may be beneficial. Since the delta-sigma integration bandwidth is about 1kHz, the filter corner need not be lower than this to assure accurate conversions. Series resistors of 1k may be inserted in the input paths without introducing measurement error. Shunt capacitors may be added from the cell inputs to V–, creating RC filtering as shown in Figure 8. The combination of 1k and 10nF is recommended as a robust, cost effective noise filter. MEASURING VARIOUS CELL COUNTS The LTC6801 is designed to measure up to 12 cells depending on the state of the CC pins (See Table 5). When using an LTC6801 configured for measuring less than 12 cells, for instance choosing to measure 8 cells by Figure 9. Driving Thermistors Directly from VREF. Two Independent Probes With a +60°C Trip Point OV1 V+ OV0 C12 UV1 C11 UV0 C10 HYST C9 CC1 C8 LTC6801 CC0 C7 SLT C6 SLTOK C5 DC C4 EOUT C3 EOUT C2 SIN C1 – SIN V SOUT VTEMP1 SOUT VTEMP2 EIN VREF EIN VREG 6801 F10 tying both CC1 and CC0 to the VREF pin, the highest cell potential (in this case C8) must be connected to the V+ pin for proper operation. Unused cell connection pins (in this case C9 to C12) may be left floating or may also be tied to the highest cell potential. OV1 V+ OV0 C12 UV1 C11 UV0 C10 HYST C9 CC1 C8 LTC6801 CC0 C7 SLT C6 SLTOK C5 DC C4 EOUT C3 EOUT C2 SIN C1 SIN V– SOUT VTEMP1 SOUT VTEMP2 EIN VREF EIN VREG 6801 F09 500k NTC B = 4567 500k NTC B = 4567 1μF 1μF 100k 100k 1k C3 1k 10nF C2 10k NTC B = 3380 10k NTC B = 3380 0.5μF 0.5μF 1k 10nF C1 2.2k 2.2k 10nF 6801 F08 Figure 10. Buffering VREF for Higher-Current Sensors. Two Independent Probes With a +70°C Trip Point 20 – 6801p Figure 8. Adding RC Filtering to the Cell inputs LT6003 + V– LTC6801 APPLICATIONS INFORMATION READING EXTERNAL TEMPERATURE PROBES The LTC6801 includes two channels of ADC input, VTEMP1 and VTEMP2, that are intended to monitor thermistors (tempco about –4%/°C generally) or diodes (–2.2mV/°C typical) located within the cell array. Sensors can be powered directly from VREF as shown in Figure 9 (up to 30μA typical). The temperature measurement inputs (VTEMP1, VTEMP2) of the LTC6801 are comparator input channels with a voltage threshold of one-half VREF. Input voltages above half VREF are considered good. Voltages below the one-half VREF threshold are considered a fault condition. The inputs may be used in combination with resistors, thermistors, or diodes to sense both an upper and lower temperature limit. Figure 9, Figure 10 and Figure 11 illustrate some possibilities. To ignore these inputs simply connect VTEMP1 and VTEMP2 to VREF. A filtering capacitor to V– is recommended to minimize the error caused by the approximately 700k input impedance of the ADC. For sensors that require higher drive currents, a buffer amplifier may be used as shown in Figure 10. Power for the sensor is actually sourced indirectly from the VREG pin in this case. Probe loads up to about 1mA maximum are supported in this configuration. Since VREF is shut down while the LTC6801 is idle between measurement cycles, the thermistor drive is also shut off and thus power dissipation is minimized. Since VREG remains always-on, the buffer op amp (LT6003 shown) is selected for its ultralow current consumption (10μA). OV1 V+ OV0 C12 UV1 C11 UV0 C10 HYST C9 CC1 C8 LTC6801 CC0 C7 SLT C6 SLTOK C5 DC C4 EOUT C3 EOUT C2 SIN C1 SIN V– SOUT VTEMP1 SOUT VTEMP2 EIN VREF EIN VREG 6801 F11 500k NTC B = 4567 1μF 1150k 1μF 100k 100k NTC B = 4250 Figure 11. Sensing Both Upper and Lower Temperature Thresholds. This Example Monitors a –20°C to +60°C Window Detector. The Thermistors Should Be in Close Proximity For circuits that include filtering capacitance, note that only the fastest DC setting (VREG connection) will keep VREF steady and allow the VTEMP voltages to settle. To use the lower power DC settings, VREF must be buffered (see Figure 10), so that a low impedance is presented to the ADC, with a time constant of no more than about 1ms. ADVANTAGES OF DELTA-SIGMA ADCs The LTC6801 employs a delta-sigma analog to digital converter for voltage measurement. The architecture of delta-sigma converters can vary considerably, but the common characteristic is that the input is sampled many times over the course of a conversion and then filtered or averaged to produce the digital output code. 6801p 21 LTC6801 APPLICATIONS INFORMATION For a given sample rate, a delta-sigma converter can achieve excellent noise rejection while settling completely in a single conversion. This is particularly important for noisy automotive systems. Other advantages of delta-sigma converters are that they are inherently monotonic, meaning they have no missing codes, and they have excellent DC specifications. The LTC6801’s ADC has a second order delta-sigma modulator followed by a SINC2, finite impulse response (FIR) digital filter, with a lowpass bandwidth of 1kHz. The front-end sample rate is 512ksps, which greatly reduces input filtering requirements. A simple 16kHz, 1 pole filter composed of a 1k resistor and a 10nF capacitor at each input will provide adequate filtering for most applications. These component values will not degrade the DC accuracy of the ADC. Each conversion consists of two phases – an autozero phase and a measurement phase. The ADC is autozeroed at each conversion, greatly improving CMRR. USING TRANSFORMERS FOR GALVANIC ISOLATION As shown in Figure 12, small gate-drive signal transformers can be used to interconnect devices and transport the enable and sense signals safely across an isolation barrier. Driving a transformer with a squarewave requires transient currents of several mA and frequency of operation at 20kHz or higher. Since the output pins of the LTC6801 are current limited at