LTC6803-1/LTC6803-3 Multicell Battery Stack Monitor FEATURES
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DESCRIPTION
The LTC®6803 is a 2nd generation, complete battery monitoring IC that includes a 12-bit ADC, a precision voltage reference, a high voltage input multiplexer and a serial interface. Each LTC6803 can measure up to 12 series-connected battery cells or supercapacitors. Using a unique level shifting serial interface, multiple LTC6803-1/ LTC6803-3 devices can be connected in series, without opto-couplers or isolators, allowing for monitoring of every cell in a long string of series-connected batteries. Each cell input has an associated MOSFET switch for discharging overcharged cells. The LTC6803-1 connects the bottom of the stack to V– internally. It is pin compatible with the LTC6802-1, providing a drop-in upgrade. The LTC6803-3 separates the bottom of the stack from V–, improving cell 1 measurement accuracy. The LTC6803 provides a standby mode to reduce supply current to 12µA. Furthermore, the LTC6803 can be powered from an isolated supply, providing a technique to reduce battery stack current draw to zero. For applications requiring individually addressable serial communications, see the LTC6803-2/LTC6803-4.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
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Measures Up to 12 Battery Cells in Series Stackable Architecture Supports Multiple Battery Chemistries and Supercapacitors Serial Interface Daisy Chains to Adjacent Devices 0.25% Maximum Total Measurement Error Engineered for ISO26262 Compliant Systems 13ms to Measure All Cells in a System Passive Cell Balancing: – Integrated Cell Balancing MOSFETs – Ability to Drive External Balancing MOSFETs Onboard Temperature Sensor and Thermistor Inputs 1MHz Serial Interface with Packet Error Checking Safe with Random Connection of Cells Built-In Self Tests Delta-Sigma Converter With Built-In Noise Filter Open-Wire Connection Fault Detection 12µA Standby Mode Supply Current High EMI Immunity 44-Lead SSOP Package
APPLICATIONS
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Electric and Hybrid Electric Vehicles High Power Portable Equipment Backup Battery Systems Electric Bicycles, Motorcycles, Scooters
TYPICAL APPLICATION
NEXT 12-CELL PACK ABOVE V+ LTC6803-3 DIE TEMP REGISTERS AND CONTROL SERIAL DATA TO LTC6803-3 ABOVE
Supply Current vs Modes of Operation
1mA 100µA SUPPLY CURRENT
+
MUX 12-CELL BATTERY
50V
+ +
12-BIT ∆Σ ADC VOLTAGE REFERENCE
ISOLATED DC/DC CONVERTER
12V
10µA 1µA 100nA 10nA 1nA
NEXT 12-CELL PACK BELOW
V– 100k NTC
EXTERNAL TEMP 100k
SERIAL DATA TO LTC6803-3 BELOW
HW SHUTDOWN
STANDBY
MEASURE
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LTC6803-1/LTC6803-3 ABSOLUTE MAXIMUM RATINGS (Note 1)
Total Supply Voltage (V+ to V–) ................................. 75V Input Voltage (Relative to V–) C0 ............................................................ –0.3V to 8V C12 ........................................................ –0.3V to 75V Cn (Note 5) ......................... –0.3V to Min (8 • n, 75V) Sn (Note 5) ......................... –0.3V to Min (8 • n, 75V) CSBO, SCKO, SDOI ............................... – 0.3V to 75V All Other Pins ........................................... –0.3V to 7V Voltage Between Inputs Cn to Cn – 1 ............................................. –0.3V to 8V Sn to Cn – 1 ............................................. –0.3V to 8V C12 to C8 ............................................... –0.3V to 25V C8 to C4 ................................................. –0.3V to 25V C4 to C0 ................................................. –0.3V to 25V Operating Temperature Range LTC6803I ............................................. –40°C to 85°C LTC6803H .......................................... –40°C to 125°C Specified Temperature Range LTC6803I ............................................. –40°C to 85°C LTC6803H .......................................... –40°C to 125°C Junction Temperature ........................................... 150°C Storage Temperature Range .................. –65°C to 150°C Note: n = 1 to 12
PIN CONFIGURATION
LTC6803-1 CSBO SDOI SCKO V+ C12 S12 C11 S11 C10 1 2 3 4 5 6 7 8 9 TOP VIEW 44 CSBI 43 SDO 42 SDI 41 SCKI 40 VMODE 39 GPIO2 38 GPIO1 37 WDTB 36 NC 35 TOS 34 VREG 33 VREF 32 VTEMP2 31 VTEMP1 30 NC 29 V– 28 S1 27 C1 26 S2 25 C2 24 S3 23 C3 LTC6803-3 CSBO SDOI SCKO V+ C12 S12 C11 S11 C10 1 2 3 4 5 6 7 8 9 TOP VIEW 44 CSBI 43 SDO 42 SDI 41 SCKI 40 VMODE 39 GPIO2 38 GPIO1 37 WDTB 36 TOS 35 VREG 34 VREF 33 VTEMP2 32 VTEMP1 31 NC 30 V– 29 C0 28 S1 27 C1 26 S2 25 C2 24 S3 23 C3
S10 10 C9 11 S9 12 C8 13 S8 14 C7 15 S7 16 C6 17 S6 18 C5 19 S5 20 C4 21 S4 22
S10 10 C9 11 S9 12 C8 13 S8 14 C7 15 S7 16 C6 17 S6 18 C5 19 S5 20 C4 21 S4 22
G PACKAGE 44-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 70°C/W
G PACKAGE 44-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 70°C/W
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LTC6803-1/LTC6803-3 ORDER INFORMATION
LEAD FREE FINISH LTC6803IG-1#PBF LTC6803IG-3#PBF LTC6803HG-1#PBF LTC6803HG-3#PBF TAPE AND REEL LTC6803IG-1#TRPBF LTC6803IG-3#TRPBF LTC6803HG-1#TRPBF LTC6803HG-3#TRPBF PART MARKING* LTC6803G-1 LTC6803G-3 LTC6803G-1 LTC6803G-3 PACKAGE DESCRIPTION 44-Lead Plastic SSOP 44-Lead Plastic SSOP 44-Lead Plastic SSOP 44-Lead Plastic SSOP SPECIFICED TEMPERATURE RANGE –40°C to 85°C –40°C to 85°C –40°C to 125°C –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
SYMBOL VS VLSB PARAMETER Supply Voltage, V+ Relative to V– Measurement Resolution ADC Offset ADC Gain Error VERR Total Measurement Error DC Specifications
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 43.2V, V– = 0V, unless otherwise noted.
CONDITIONS VERR Specification Met Timing Specification Met Quantization of the ADC (Note 2) (Note 2)
l l l l l
MIN 10 4
TYP
MAX 55 55
UNITS V V mV/Bit mV % % mV mV mV mV mV mV mV mV mV mV mV mV V V V V V °C
1.5 –0.5 –0.12 –0.22 ±2.5 0.5 0.12 0.22
(Note4) VCELL = –0.3V VCELL = 2.3V VCELL = 2.3V VCELL = 3.6V VCELL = 3.6V, LTC6803IG VCELL = 3.6V, LTC6803HG VCELL = 4.2V VCELL = 4.2V, LTC6803IG VCELL = 4.2V, LTC6803HG VCELL = 5V 2.3V < VTEMP < 4.2V, LTC6803IG 2.3V < VTEMP < 4.2V, LTC6803HG Full-Scale Voltage Range Range of Inputs Cn < 0.25% Gain Error, n = 2 to 11, LTC6803IG Range of Inputs C0, C1 < 0.25% Gain Error, LTC6803IG Range of Inputs Cn < 0.5% Gain Error, n = 2 to 11, LTC6803HG Range of Inputs C0, C1 < 0.5% Gain Error, LTC6803HG
l l l l l l l
–2.8 –5.1 –4.3 –7.9 –9 –5 –9.2 –10 –9.2 –10 –0.3 1.8 0 1.8 0
±3
2.8 5.1 4.3 7.9 9 5 9.2 10 9.2 10 5 5•n 5 5•n 5
VCELL VCM
Cell Voltage Range Common Mode Voltage Range Measured Relative to V–
l l l l
Die Temperature Measurement Error VREF Reference Pin Voltage Reference Voltage Temperature Coefficient
Error in Measurement of 125°C RLOAD = 100k to V–
l
5 3.020 3.015 3.065 3.065 8 100 60 3.110 3.115
V V ppm/°C ppm ppm/√kHr
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Reference Voltage Thermal Hysteresis 25°C to 85°C and 25°C to –40°C Reference Voltage Long-Term Drift
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LTC6803-1/LTC6803-3 ELECTRICAL CHARACTERISTICS
SYMBOL VREF2 VREG PARAMETER 2nd Reference Voltage
l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 43.2V, V– = 0V, unless otherwise noted.
CONDITIONS MIN 2.25 2.1 4.5 4.5 8 –10 10 TYP 2.5 2.5 5.0 5.0 MAX 2.75 2.9 5.5 UNITS V V V V mA µA nA µA µA µA µA µA µA µA µA mA mA mA µA Ω µA °C °C 15 13 4.1 1.4 ms ms ms ms ns ns ns ns ns ns ns 250 1 1 2.5 600 300 300 300 ns MHz Seconds ns ns ns ns
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Regulator Pin Voltage Regulator Pin Short-Circuit Limit
10V < V+ < 50V, No Load ILOAD = 4mA In/Out of Pins C1 Through C12 When Measuring Cell When Not Measuring Cell Current Into the V+ Pin When Measuring Continuous Measuring (CDC = 2) Continuous Measuring (CDC = 2) Measure Every 130ms (CDC = 5) Measure Every 500ms (CDC = 6) Measure Every 2 Seconds (CDC = 7) Current Into V+ Pin When In Standby, All Serial Port Pin at Logic “1” LTC6803IG LTC6803HG Current Into V+ Pin During Serial Communications, All Serial Port Pins at Logic “0”. VMODE = “0”, This Current is Added to IS or IQS LTC6803IG LTC6803HG Current Out of V–, VC12 = 43.2V, V+ Floating (Note 8) VCELL > 3V (Note 3)
l l l
IB IS
Input Bias Current
1 780 780 250 175 70 12 12 12 3.9 3.9 3.9 0.001
Supply Current, Measure Mode (Note 7)
l l l l
620 600 190 140 55 8
1000 1150 360 250 105 16.5 18 19 4.3 4.5 4.9 1 20
IQS
Supply Current, Standby
l l
6 6 3.1
ICS
Supply Current, Serial I/O
l l l l l
3 3
ISD
Supply Current, Hardware Shutdown Discharge Switch-On Resistance
10 70 110 145 5
IOW
Current Used for Open-Wire Detection Thermal Shutdown Temperature Thermal Shutdown Hysteresis
140
Voltage Mode Timing Specifications tCYCLE Measurement Cycling Time Required to Measure 12 Cells Time Required to Measure 10 Cells Time Required to Measure 3 Temperatures Time Required to Measure 1 Cell or Temperature
l l l l l l l l l l l l l l
11 9 2.8 1.0 10 250 400 400 400 100 100
13 11 3.4 1.2
t1 t2 t3 t4 t5 t6 t7 t8
SDI Valid to SCKI Rising Setup SDI Valid to SCKI Rising Hold SCKI Low SCKI High CSBI Pulse Width CSBI Falling to SCKI Rising CSBI Falling to SDO Valid SCKI Falling to SDO Valid Clock Frequency Watchdog Timer Timeout Period
Timing Specifications tPD1 tPD2 tPD3 tPD4 CSBI to CSBO SCKI to SCKO SDI to SDOI Write Delay SDI to SDOI Read Delay CCSBO = 150pF CSCKO = 150pF CSDOI = 150pF CSDO = 150pF
l l l l
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LTC6803-1/LTC6803-3 ELECTRICAL CHARACTERISTICS
SYMBOL VIH VIL VOL IIN IIH1 IIL1 IIH2 IIL2 IOH1 IOL1 IOH2 IOL2 PARAMETER Digital Input Voltage High Digital Input Voltage Low Digital Output Voltage Low Digital Input Current Digital Input Current High Digital Input Current Low Digital Input Current High Digital Input Current Low Digital Output Current High Digital Output Current Low Digital Output Current High Digital Output Current Low Voltage Mode Digital I/O Pins SCKI, SDI and CSBI Pins SCKI, SDI and CSBI Pin SDO, Sinking 500µA VMODE, TOS, SCKI, SDI, CSBI Pins CSBI, SCKI, SDI (Write, Pin Sourcing) CSBI, SCKI, SDI (Write, Pin Sourcing) SDOI (Read, Pin Sinking) SDOI (Read, Pin Sinking) CSBO, SCKO, SDOI (Write, Pin Sinking) CSBO, SCKO, SDOI(Write, Pin Sinking) SDI (Read, Pin Sourcing) SDI (Read, Pin Sourcing)
l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 43.2V, V– = 0V, unless otherwise noted.
CONDITIONS MIN 2 0.8 0.3 10 3 1000 1000 10 1000 1000 1000 3 1300 1300 1600 1600 10 10 TYP MAX UNITS V V V µA µA µA µA µA µA µA µA µA
Current Mode Digital I/O
l l l l l l l l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The ADC specifications are guaranteed by the Total Measurement Error (VERR) specification. Note 3: Due to the contact resistance of the production tester, this specification is tested to relaxed limits. The 20Ω limit is guaranteed by design. Note 4: VCELL refers to the voltage applied across Cn to Cn – 1 for n = 1 to 12. VTEMP refers to the voltage applied from VTEMP1 or VTEMP2 to V–.
Note 5: These absolute maximum ratings apply provided that the voltage between inputs do not exceed the absolute maximum ratings. Note 6: Supply current is tested during continuous measuring. The supply current during periodic measuring (130ms, 500ms, 2s) is guaranteed by design. Note 7: The CDC = 5, 6 and 7 supply currents are not measured. They are guaranteed by the CDC = 2 supply current measurement. Note 8: Limit is determined by high speed automated test capability.
TYPICAL PERFORMANCE CHARACTERISTICS
Cell Measurement Error vs Cell Input Voltage
4.5 TOTAL UNADJUSTED ERROR (mV) 3.0 1.5 0 –1.5 –3.0 –4.5 TA = 125°C TA = 85°C TA = 25°C TA = –40°C 5 0 CELL VOLTAGE ERROR (mV) –5 –10 –15 –20 –25 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CELL INPUT VOLTAGE (V)
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Cell Measurement Error vs Input RC Values
0 –5 –10 –15 –20 –25 –30
Cell Measurement Error vs Input RC Values
CELLS 2 TO 12, 13ms CELL MEASUREMENT REPETITION VCELL = 3.3V
–30
C = 0µF C = 0.1µF C = 1µF C = 3.3µF CELL 1, 13ms CELL MEASUREMENT REPETITION VCELL = 3.3V 0 1 2 3 78 456 INPUT RESISTANCE (k ) 9 10
CELL VOLTAGE ERROR (mV)
C = 0µF C = 0.1µF C = 1µF C = 3.3µF 0 1 2 3 78 456 INPUT RESISTANCE (k ) 9 10
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LTC6803-1/LTC6803-3 TYPICAL PERFORMANCE CHARACTERISTICS
Cell 12 Measurement Error vs V+
100 CELL 12 MEASUREMENT ERROR (mV) CELL MEASUREMENT ERROR (mV) TA = 25°C VCELL = 3.3V 2 0 –2 –4 –6 –8 –10 –12 –14 0 1 2 VCELL = 3.6V TA = 25°C CELL2 ERROR vs VC1 CELL3 ERROR vs VC2 CELLn ERROR VS VCn–1, n = 4 TO 12 4 3 COMMON MODE VOLTAGE (V) 5
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Cell Voltage Measurement Error vs Common Mode Voltage
CELL VOLTAGE MEASUREMENT ERROR (mV) 1000
Cell Measurement Error vs Cell Voltage
ALL OTHER CELLS = 3V
100
10
10
CELL6
1
1
0.1 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 V+ – VC12 (V)
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0.1 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 VIN CELL6 (V)
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Cell 1 Voltage Measurement Error vs Temperature
1.75 CELL MEASUREMENT ERROR (mV) 1.00 CELL MEASUREMENT ERROR (mV) VCELL = 0.8V V+ = 9.6V 4 SAMPLES 2.50 1.75 1.00 0.25 –0.50 –1.25
Cell 2 Voltage Measurement Error vs Temperature
CELL MEASUREMENT ERROR (mV) VCELL = 0.8V V+ = 9.6V 4 SAMPLES 1.75 1.00
Cell 3 to Cell 12 Voltage Measurement Error vs Temperature
0.25
0.25
–0.50 –1.25 –2.00 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C)
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–0.50 –1.25
–2.00 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C)
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–2.00 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C)
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VCELL = 0.8V V+ = 9.6V 4 SAMPLES
Measurement Gain Error Hysteresis
25 TA = 85°C TO 25°C 20 18 16 NUMBER OF UNITS
Measurement Gain Error Hysteresis
TA = –45°C TO 25°C 0
Cell Measurement Common Mode Rejection
VCM(IN) = 5VP-P 72dB REJECTION –10 CORRESPONDS TO LESS THAN 1 BIT –20 AT ADC OUTPUT REJECTION (dB) –30 –40 –50 –60 –70 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M
20 NUMBER OF UNITS
14 12 10 8 6 4 2
15
10
5
0 –250 –200 –150 –100 –50 0 50 100 150 200 CHANGE IN GAIN ERROR (ppm)
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0 –250 –200 –150 –100 –50 0 50 100 150 200 CHANGE IN GAIN ERROR (ppm)
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LTC6803-1/LTC6803-3 TYPICAL PERFORMANCE CHARACTERISTICS
ADC Normal Mode Rejection vs Frequency
0 –10 –20 REJECTION (dB) –30 –40 –50 –60 –70 10 100 1k 10k FREQUENCY (Hz) 100k
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ADC INL
2.0 1.5 1.0 DNL (BITS) INL (BITS) 0.5 0 –0.5 –1.0 –1.5 –2.0 0 1 2 3 INPUT (V) 4 5
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ADC DNL
1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1 3 2 INPUT (V) 4 5
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Cell Input Bias Current During Standby and Hardware Shutdown
50 45 CELL INPUT BIAS CURRENT (nA) 40 SUPPLY CURRENT (µA) 35 30 25 20 15 10 5 0 –40 –20 0 C12 C6 C1 20 40 60 80 100 120 TEMPERATURE (°C)
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Standby Supply Current vs Supply Voltage
16 14 SUPPLY CURRENT (µA) 12 10 8 6 4 2 0 0 10 40 30 SUPPLY VOLTAGE (V) 20 125°C 85°C 25°C –40°C 50 60 800 850
Supply Current vs Supply Voltage During Continuous Conversions
CDC = 2 CONTINUOUS CONVERSION
CELL INPUT = 3.6V
750
700 125°C 85°C 25°C –40°C 0 10 20 40 30 SUPPLY VOLTAGE (V) 50 60
650
600
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Internal Die Temperature Measurement Error Using an 8mV/°K Scale Factor
15 10 SAMPLES TOTAL UNADJUSTED ERROR (mV) 4.5 3.0 1.5 0 –1.5 –3.0 –4.5
External Temperature Measurement Total Unadjusted Error vs Input
TA = 125°C TA = 85°C TA = 25°C TA = –40°C
E = (AMBIENT TEMP-INTERNAL DIE TEMP READING) (°C)
10
5
0
–5
–10
0
25
50 75 100 TEMPERATURE (°C)
125
150
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TEMPERATURE INPUT VOLTAGE (V)
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LTC6803-1/LTC6803-3 TYPICAL PERFORMANCE CHARACTERISTICS
VREF Output Voltage vs Temperature
3.070 3.068 3.066 VREF (V) VREF (V) VREF (V) 3.064 3.062 3.060 3.058 3.056 –50 5 REPRESENTATIVE UNITS –25 25 75 0 50 TEMPERATURE (°C) 100 125 3.05 3.07 TA = 85°C TA = 25°C TA = –40°C 3.09
VREF Load Regulation
3.074 3.072 3.070 3.068 3.066 3.064 3.062 0 10 100 SOURCING CURRENT (µA) 1000
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VREF Line Regulation
NO EXTERNAL LOAD ON VREF, CDC = 2 (CONTINUOUS CELL CONVERSIONS)
3.08
TA = 25°C TA = 85°C TA = –40°C
3.06
3.04
3.060
0
10
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20 30 40 SUPPLY VOLTAGE (V)
50
60
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VREG Load Regulation
5.2 5.0 4.8 VREG (V) VREG (V) 4.6 4.4 4.2 4.0 TA = 125°C TA = 85°C TA = 25°C TA = –40°C 0 2 4 6 8 SUPPLY CURRENT (mA) 10 12 5.0 V+ = 43.2V 5.5
VREG Line Regulation
CDC = 2 CONTINUOUS CONVERSIONS DISCHARGE RESISTANCE ( )
Internal Discharge Resistance vs Cell Voltage
50 45 40 35 30 25 20 15 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CELL VOLTAGE (V)
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TA = 105°C TA = 85°C TA = 25°C TA = –45°C
4.5 TA = 125°C TA = 85°C TA = 25°C TA = –40°C 0 10 20 30 40 SUPPLY VOLTAGE (V) 50 60
4.0
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Die Temperature Increase vs Discharge Current in Internal FET
50 INCREASE IN DIE TEMPERATURE (°C) ALL 12 CELLS AT 3.6V 45 VS = 43.2V TA = 25°C 40 35 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 DISCHARGE CURRENT PER CELL (mA)
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Cell Conversion Time
13.20 13.15 CONVERSION TIME (ms) 13.10 13.05 13.00 12.95 12.90 12.85 12.80 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120
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12 CELLS DISCHARGING
6 CELLS DISCHARGING 1 CELL DISCHARGING
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LTC6803-1/LTC6803-3 PIN FUNCTIONS
To ensure pin compatibility with the LTC6802-1, the LTC6803-1 is configured such that the bottom cell input (C0) is connected internally to the negative supply voltage (V–). The LTC6803-3 offers a unique pinout with an input for the bottom cell (C0). This simple functional difference offers the possibility for enhanced cell 1 measurement accuracy, enhanced SPI noise tolerance and simplified wiring. More information is provided in the applications section entitled Advantages of Kelvin Connections for C0. CSBO (Pin 1): Chip Select Output (Active Low). CSBO is a buffered version of the chip select input, CSBI. CSBO drives the next IC in the daisy chain. See Serial Port in the Applications Information section. SDOI (Pin 2): Serial Data I/O Pin. SDOI transfers data to and from the next IC in the daisy chain. See Serial Port in the Applications Information section. SCKO (Pin 3): Serial Clock Output. SCKO is a buffered version of SCKI. SCKO drives the next IC in the daisy chain. See Serial Port in the Applications Information section. V+ (Pin 4): Positive Power Supply. Pin 4 can be tied to the most positive potential in the battery stack or an isolated power supply. V+ must be greater than the most positive potential in the battery stack under normal operation. With an isolated power supply, LTC6803 can be turned off by simply shutting down V+. C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1 (Pins 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27): C1 through C12 are the inputs for monitoring battery cell voltages. The negative terminal of the bottom cell is tied to pin V– for LTC6803-1, pin C0 for LTC6803-3 . The next lowest potential is tied to C1 and so forth. See the figures in the Applications Information section for more details on connecting batteries to the LTC6803-1 and LTC6803-3. The LTC6803 can monitor a series connection of up to 12 cells. Each cell in a series connection must have a common mode voltage that is greater than or equal to the cells below it. 100mV negative voltages are permitted. S12, S11, S10, S9, S8, S7, S6, S5, S4, S3, S2, S1 (Pins 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28): S1 though S12 pins are used to balance battery cells. If one cell in a series becomes overcharged, an S output can be used to discharge the cell. Each S output has an internal N-channel MOSFET for discharging. See the Block Diagram. The NMOS has a maximum on resistance of 20Ω. An external resistor should be connected in series with the NMOS to dissipate heat outside of the LTC6803 package. When using the internal MOSFETs to discharge cells, the die temperature should be monitored. See Power Dissipation and Thermal Shutdown in the Applications Information section. The S pins also feature an internal pull-up PMOS. This allows the S pins to be used to drive the gates of external MOSFETs for higher discharge capability. C0 (Pin 29 on LTC6803-3): Negative Terminal of the Bottom Battery Cell. C0 and V– form Kelvin connections to eliminate effect of voltage drop at the V– trace. V– (Pin 29 on LTC6803-1/ Pin 30 on LTC6803-3): Connect V– to the most negative potential in the series of cells. NC (Pin 30 on LTC6803-1/Pin 31 on LTC6803-3 ): This pin is not used and is internally connected to V– through 10Ω. It can be left unconnected or connected to V– on the PCB. VTEMP1, VTEMP2 (Pins 31, 32 on LTC6803-1/ Pins 32, 33 on LTC6803-3 ): Temperature Sensor Inputs. The ADC measures the voltage on VTEMPn with respect to V– and stores the result in the TMP registers. The ADC measurements are relative to the VREF pin voltage. Therefore a simple thermistor and resistor combination connected to the VREF pin can be used to monitor temperature. The VTEMP inputs can also be general purpose ADC inputs. Any voltage from 0V to 5.125V referenced to V– can be measured. VREF (Pin 33 on LTC6803-1/ Pin 34 on LTC6803-3 ): 3.065V Voltage Reference Output. This pin should be bypassed with a 1µF capacitor. The VREF pin can drive a 100k resistive load connected to V–. Larger loads should be buffered with an LT6003 op amp, or similar device.
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LTC6803-1/LTC6803-3 PIN FUNCTIONS
VREG (Pin 34 on LTC6803-1/ Pin 35 on LTC6803-3 ): Linear Voltage Regulator Output. This pin should be bypassed with a 1µF capacitor. The VREG pin is capable of supplying up to 4mA to an external load. The VREG pin does not sink current. TOS (Pin 35 on LTC6803-1/Pin 36 on LTC6803-3): Top of Stack Input. Tie TOS to VREG when the LTC6803-1 or LTC6803-3 is the top device in a daisy chain. Tie TOS to V– otherwise. When TOS is tied to VREG, the LTC6803-1 or LTC6803-3 ignores the SDOI input and SCKO, CSBO are turned off. When TOS is tied to V–, the LTC6803-1 or LTC6803-3 expects data to be passed to and from the SDOI pin. NC (Pin 36 on LTC6803-1 ): No Connection. WDTB (Pin 37): Watchdog Timer Output (Active Low). If there is no valid command received for 1 to 2.5 seconds, the WDTB output is asserted. The WDTB pin is an open-drain NMOS output. When asserted it pulls the output down to V– and resets the configuration register to its default state. GPIO1, GPIO2 (Pins 38, 39): General Purpose Input/ Output. By writing a “0” to a GPIO configuration register bit, the open-drain output is activated and the pin is pulled to V–. By writing logic “1” to the configuration register bit, the corresponding GPIO pin is high impedance. An external resistor is required to pull the pin up to VREG. By reading the configuration register locations GPIO1 and GPIO2, the state of the pins can be determined. For example, if a “0” is written to register bit GPIO1, a “0” is always read back because the output N-channel MOSFET pulls Pin 38 to V–. If a “1” is written to register bit GPIO1, the pin becomes high impedance. Either a “1” or a “0” is read back, depending on the voltage present at Pin 38. The GPIOs makes it possible to turn on/off circuitry around the LTC6803, or read logic values from a circuit around the LTC6803. The GPIO pins should be connected to V– if not used. VMODE (Pin 40): Voltage Mode Input. When VMODE is tied to VREG, the SCKI, SDI, SDO and CSBI pins are configured as voltage inputs and outputs. This means these pins accept standard TTL logic levels. Connect VMODE to VREG when the LTC6803-1 or LTC6803-3 is the bottom device in a daisy chain. When VMODE is connected to V–, the SCKI, SDI and CSBI pins are configured as current inputs and outputs, and SDO is unused. Connect VMODE to V– when the LTC6803-1 or LTC6803-3 is being driven by another LTC6803-1 or LTC6803-3 in a daisy chain. SCKI (Pin 41): Serial Clock Input. The SCKI pin interfaces to any logic gate (TTL levels) if VMODE is tied to VREG. SCKI must be driven by the SCKO pin of another LTC6803-1 or LTC6803-3 if VMODE is tied to V–. See Serial Port in the Applications Information Section. SDI (Pin 42): Serial Data Input. The SDI pin interfaces to any logic gate (TTL levels) if VMODE is tied to VREG. SDI must be driven by the SDOI pin of another LTC6803-1 or LTC6803-3 if VMODE is tied to V–. See Serial Port in the Applications Information section. SDO (Pin 43): Serial Data Output. The SDO pin is an NMOS open-drain output if VMODE is tied to VREG. A pull-up resistor is needed on SDO. SDO is not used if VMODE is tied to V–. See Serial Port in the Applications Information section. CSBI (Pin 44): Chip Select (Active Low) Input. The CSBI pin interfaces to any logic gate (TTL levels) if VMODE is tied to VREG. CSBI must be driven by the CSBO pin of another LTC6803-1 or LTC6803-3 if VMODE is tied to V–. See Serial Port in the Applications Information section.
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10
LTC6803-1/LTC6803-3 BLOCK DIAGRAMS
LTC6803-1 2ND REFERENCE VREF2 5 6 7 C12 S12 C11 SCKO SDOI 24 25 26 27 28 29 30 S3 C2 S2 C1 REFERENCE S1 V– NC 10 DIE TEMP VTEMP1 31 CONTROL EXTERNAL TEMP VTEMP2 32 VREF 32
68031 BD
4
V+ VREG 34
REGULATOR
WATCHDOG TIMER
WDTB
37
3 2 1 44 43 42 41
CSBO MUX ∆Σ A/D CONVERTER 12 RESULTS REGISTER AND COMMUNICATIONS CSBI SDO SDI SCKI
VMODE GPIO2 GPIO1
40 39 38
NC 36 TOS 35
LTC6803-3 2ND REFERENCE VREF2 5 6 7 C12 S12 C11
4
V+ VREG 35
REGULATOR
WATCHDOG TIMER
WDTB
37
SCKO SDOI
3 2 1 44 43 42 41
24 25 26 27 28 29 30
S3 C2 S2 C1 REFERENCE S1 C0 CONTROL V– 10 NC 31 DIE TEMP VTEMP1 32 EXTERNAL TEMP VTEMP2 33 VREF 34 MUX ∆Σ A/D CONVERTER 12 RESULTS REGISTER AND COMMUNICATIONS
CSBO CSBI SDO SDI SCKI
VMODE GPIO2 GPIO1 TOS
40 39 38 36
68033 BD
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11
LTC6803-1/LTC6803-3 TIMING DIAGRAM
Timing Diagram of the Serial Interface
t1 SCKI t2 t4 t3 t6 t7
SDI
D3
D2
D1
D0 t5
D7···D4
D3
CSBI t8 SDO D4 D3 D2 D1 D0 D7···D4 CURRENT COMMAND D3
680313 TD
PREVIOUS COMMAND
OPERATION
THEORY OF OPERATION The LTC6803 is a data acquisition IC capable of measuring the voltage of 12 series connected battery cells. An input multiplexer connects the batteries to a 12-bit delta-sigma analog-to-digital converter (ADC). An internal 8ppm/°C voltage reference combined with the ADC give the LTC6803 its outstanding measurement accuracy. The inherent benefits of the delta-sigma ADC versus other types of ADCs (e.g., successive approximation) are explained in Advantages of Delta-Sigma ADCs in the Applications Information section. Communication between the LTC6803 and a host processor is handled by an SPI compatible serial interface. As shown in Figure 1, the LTC6803-1s or LTC6803-3s can pass data up and down a stack of devices using simple diodes for isolation. This operation is described in Serial Port in the Applications Information section. The LTC6803 also contains circuitry to balance cell voltages. Internal MOSFETs can be used to discharge cells. These internal MOSFETs can also be used to control external balancing circuits. Figure 1 illustrates cell balancing by internal discharge. Figure 12 shows the S pin controlling an external balancing circuit. It is important to note that the LTC6803 makes no decisions about turning on/off the internal MOSFETs. This is completely controlled by the host processor. The host processor writes values to a configuration register inside the LTC6803 to control the switches. The watchdog timer inside the LTC6803 will turn off the discharge switches if communication with the host processor is interrupted. The LTC6803 has three modes of operation: hardware shutdown, standby and measure. Hardware shutdown is a true zero power mode. Standby mode is a power saving state where all circuits except the serial interface are turned off. In measure mode, the LTC6803 is used to measure cell voltages and store the results in memory. Measure mode will also monitor each cell voltage for overvoltage (OV) and undervoltage (UV) conditions. HARDWARE SHUTDOWN MODE The V+ pin can be disconnected from the C pins and the battery pack. If the V+ supply pin is 0V, the LTC6803 will typically draw less than 1nA from the battery cells. All circuits inside the IC are off. It is not possible to communicate with the IC when V+ = 0V. See the Applications Information section for hardware shutdown circuits. STANDBY MODE The LTC6803 defaults (powers up) to standby mode. Standby mode is the lowest supply current state with a supply connected. Standby current is typically 12µA
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LTC6803-1/LTC6803-3 OPERATION
BATTERY POSITIVE 350V LTC6803-3 IC #8 CSBI CSBO SDO SDOI SDI SCKO SCKI V+ VMODE C12 S12 GPIO2 C11 GPIO1 S11 WDTB C10 TOS S10 VREG C9 VREF S9 VTEMP2 C8 VTEMP1 S8 NC C7 V– S7 C0 C6 S1 S6 C1 C5 S2 S5 C2 C4 S3 S4 C3 BATTERIES #25 TO #84 AND LTC6803-3 ICs #3 TO #7 LTC6803-3 IC #2 CSBI CSBO SDO SDOI SDI SCKO + SCKI V VMODE C12 S12 GPIO2 C11 GPIO1 S11 WDTB C10 TOS S10 VREG C9 VREF S9 VTEMP2 C8 VTEMP1 S8 NC C7 V– S7 C0 C6 S1 S6 C1 C5 S2 S5 C2 C4 S3 S4 C3
+ + + + + + + + + + + +
+ + + + + + + + + + + +
+ + + + + + + + + + + +
LTC6803-3 IC #1 CSBI CSBO SDO SDOI SDI SCKO SCKI V+ VMODE C12 S12 GPIO2 C11 GPIO1 S11 WDTB C10 TOS S10 VREG C9 VREF S9 VTEMP2 C8 VTEMP1 S8 NC C7 V– S7 C0 C6 S1 S6 C1 C5 S2 S5 C2 C4 S3 S4 C3
V2 – OE2
V1– OE1
3V MPU CS MISO MISI CLK 3V
MODULE IO
V2 +
V1–
V2 – V1+ DIGITAL ISOLATOR
680313 F01
Figure 1. 96-Cell Battery Stack, Daisy-Chain Interface. This is a Simplified Schematic Showing the Basic Multi-IC Architecture
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13
LTC6803-1/LTC6803-3 OPERATION
when V+ = 44V. All circuits are turned off except the serial interface and the voltage regulator. For the lowest possible standby current consumption all SPI logic inputs should be set to logic 1 level. The LTC6803 can be programmed for standby mode by setting the comparator duty cycle configuration bits, CDC[2:0], to 0. If the part is put into standby mode while ADC measurements are in progress, the measurements will be interrupted and the cell voltage registers will be in an indeterminate state. To exit standby mode, the CDC bits must be written to a value other than 0. MEASURE MODE The LTC6803 is in measure mode when the CDC bits are programmed with a value from 1 to 7. When CDC = 1 the LTC6803 is on and waiting for a start ADC conversion command. When CDC is 2 through 7 the IC monitors each cell voltage and produces an interrupt signal on the SDO pin indicating all cell voltages are within the UV and OV limits. The value of the CDC bits determines how often the cells are monitored, and how much average supply current is consumed. There are two methods for indicating the UV/OV interrupt status: toggle polling (using a 1kHz output signal) and level polling (using a high or low output signal). The polling methods are described in the Serial Port section. The UV/OV limits are set by the VUV and VOV values in the configuration registers. When a cell voltage exceeds the UV/OV limits a bit is set in the flag register. The UV and OV flag status for each cell can be determined using the Read Flag Register Group. An ADC measurement can be requested at any time when the IC is in measure mode. To initiate cell voltage measurements while in measure mode, a Start A/D Conversion is sent. After the command has been sent, the LTC6803 will indicate the A/D converter status via toggle polling or level polling (as described in the Serial Port section). During cell voltage measurement commands, the UV and OV flags (within the flag register group) are also updated. When the measurements are complete, the part will continue monitoring UV and OV conditions at the rate designated by the CDC bits. Operating with Less than 12 Cells If fewer than 12 cells are connected to the LTC6803, the unused input channels must be masked. The MCxI bits in the configuration registers are used to mask channels. In addition, the LTC6803 can be configured to automatically bypass the measurements of the top 2 cells, reducing power consumption and measurement time. If the CELL10 bit is high, the inputs for cell 11 and cell 12 are masked and only the bottom 10 cell voltages will be measured. By default, the CELL10 bit is low, enabling measurement of all 12 cell voltages. Additional information regarding operation with less than 12 cells is provided in the applications section. ADC RANGE AND OUTPUT FORMAT The ADC outputs a 12-bit code with an offset of 0x200 (512 decimal). The input voltage can be calculated as: VIN = (DOUT – 512) • VLSB; VLSB = 1.5mV where DOUT is a decimal integer. For example, a 0V input will have an output reading of 0x200. An ADC reading of 0x000 means the input was –0.768V. The absolute ADC measurement range is –0.768V to 5.376V. The resolution is VLSB = 1.5mV = (5.376 + 0.768)/212. The useful range is –0.3V to 5V. This range allows monitoring super capacitors, which could have small negative voltage. Inputs below –0.3V exceed the absolute maximum rating of the C pins. If all inputs are negative then the ADC range is reduced to –0.1V. Inputs above 5V will have noisy ADC readings (see Typical Performance Characteristics curves). ADC MEASUREMENTS DURING CELL BALANCING The primary cell voltage ADC measurement commands (STCVAD and STOWAD) automatically turn off a cell’s discharge switch while its voltage is being measured. The discharge switches for the cell above and the cell below will also be turned off during the measurement. For example, discharge switches S4, S5 and S6 will be off while cell 5 is being measured.
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LTC6803-1/LTC6803-3 OPERATION
In some systems it may be desirable to allow discharging to continue during cell voltage measurements. The cell voltage ADC conversion commands STCVDC and STOWDC allow the discharge switches to remain on during cell voltage measurements. This feature allows the system to perform a self test to verify the discharge functionality. All discharge switches are automatically disabled during OV and UV comparison measurements. ADC REGISTER CLEAR COMMAND The clear command can be used to clear the cell voltage registers and temperature registers. The clear command will set all registers to 0xFFF This command is used to . make sure conversions are being made. When cell voltages are stable, ADC results could stay the same. If a start ADC conversion command is sent to the LTC6803 but the PEC fails to match then the command is ignored and the voltage register contents also will not change. Sending a clear command then reading back register contents is a way to make sure LTC6803 is accepting commands and performing new measurements. The clear command takes 1ms to execute. ADC CONVERTER SELF TEST Two self-test commands can be used to verify the functionality of the digital portions of the ADC. The self tests also verify the cell voltage registers and temperature monitoring registers. During these self tests a test signal is applied to the ADC. If the circuitry is working properly all cell voltage and temperature registers will contain 0x555 or 0xAAA. The time required for the self-test function is the same as required to measure all cell voltages or all temperature sensors. MULTIPLEXER AND REFERENCE SELF TEST The LTC6803 uses a multiplexer to measure the 12 battery cell inputs, as well as the temperature signals. A diagnostic command is used to validate the function of the multiplexer, the temperature sensor, and the precision reference circuit. Diagnostic registers will be updated after each diagnostic test. The muxfail bit of the registers will be 1 if the multiplexer self test fails. A constant voltage generated by the 2nd reference circuit will be measured by the ADC and the results written to the diagnostic register. The voltage reading should be 2.5V ±16%. Readings outside this range indicate a failure of the temperature sensor circuit, the precision reference circuit, or the analog portion of the ADC. The DAGN command executes in 16.4ms, which is the sum of the 12-cell tCYCLE and 3 temperature tCYCLE. The diagnostic read command can be used to read the registers. USING THE GENERAL PURPOSE INPUTS/OUTPUTS (GPIO1, GPIO2) The LTC6803 has two general purpose digital input/output pins. By writing a GPIO configuration register bit to a logic low, the open-drain output can be activated. The GPIOs give the user the ability to turn on/off circuitry around the LTC6803. One example might be a circuit to verify the operation of the system. When a GPIO configuration bit is written to a logic high, the corresponding GPIO pin may be used as an input. The read back value of that bit will be the logic level that appears at the GPIO pin. WATCHDOG TIMER CIRCUIT The LTC6803 includes a watchdog timer circuit. The watchdog timer is on for all modes except CDC = 0. The watchdog timer times out if no valid command is received for 1 to 2.5 seconds. When the watchdog timer circuit times out, the WDTB open-drain output is asserted low and the configuration register bits are reset to their default (power-up) state. In the power-up state, CDC is 0, the S outputs are off and the IC is in the low power standby mode. The WDTB pin remains low until a valid command is received. The watchdog timer provides a means to turn off cell discharging should communications to the MPU be interrupted. There is no need for the watchdog timer at CDC = 0 since discharging is off. The open-drain WDTB output can be wire ORd with other external open-drain signals. Pulling the WDTB signal low will not initiate a watchdog event, but the CNFGO bit 7 will reflect the state of this signal. Therefore, the WDTB pin can be used to monitor external digital events if desired.
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LTC6803-1/LTC6803-3 OPERATION
SERIAL PORT Overview The LTC6803 has an SPI bus compatible serial port. Several devices can be daisy chained in series. There are two sets of serial port pins, designated as low side and high side. The low side and high side ports enable devices to be daisy chained even when they operate at different power supply potentials. In a typical configuration, the positive power supply of the first, bottom device is connected to the negative power supply of the second, top device, as shown in Figure 1. When devices are stacked in this manner, they can be daisy chained by connecting the high side port of the bottom device to the low side port of the top device. With this arrangement, the master writes to or reads from the cascaded devices as if they formed one long shift register. The LTC6803-1/LTC6803-3 translate the voltage level of the signals between the low side and high side ports to pass data up and down the battery stack. Physical Layer On the LTC6803-1/LTC6803-3, seven pins comprise the low side and high side ports. The low side pins are CSBI, SCKI, SDI and SDO. The high side pins are CSBO, SCKO and SDOI. CSBI and SCKI are always inputs, driven by the master or by the next lower device in a stack. CSBO and SCKO are always outputs that can drive the next higher device in a stack. SDI is a data input when writing to a stack of devices. For devices not at the bottom of a stack, SDI is a data output when reading from the stack. SDOI is a data output when writing to and a data input when reading from a stack of devices. SDO is an open-drain output that is only used on the bottom device of a stack, where it may be tied with SDI, if desired, to form a single, bi-directional port. The SDO pin on the bottom device of a stack requires a pull-up resistor. For devices up in the stack, SDO should be tied to the local V– or left floating. To communicate between daisy-chained devices, the high side port pins of a lower device (CSBO, SCKO and SDOI) should be connected through high voltage diodes to the respective low side port pins of the next higher device (CSBI, SCKI and SDI). In this configuration, the devices communicate using current rather than voltage. To signal a logic high from the lower device to the higher device, the lower device sinks a smaller current from the higher device pin. To signal a logic low, the lower device sinks a larger current. Likewise, to signal a logic high from the higher device to the lower device, the higher device sources a larger current to the lower device pin. To signal a logic low, the higher device sources a smaller current. See Figure 2. Since CSBO, SCKO and SDOI voltages are close to the V– of high side device, the V– of the high side device must be at least 5V higher than that of the low side device to guarantee current flows of the current mode interface. It is recommended that high voltage diodes be placed in series with the SPI daisy-chain signals as shown if Figure 1. These diodes prevent reverse voltage stress on the IC if a battery group bus bar is removed. See Battery Interconnection Integrity for additional information. Standby current consumed in the current mode serial interface is minimized when CSBI, SCKI and SDI are all high. The voltage mode pin (VMODE) determines whether the low side serial port is configured as voltage mode or current mode. For the bottom device in a daisy-chain stack, this pin must be pulled high (tied to VREG). The other devices in the daisy chain must have this pin pulled low (tied to V–) to designate current mode communication. To designate the top-of-stack device for polling commands, the TOS pin on the top device of a daisy chain must be tied high. The other devices in the stack must have TOS tied low. See Figure 1.
LOW SIDE PORT ON HIGHER DEVICE
VSENSE (WRITE)
+ –
READ 1
WRITE
HIGH SIDE PORT ON LOWER DEVICE
VSENSE (READ)
+ –
680313 F02
Figure 2. Current Mode Interface
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LTC6803-1/LTC6803-3 OPERATION
Data Link Layer Clock Phase And Polarity: The LTC6803 SPI compatible interface is configured to operate in a system using CPHA = 1 and CPOL = 1. Consequently, data on SDI must be stable during the rising edge of SCKI. Data Transfers: Every byte consists of 8 bits. Bytes are transferred with the most significant bit (MSB) first. On a write, the data value on SDI is latched into the device on the rising edge of SCKI (Figure 3). Similarly, on a read, the data value output on SDO is valid during the rising edge of SCKI and transitions on the falling edge of SCKI (Figure 4). CSBI must remain low for the entire duration of a command sequence, including between a command byte and subsequent data. On a write command, data is latched in on the rising edge of CSBI. Network Layer PEC Byte: The packet error code (PEC) byte is a cyclic redundancy check (CRC) value calculated for all of the bits in a register group in the order they are passed, using the initial PEC value of 01000001 (0x41) and the following characteristic polynomial: x8 + x2 + x + 1 To calculate the 8-bit PEC value, a simple procedure can be established: 1. Initialize the PEC to 0100 0001. 2. For each bit DIN coming into the register group, set IN0 = DIN XOR PEC[7], then IN1=PEC[0] XOR IN0, IN2 = PEC[1] XOR IN0. 3. U pdate the 8-bit PEC as PEC[7] = PEC[6], PEC[6] = PEC[5],……PEC[3] = PEC[2], PEC[2] = IN2, PEC[1] = IN1, PEC[0] = IN0. 4. Go back to step 2 until all data are shifted. The 8-bit result is the final PEC byte.
CSBI
SCKI
SDI
MSB (CMD) BIT 6 (CMD)
LSB (PEC) MSB (DATA)
LSB (PEC)
680313 F03
Figure 3. Transmission Format (Write)
CSBI
SCKI
SDI
MSB (CMD) BIT 6 (CMD)
LSB (PEC)
SDO
MSB (DATA)
LSB (PEC)
680313 F04
Figure 4. Transmission Format (Read)
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17
LTC6803-1/LTC6803-3 OPERATION
An example to calculate the PEC is listed in Table 1 and Figure 5. The PEC of the 1 byte data 0x01 is computed as 0xC7 after the last bit of the byte clocked in. For multiple byte data, the PEC is valid at the end (LSB) of the last byte. LTC6803 calculates PEC byte for any command or data received and compares it with the PEC byte following the command or data. The command or data is regarded as valid only if the PEC bytes match. LTC6803 also attaches the calculated PEC byte at the end of the data it shifts out. For daisy-chained LTC6803-1/LTC6803-3, each device computes the PEC byte based on the data it sends out or receives for itself. The data passing through for other devices do affect its PEC. On a read command, each device shifts its data out with, and then shifts out the PEC byte it computed, MSB first. For example, when reading the flag registers from two stacked devices (bottom device A and top device B), the data will be output in the following order: FLGR0(A), FLGR1(A), FLGR2(A), PEC(A), FLGR0(B), FLGR1(B), FLGR2(B), PEC(B ) On a write command, each device receives its data and then the PEC byte, MSB first. For example, when writing configuration registers to two stacked devices (bottom device A and top device B), the data will be input in the following order: CFGRR0(B), CFGR1(B),……, CFGR5(B), PEC(B), CFGR0(A), CFGR1(A),……, CFGR5(A), PEC(A) Broadcast Commands: A broadcast command is one to which all devices on the bus will respond, regardless of
Table 1. Procedure to Calculate PEC Byte
CLOCK CYCLE 0 1 2 3 4 5 6 7 8 DIN 0 0 0 0 0 0 0 1 IN0 0 1 0 0 0 0 0 1 IN1 1 1 1 0 0 0 0 1 IN2 0 0 1 1 0 0 0 1 PEC[7] 0 1 0 0 0 0 0 0 1 PEC[6] 1 0 0 0 0 0 0 1 1 PEC[5] 0 0 0 0 0 0 1 1 0 PEC[4] 0 0 0 0 0 1 1 0 0 PEC[3] 0 0 0 0 1 1 0 0 0 PEC[2] 0 0 0 1 1 0 0 0 1 PEC[1] 0 1 1 1 0 0 0 0 1 PEC[0] 1 0 1 0 0 0 0 0 1
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device address. See the Bus Protocols and Commands sections. In daisy-chained configurations, all devices in the chain receive the command bytes simultaneously. For example, to initiate ADC conversions in a stack of devices, a single STCVAD command is sent, and all devices will start conversions at the same time. For read and write commands, a single command is sent, and then the stacked devices effectively turn into a cascaded shift register, in which data is shifted through each device to the next higher (on a write) or the next lower (on a read) device in the stack. See the Serial Command Examples section. Polling Methods: For ADC conversions, three methods can be used to determine ADC completion. First, a controller can start an ADC conversion and wait for the specified conversion time to pass before reading the results. The second method is to hold CSBI low after an ADC start command has been sent. The ADC conversion status will be output on SDO (Figure 6). A problem with the second method is that the controller is not free to do other serial communication while waiting for ADC conversions to complete. The third method overcomes this limitation. The controller can send an ADC start command, perform other tasks, and then send a poll ADC converter status (PLADC) command to determine the status of the ADC conversions (Figure 7). For OV/UV interrupt status, the poll interrupt status (PLINT) command can be used to quickly determine whether any cell in a stack is in an overvoltage or undervoltage condition (Figure 7).
18
OPERATION
PEC[7] INO PEC1 D CLK Q DTFF DTFF DTFF DTFF PEC[1] CLK Q CLK Q CLK Q Q D Q D Q PEC[1] XOR PEC2 PEC[2] PEC[3] IN0 PEC[2] PEC[3] XOR D
XOR 2 PEC1 = PEC[0] XOR IN0; PEC[5] Q CLK Q DTFF PEC2 = PEC[1] XOR IN0; 3 4
IN0 PEC[0] Q PEC[0] END PEC[4] PEC[4] D Q
PEC[7:0] = {PEC[6:2], PEC2, PEC1, IN0}; PEC[5] PEC[6] D Q CLK Q DTFF PEC[6]
PEC[7] PEC[7] D Q CLK Q DTFF
680313 F05
DATAIN
1 CLK Q
INO = DATAIN XOR PEC[7];
D
BEGIN PEC[7:0] = 0x41
CLOCK
DTFF
PEC Hardware and Software Example
BEGIN PEC[7:0] = 0x41
1
INO = DATAIN XOR PEC[7];
2
PEC1 = PEC[0] XOR IN0;
3
PEC2 = PEC[1] XOR IN0;
4
PEC[7:0] = {PEC[6:2], PEC2, PEC1, IN0};
END
Figure 5
LTC6803-1/LTC6803-3
19
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LTC6803-1/LTC6803-3 OPERATION
CSBI tCYCLE
SCKI
SDI
MSB (CMD) BIT6 (CMD)
LSB (PEC)
SDO
TOGGLE OR LEVEL POLL
680313 F06
Figure 6. Transmission Format (ADC Conversion and Poll)
CSBI
SCKI
SDI
MSB (CMD) BIT6 (CMD)
LSB (PEC)
SDO
TOGGLE OR LEVEL POLL
680313 F07
Figure 7. Transmission Format (PLADC Conversion or PLINT)
Toggle Polling: Toggle polling allows a robust determination both of device states and of the integrity of the connections between the devices in a stack. Toggle polling is enabled when the LVLPL bit is low. After entering a polling command, the data out line will be driven by the slave devices based on their status. When polling for the ADC converter status, data out will be low when any device is busy performing an ADC conversion and will toggle at 1kHz when no device is busy. Similarly, when polling for interrupt status, the output will be low when any device has an interrupt condition and will toggle at 1kHz when none has an interrupt condition. Toggle Polling—Daisy-Chained Broadcast Polling: The SDO pin (bottom device) or SDI pin (stacked devices) will be low if a device is busy/in interrupt. If it is not busy/not in interrupt, the device will pass the signal from the SDOI input to data out (if not the top-of-stack device) or toggle the data out line at 1kHz (if the top-of-stack device). The master pulls CSBI high to exit polling.
Level Polling: Level polling is enabled when the LVLPL bit is high. After entering a polling command, the data out line will be driven by the slave devices based on their status. When polling for the ADC converter status, data out will be low when any device is busy performing an ADC conversion and will be high when no device is busy. Similarly, when polling for interrupt status, the output will be low when any device has an interrupt condition and will be high when none has an interrupt condition. Level Polling—Daisy-Chained Broadcast Polling: The SDO pin (bottom device) or SDI pin (stacked devices) will be low if a device is busy/in interrupt. If it is not busy/not in interrupt, the device will pass the level from the SDOI input to data out (if not the top-of-stack device) or hold the data out line high (if the top-of-stack device). Therefore, if any device in the chain is busy or in interrupt, the SDO signal at the bottom of the stack will be low. If all devices are not busy/not in interrupt, the SDO signal at the bottom of the stack will be high. The master pulls CSBI high to exit polling.
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LTC6803-1/LTC6803-3 OPERATION
Table 2. Protocol Key
PEC N ... Packet Error Code Number of Bits Continuation of Protocol Master-to-Slave Slave-to-Master Complete Byte of Data
Revision Code: The diagnostic register group contains a 2-bit revision code. If software detection of device revision is necessary, then contact the factory for details. Otherwise, the code can be ignored. In all cases, however, the values of all bits must be used when calculating the packet error code (PEC) byte on data reads. Bus Protocols: There are 3 different protocol formats, depicted in Table 3 through Table 5. Table 2 is the key for reading the protocol diagrams.
Table 3. Broadcast Poll Command
8 Command 8 PEC Poll Data
Table 4. Broadcast Read
8 Command 8 PEC 8 Data Byte Low … … 8 Data Byte High 8 PEC 8 Shift Byte 1 … … 8 Shift Byte N
Table 5. Broadcast Write
8 Command 8 PEC 8 Data Byte Low … … 8 Data Byte High 8 PEC 8 Shift Byte 1 … … 8 Shift Byte N
See Serial Command examples.
Table 6. Command Codes and PEC Bytes
COMMAND DESCRIPTION Write Configuration Register Group Read Configuration Register Group Read All Cell Voltage Group Read Cell Voltages 1-4 Read Cell Voltages 5-8 Read Cell Voltages 9-12 Read Flag Register Group Read Temperature Register Group Start Cell Voltage ADC Conversions and Poll Status NAME WRCFG RDCFG RDCV RDCVA RDCVB RDCVC RDFLG RDTMP STCVAD All Cell 1 Cell 2 Cell 3 Cell 4 Cell 5 Cell 6 Cell 7 Cell 8 Cell 9 Cell 10 Cell 11 Cell 12 Clear (FF) Self Test1 Self Test2 CODE 01 02 04 06 08 0A 0C 0E 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F PEC C7 CE DC D2 F8 F6 E4 EA B0 B7 BE B9 AC AB A2 A5 88 8F 86 81 94 93 9A 9D
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LTC6803-1/LTC6803-3 OPERATION
Table 6. Command Codes and PEC Bytes (continued)
COMMAND DESCRIPTION Start Open-Wire ADC Conversions and Poll Status NAME STOWAD All Cell 1 Cell 2 Cell 3 Cell 4 Cell 5 Cell 6 Cell 7 Cell 8 Cell 9 Cell 10 Cell 11 Cell 12 All External1 External2 Internal Self Test 1 Self Test 2 CODE 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 30 31 32 33 3E 3F 40 50 52 54 All Cell 1 Cell 2 Cell 3 Cell 4 Cell 5 Cell 6 Cell 7 Cell 8 Cell 9 Cell 10 Cell 11 Cell 12 All Cell 1 Cell 2 Cell 3 Cell 4 Cell 5 Cell 6 Cell 7 Cell 8 Cell 9 Cell 10 Cell 11 Cell 12 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 70 71 72 73 74 75 76 77 78 79 7A 7B 7C PEC 20 27 2E 29 3C 3B 32 35 18 1F 16 11 04 50 57 5E 59 7A 7D 07 77 79 6B E7 E0 E9 EE FB FC F5 F2 DF D8 D1 D6 C3 97 90 99 9E 8B 8C 85 82 AF A8 A1 A6 B3
Start Temperature ADC Conversions and Poll Status
STTMPAD
Poll ADC Converter Status Poll Interrupt Status Start Diagnose and Poll Status Read Diagnostic Register Start Cell Voltage ADC Conversions and Poll Status, with Discharge Permitted
PLADC PLINT DAGN RDDGNR STCVDC
Start Open-Wire ADC Conversions and Poll Status, with Discharge Permitted
STOWDC
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LTC6803-1/LTC6803-3 OPERATION
Table 7. Configuration (CFG) Register Group
REGISTER CFGR0 CFGR1 CFGR2 CFGR3 CFGR4 CFGR5 RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR BIT 7 WDT DCC8 MC4I MC12I VUV[7] VOV[7] BIT 6 GPIO2 DCC7 MC3I MC11I VUV[6] VOV[6] BIT 5 GPIO1 DCC6 MC2I MC10I VUV[5] VOV[5] BIT 4 LVLPL DCC5 MC1I MC9I VUV[4] VOV[4] BIT 3 CELL10 DCC4 DCC12 MC8I VUV[3] VOV[3] BIT 2 CDC[2] DCC3 DCC11 MC7I VUV[2] VOV[2] BIT 1 CDC[1] DCC2 DCC10 MC6I VUV[1] VOV[1] BIT 0 CDC[0] DCC1 DCC9 MC5I VUV[0] VOV[0]
Table 8. Cell Voltage (CV) Register Group
REGISTER CVR00 CVR01 CVR02 CVR03 CVR04 CVR05 CVR06 CVR07 CVR08 CVR09 CVR10 CVR11 CVR12 CVR13 CVR14 CVR15* CVR16* CVR17* RD/WR RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD BIT 7 C1V[7] C2V[3] C2V[11] C3V[7] C4V[3] C4V[11] C5V[7] C6V[3] C6V[11] C7V[7] C8V[3] C8V[11] C9V[7] C10V[3] C10V[11] C11V[7] C12V[3] C12V[11] BIT 6 C1V[6] C2V[2] C2V[10] C3V[6] C4V[2] C4V[10] C5V[6] C6V[2] C6V[10] C7V[6] C8V[2] C8V[10] C9V[6] C10V[2] C10V[10] C11V[6] C12V[2] C12V[10] BIT 5 C1V[5] C2V[1] C2V[9] C3V[5] C4V[1] C4V[9] C5V[5] C6V[1] C6V[9] C7V[5] C8V[1] C8V[9] C9V[5] C10V[1] C10V[9] C11V[5] C12V[1] C12V[9] BIT 4 C1V[4] C2V[0] C2V[8] C3V[4] C4V[0] C4V[8] C5V[4] C6V[0] C6V[8] C7V[4] C8V[0] C8V[8] C9V[4] C10V[0] C10V[8] C11V[4] C12V[0] C12V[8] BIT 3 C1V[3] C1V[11] C2V[7] C3V[3] C3V[11] C4V[7] C5V[3] C5V[11] C6V[7] C7V[3] C7V[11] C8V[7] C9V[3] C9V[11] C10V[7] C11V[3] C11V[11] C12V[7] BIT 2 C1V[2] C1V[10] C2V[6] C3V[2] C3V[10] C4V[6] C5V[2] C5V[10] C6V[6] C7V[2] C7V[10] C8V[6] C9V[2] C9V[10] C10V[6] C11V[2] C11V[10] C12V[6] BIT 1 C1V[1] C1V[9] C2V[5] C3V[1] C3V[9] C4V[5] C5V[1] C5V[9] C6V[5] C7V[1] C7V[9] C8V[5] C9V[1] C9V[9] C10V[5] C11V[1] C11V[9] C12V[5] BIT 0 C1V[0] C1V[8] C2V[4] C3V[0] C3V[8] C4V[4] C5V[0] C5V[8] C6V[4] C7V[0] C7V[8] C8V[4] C9V[0] C9V[8] C10V[4] C11V[0] C11V[8] C12V[4]
*Registers CVR15, CVR16, and CVR17 can only be read if the CELL10 bit in register CFGR0 is low
Table 9. Flag (FLG) Register Group
REGISTER FLGR0 FLGR1 FLGR2 RD/WR RD RD RD BIT 7 C4OV C8OV C12OV* BIT 6 C4UV C8UV C12UV* BIT 5 C3OV C7OV C11OV* BIT 4 C3UV C7UV C11UV* BIT 3 C2OV C6OV C10OV BIT 2 C2UV C6UV C10UV BIT 1 C1OV C5OV C9OV BIT 0 C1UV C5UV C9UV
* Bits C11UV, C12UV, C11OV and C12OV are always low if the CELL10 bit in register CFGR0 is high
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LTC6803-1/LTC6803-3 OPERATION
Table 10. Temperature (TMP) Register Group
REGISTER TMPR0 TMPR1 TMPR2 TMPR3 TMPR4 RD/WR RD RD RD RD RD BIT 7 ETMP1[7] ETMP2[3] ETMP2[11] ITMP[7] NA BIT 6 ETMP1[6] ETMP2[2] ETMP2[10] ITMP[6] NA BIT 5 ETMP1[5] ETMP2[1] ETMP2[9] ITMP[5] NA BIT 4 ETMP1[4] ETMP2[0] ETMP2[8] ITMP[4] THSD BIT 3 ETMP1[3] ETMP1[11] ETMP2[7] ITMP[3] ITMP[11] BIT 2 ETMP1[2] ETMP1[10] ETMP2[6] ITMP[2] ITMP[10] BIT 1 ETMP1[1] ETMP1[9] ETMP2[5] ITMP[1] ITMP[9] BIT 0 ETMP1[0] ETMP1[8] ETMP2[4] ITMP[0] ITMP[8]
Table 11. Packet Error Code (PEC)
REGISTER PEC RD/WR RD BIT 7 PEC[7] BIT 6 PEC[6] BIT 5 PEC[5] BIT 4 PEC[4] BIT 3 PEC[3] BIT 2 PEC[2] BIT 1 PEC[1] BIT 0 PEC[0]
Table 12. Diagnostic Register Group
REGISTER DGNR0 DGNR1 RD/WR RD RD BIT 7 REF[7] REV[1] BIT 6 REF[6] REV[0] BIT 5 REF[5] MUXFAIL BIT 4 REF[4] NA BIT 3 REF[3] REF[11] BIT 2 REF[2] REF[10] BIT 1 REF[1] REF[9] BIT 0 REF[0] REF[8]
Table 13. Memory Bit Descriptions
NAME DESCRIPTION VALUES CDC 0 (default) 1 CDC Comparator Duty Cycle 2 3 4 5 6 7 CELL10 LVLPL GPIO1 GPIO2 WDT DCCx VUV VOV MUXFAIL 10-Cell Mode Level Polling Mode GPIO1 Pin Control GPIO2 Pin Control Watchdog Timer Discharge Cell x Undervoltage Comparison Voltage* Overvoltage Comparison Voltage* Multiplexer Self Test Result UV/OV COMPARATOR PERIOD N/A (Comparator Off) Standby Mode N/A (Comparator Off) 13ms 130ms 500ms 130ms 500ms 2000ms VREF POWERED DOWN BETWEEN MEASUREMENTS Yes No No No No Yes Yes Yes CELL VOLTAGE MEASUREMENT TIME N/A 13ms 13ms 13ms 13ms 21ms 21ms 21ms
0 = 12-cell mode (default); 1 = 10-cell mode 0 = toggle polling (default); 1 = level polling Write: 0 = GPIO1 pin pull-down on; 1 = GPIO1 pin pull-down off (default) Read: 0 = GPIO1 pin at logic ‘0’; 1 = GPIO1 pin at logic ‘1’ Write: 0 = GPIO2 pin pull-down on; 1 = GPIO2 pin pull-down off (default) Read: 0 = GPIO2 pin at logic ‘0’; 1 = GPIO2 pin at logic ‘1’ Read: 0 = WDT pin at logic ‘0’; 1 = WDT pin at logic ‘1’ x = 1..12 0 = turn off shorting switch for cell ‘x’ (default); 1 = turn on shorting switch Comparison voltage = (VUV – 31) • 16 • 1.5mV Comparison voltage = (VOV – 32) • 16 • 1.5mV Read: 0 = test passed; 1 = test failed
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LTC6803-1/LTC6803-3 OPERATION
Table 13. Memory Bit Descriptions (continued)
NAME MCxI CxV CxUV CxOV ETMPx THSD REV ITMP PEC REF DESCRIPTION Mask Cell x Interrupts Cell x Voltage* Cell x Undervoltage Flag Cell x Overvoltage Flag External Temperature Measurement* Thermal Shutdown Status Revision Code Internal Temperature Measurement* Packet Error Code Reference Voltage for Diagnostics VALUES x = 1..12 0 = enable interrupts for cell ‘x’ (default) 1 = turn off interrupts and clear flags for cell ‘x’ x = 1..12 12-bit ADC measurement value for cell ‘x’ cell voltage for cell ‘x’ = (CxV – 512) • 1.5mV reads as 0xFFF while A/D conversion in progress x = 1..12 cell voltage compared to VUV comparison voltage 0 = cell ‘x’ not flagged for undervoltage condition; 1 = cell ‘x’ flagged x = 1..12 cell voltage compared to VOV comparison voltage 0 = cell ‘x’ not flagged for overvoltage condition; 1 = cell ‘x’ flagged Temperature measurement voltage = (ETMPx – 512) • 1.5mV 0 = thermal shutdown has not occurred; 1 = thermal shutdown has occurred Status cleared to ‘0’ on read of Thermal Register Group Device revision code Temperature measurement voltage = (ITMP – 512) • 1.5mV = 8mV * T(°K) Cyclic redundancy check (CRC) value This reference voltage = (REF – 512) • 1.5mV. Normal range is within 2.1V to 2.9V
*Voltage equations use the decimal value of the registers, 0 to 4095 for 12-bit and 0 to 255 for 8-bit registers
SERIAL COMMAND EXAMPLES Examples below use a configuration of three stacked LTC6803-1 or LTC6803-3 devices: bottom (B), middle (M), and top (T) Write Configuration Registers (Figure 8) 1. Pull CSBI low 2. Send WRCFG command and its PEC byte 3. Send CFGR0 byte for top device, then CFGR1 (T), …CFGR5 (T), PEC of CFGR0(T) to CFGR5(T) 4. Send CFGR0 byte for middle device, then CFGR1 (M) … CFGR5 (M) ), PEC of CFGR0(M) to CFGR5(M) 5. Send CFGR0 byte for bottom device, then CFGR1 (B), … CFGR5 (B) ), PEC of CFGR0(B) to CFGR5(B) 6. Pull CSBI high; data latched into all devices on rising edge of CSBI. S pins respond as data latched. Calculation of serial interface time for sequence above: Number of devices in stack = N Number of bytes in sequence = B = 2 command byte and 7 data bytes per device = 2 + 7 • N Serial port frequency per bit = F Time = (1/F) • B • 8 bits/byte = (1/F) • (2 + 7 • N) • 8 Time for 3-cell example above, with 1MHz serial port = (1/1000000) • (2 + 7 • 3) • 8 = 184µs
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LTC6803-1/LTC6803-3 OPERATION
CSBI SCKI
SDI
WRCFG + CFGR + PEC td td < 2µs IF Sn IS UNLOADED Sn, DISCHARGE PIN STATE
680313 F08
Sn (n = 1 TO 12)
Figure 8. S Pin Action and SPI Transmission
Read Cell Voltage Registers (12 Cell Mode) 1. Pull CSBI low 2. Send RDCV command and PEC 3. Read CVR00 byte of bottom device, then CVR01 (B), CVR02 (B), … CVR17 (B), and then PEC (B) 4. Read CVR00 byte of middle device, then CVR01 (M), CVR02 (M), … CVR17 (M), and then PEC (M) 5. Read CVR00 byte for top device, then CVR01 (T), CVR02 (T), … CVR17 (T), and then PEC (T) 6. Pull CSBI high Calculation of serial interface time for sequence above: Number of devices in stack = N Number of bytes in sequence = B = 2 command byte, and 18 data bytes plus 1 PEC byte per device = 2 + 19 • N Serial port frequency per bit = F Time = (1/F) • B • 8 bits/byte = (1/F) • (2 + 19 • N) • 8 Time for 3-cell example above, with 1MHz serial port = (1/1000000) • (2 + 19 • 3) • 8 = 472µs Start Cell Voltage ADC Conversions and Poll Status (Toggle Polling) 1. Pull CSBI low 2. Send STCVAD command byte and PEC (all devices in stack start ADC conversions simultaneously) 3. SDO output from bottom device pulled low for approximately 12ms 4. SDO output toggles at 1kHz rate, indicating conversions complete for all devices in daisy chain 5. Pull CSBI high to exit polling Start Cell Voltage ADC Conversions and Poll Status (Broadcast Command with Toggle Polling) 1. Pull CSBI low 2. Send STCVAD command and PEC (all devices in stack start ADC conversions simultaneously) 3. SDO output of all devices in parallel pulled low for approximately 12ms 4. SDO output toggles at 1kHz rate, indicating conversions complete for all devices in the daisy chain 5. Pull CSBI high to exit polling Poll Interrupt Status (Level Polling) 1. Pull CSBI low 2. Send PLINT command and PEC 3. SDO output from bottom device pulled low if any device has an interrupt condition; otherwise, SDO high 4. Pull CSBI high to exit polling
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LTC6803-1/LTC6803-3 APPLICATIONS INFORMATION
DIFFERENCE BETWEEN THE LTC6803-1 AND LTC6803-3 The only difference between the LTC6803-1 and the LTC6803-3 is the bonding of the V– and C0 pins. The V– and C0 are separate signals on every LTC6803 die. In the LTC6803-1 package, the V– and C0 signals are shorted together by bonding these signals to the same pin. In the LTC6803-3 package, V– and C0 are separate pins. Therefore, the LTC6803-1 is pin compatible with the LTC6802-1. For new designs the LTC6803-3 pinout allows a Kelvin connection to C0 (Figure 24). CELL VOLTAGE FILTERING The LTC6803 employs a sampling system to perform its analog-to-digital conversions and provides a conversion result that is essentially an average over the 0.5ms conversion window, provided there isn’t noise aliasing with respect to the delta-sigma modulator rate of 512kHz. This indicates that a lowpass filter with 30dB attenuation at 500kHz may be beneficial. Since the delta-sigma integration bandwidth is about 1kHz, the filter corner need not be lower than this to assure accurate conversions. Series resistors of 100Ω may be inserted in the input paths without introducing meaningful measurement error. Shunt capacitors may be added from the cell inputs to V–, creating RC filtering as shown in Figure 9. The cell balancing MOSFET in Figure 12 can cause a small transient when it switches on and off. Keeping the cutoff frequency of the RC filter relatively high will allow adequate settling prior to the actual conversion. A delay of about 500µs is provided in the ADC timing, so a 16kHz LPF is optimal (100Ω, 0.1µF) and offers 30dB of noise rejection.
100
Larger series resistors and shunt capacitors can be used to lower the filter bandwidth. The measurement error due to the larger component values is a complex function of the component values. The error also depends on how often measurements are made. Table 14 is an example. In each example a 3.6V cell is being measured and the error is displayed in millivolts. There is a RC filter in series with inputs C1 through C12 for the LTC6803-1. There is an RC filter in series with inputs C0 through C12 for the LTC6803-3.
Table 14. Cell Measurement Errors vs Input RC Values
R = 100Ω, R = 1k, C = 0.1µF C = 0.1µF Cell 1 Error (mV, LTC6803-1) Cell 2 to Cell 12 (mV) 0.5 1 4.5 9 R = 1k, C = 1µF 1.5 3 R = 10k, C = 3.3µF 1.5 0.5
For the LTC6803-1, no resistor should be placed in series with the V– pin. Because the supply current flows from the V– pin, any resistance on this pin could generate a significant conversion error for cell 1, and the error of cell 1 caused by the RC filter differs from errors of cell 2 to cell 12. OPEN CONNECTION DETECTION When a cell input (C pin) is open, it affects two cell measurements. Figure 10 shows an open connection to C3, in an application without external filtering between the C pins and the cells. During normal ADC conversions (that is, using the STCVAD command), the LTC6803 will give near zero readings for B3 and B4 when C3 is open. The zero reading for B3 occurs because during the measurement of B3, the ADC input resistance will pull C3 to the C2 potential. Similarly, during the measurement of B4, the ADC input resistance pulls C3 to the C4 potential. Figure 11 shows an open connection at the same point in the cell stack as Figure 10, but this time there is an external filtering network still connected to C3. Depending on the value of the capacitor remaining on C3, a normal measurement of B3 and B4 may not give near-zero readings, since the C3 pin is not truly open. In fact, with a large external capacitance on C3, the C3 voltage will be charged midway
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Cn 100nF 7.5V C(n – 1)
+
100
100nF
680313 F09
Figure 9. Adding RC Filtering to the Cell Inputs (One Cell Connection Shown)
27
LTC6803-1/LTC6803-3 APPLICATIONS INFORMATION
+
B4 B3
+ + + +
21 23 25 27 29
C4 C3 C2 C1 V– MUX
LTC6803-1
in the value of battery connected between inputs C3 and C4 (battery B4). The following algorithm can be used to detect an open connection to cell pin Cn: 1. Issue a STOWAD command (with 100µA sources connected).
100µA
2. Issue a RDCV command and store all cell measurements into array CELLA(n).
680313 F10
3. Issue the 2nd STOWAD command (with 100µA sources connected). 4. Issue the 2nd RDCV command and store all cell measurements into array CELLB(n).
Figure 10. Open Connection
+
B4 B3
+ + + +
21 CF4 23 CF3 25 27 29
C4 C3 C2 C1 V– MUX
LTC6803-1
5. For battery cells, if CELLA(1) < 0 or CELLB(1) < 0, V– must be open. If CELLA(12) < 0 or CELLB(12) < 0, C12 must be open. For n = 2 to 11, if CELLB(n+1) – CELLA(n+1) > 200mV, or CELLB(n+1) reaches the full scale of 5.375V, then Cn is open. The 200mV threshold is chosen to provide tolerance for measurement errors. For a system with the capacitor connected to Cn larger than 0.5µF repeating step 3 several , times will discharge the external capacitor enough to meet the criteria. If the top C pin is open yet V+ is still connected, then the best way to detect an open connection to the top C pin is by comparing the sum of all cell measurements using the STCVAD command to an auxiliary measurement of the sum of all the cells, using a method similar to that shown in Figure 21. A significantly lower result for the sum of all 12 cells suggests an open connection to the top C pin, provided it was already determined that no other C pin is open. USING THE S PINS AS DIGITAL OUTPUTS OR GATE DRIVERS The S outputs include an internal pull-up PMOS. Therefore the S pins will behave as a digital output when loaded with a high impedance, e.g., the gate of an external MOSFET. For applications requiring high battery discharge currents, connect a discrete PMOS switch device and suitable
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100µA
680313 F11
Figure 11. Open Connection with RC Filtering
between C2 and C4 after several cycles of measuring cells B3 and B4. Thus the measurements for B3 and B4 may indicate a valid cell voltage when in fact the exact state of B3 and B4 is unknown. To reliably detect an open connection, the command STOWAD is provided. With this command, two 100µA current sources are connected to the ADC inputs and turned on during all cell conversions. Referring again to Figure 11, with the STOWAD command, the C3 pin will be pulled down by the 100µA current source during the B3 cell measurement and during the B4 cell measurement. This will tend to decrease the B3 measurement result and increase the B4 measurement result relative to the normal STCVAD command. The biggest change is observed in the B4 measurement when C3 is open. So, the best method to detect an open wire at input C3 is to look for an increase
28
LTC6803-1/LTC6803-3 APPLICATIONS INFORMATION
discharge resistor to the cell, and the gate terminal to the S output pin, as illustrated in Figure 12.
C (n) 3.3k 33 1W
680313 F12
Since thermal shutdown interrupts normal operation, the internal temperature monitor should be used to determine when the device temperature is approaching unacceptable levels. USING THE LTC6803 WITH LESS THAN 12 CELLS If the LTC6803 is powered by the stacked cells, the minimum number of cells is governed by the supply voltage requirements of the LTC6803. The sum of the cell voltages must be 10V to guarantee that all electrical specifications are met. Figure 13 shows an example of the LTC6803 when used to monitor seven cells. The lowest C inputs connect to theseven cells and the upper C inputs connect to C12. Other configurations, e.g., 9 cells, would be configured in the same way: the lowest C inputs connected to the battery cells and the unused C inputs connected to C12. The unused inputs will result in a reading of 0V for those channels. The ADC can also be commanded to measure a stack of 10 or 12 cells, depending on the state of the CELL10 bit in the control register. The ADC can also be commanded to measure any individual cell voltage. FAULT PROTECTION Care should always be taken when using high energy sources such as batteries. There are numerous ways that systems can be misconfigured when considering the assembly and service procedures that might affect a battery system during its useful lifespan. Table 15 shows the various situations that should be considered when planning protection circuitry. The first five scenarios are to be anticipated during production and appropriate protection is included within the LTC6803-1/LTC6803-3 device itself. BATTERY INTERCONNECTION INTEGRITY The FMEA scenarios involving a break in the stack of battery cells are potentially the most damaging. In the case where the battery stack has a discontinuity between groupings of cells monitored by LTC6803 ICs, any load will force a large reverse potential on the daisy-chain connection. This
Si2351DS
+
S (n) C (n – 1)
Figure 12. External Discharge FET Connection (One Cell Shown)
POWER DISSIPATION AND THERMAL SHUTDOWN The MOSFETs connected to the pins S1 through S12 can be used to discharge battery cells. An external resistor should be used to limit the power dissipated by the MOSFETs. The maximum power dissipation in the MOSFETs is limited by the amount of heat that can be tolerated by the LTC6803. Excessive heat results in elevated die temperatures. The electrical characteristics for the LTC6803 I-grade are guaranteed for die temperatures up to 85°C. Little or no degradation will be observed in the measurement accuracy for die temperatures up to 105°C. Damage may occur above 150°C, therefore the recommended maximum die temperature is 125°C. To protect the LTC6803 from damage due to overheating, a thermal shutdown circuit is included. Overheating of the device can occur when dissipating significant power in the cell discharge switches. The problem is exacerbated when the thermal conductivity of the system is poor. The thermal shutdown circuit is enabled whenever the device is not in standby mode (see Modes of Operation). It will also be enabled when any current mode input or output is sinking or sourcing current. If the temperature detected on the device goes above approximately 145°C, the configuration registers will be reset to default states, turning off all discharge switches and disabling ADC conversions. When a thermal shutdown has occurred, the THSD bit in the temperature register group will go high. The bit is cleared by performing a read of the temperature registers (RDTMP command).
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LTC6803-1/LTC6803-3 APPLICATIONS INFORMATION
NEXT HIGHER GROUP OF 7 CELLS NEXT HIGHER GROUP OF 7 CELLS
100
+ + + + + + +
V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 LTC6803-1 C6 S6 C5 S5 C4 S4 C3 S3 C2 S2 C1 S1 V–
100
+ + + + + + +
V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 LTC6803-3 C6 S6 C5 S5 C4 S4 C3 S3 C2 S2 C1 S1 C0 V–
680313 F13
NEXT LOWER GROUP OF 7 CELLS
NEXT LOWER GROUP OF 7 CELLS
Figure 13. Monitoring 7 Cells with the LTC6803-1/LTC6803-3 Table 15. LTC6803-1/LTC6803-3 Failure Mechanism Effect Analysis
SCENARIO Cell input open-circuit (random). Cell input open-circuit (random). EFFECT Power-up sequence at IC inputs. Differential input voltage overstress. DESIGN MITIGATION Clamp diodes at each pin to V+ and V– (within IC) provide alternate power path. Zener diodes across each cell voltage input pair (within IC) limits stress. Separate power may be supplied by a local supply.
Disconnection of a harness Loss of supply connection to the IC. between a group of battery cells and the IC (in a system of stacked groups). Data link disconnection between Break of "daisy-chain" communication (no stress to stacked LTC6803 units. ICs). Communication will be lost to devices above the disconnection. The devices below the disconnection are still able to communicate and perform all functions, however, the polling feature is disabled. Cell-pack integrity, break between Daisy-chain voltage reversal up to full stack potential stacked units. during pack discharge. Cell-pack integrity, break between stacked units. Cell-pack integrity, break within stacked unit. Cell-pack integrity, break within stacked unit. Daisy-chain positive overstress during charging. Cell input reverse overstress during discharge. Cell input positive overstress during charge.
All units above the disconnection will enter standby mode within 2 seconds of disconnect. Discharge switches are disabled in standby mode. Use series protection diodes with top-port I/O connections (RS07J for up to 600V). Use isolated data link at bottommost data port. Add redundant current path link. See Figure 14. Add parallel Schottky diodes across each cell for loadpath redundancy. Diode and connections must handle full operating current of stack, will limit stress on IC. Add SCR across each cell for charge-path redundancy. SCR and connections must handle full charging current of stack, will limit stress on IC by selection of trigger Zener.
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LTC6803-1/LTC6803-3 APPLICATIONS INFORMATION
situation might occur in a modular battery system during initial installation or a service procedure. The daisy-chain ports are protected from the reverse potential in this scenario by external series high voltage diodes required in the upper port data connections as shown in Figure 14. During the charging phase of operation, this fault would lead to forward biasing of daisy-chain ESD clamps that would also lead to part damage. An alternative connection to carry current during this scenario will avoid this stress from being applied (Figure 14).
+
V– PROTECT AGAINST BREAK HERE OPTIONAL REDUNDANT CURRENT PATH V
+
4 5 6 7 8 9 10 11 12 13 14
V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 S2 C1 S1 C0
LTC6803-3 SCKO
3
SDOI
2
ZCLAMP
CSBO
1
ZCLAMP ZCLAMP ZCLAMP
ZCLAMP ZCLAMP ZCLAMP VREG VREF 35 34 33 32
LTC6803-1 (NEXT HIGHER IN STACK) SDO SDI SCKI CSBI RSO7J ×3 SDOI SCKO CSBO
15 16 17 18 19 20 21
ZCLAMP
VTEMP2 VTEMP1
+
CSBI SDO SDI SCKI VMODE ZCLAMP GPIO2 GPIO1 WDTB TOS
44 43 42 41 40 39 38 37 36
LTC6803-1 (NEXT LOWER IN STACK)
860313 F14
22 23 24 25 26
Figure 14. Reverse-Voltage Protection for the Daisy Chain (One Link Connection Shown)
Internal Protection Diodes Each pin of the LTC6803 has protection diodes to help prevent damage to the internal device structures caused by external application of voltages beyond the supply rails as shown in Figure 15. The diodes shown are conventional silicon diodes with a forward breakdown voltage of 0.5V. The unlabeled Zener diode structures have a reversebreakdown characteristic which initially breaks down at 12V then snaps back to a 7V clamping potential. The Zener diodes labeled ZCLAMP are higher voltage devices with an initial reverse breakdown of 30V snapping back to 25V. The forward voltage drop of all Zeners is 0.5V. Refer to Figure 15 in the event of unpredictable voltage clamping or current flow. Limiting the current flow at any pin to ±10mA will prevent damage to the IC.
27 28 29
V– 30 NOTE: NOT SHOWN ARE PN DIODES TO ALL OTHER PINS FROM PIN 30
680313 F15
Figure 15. Internal Protection Diodes
READING EXTERNAL TEMPERATURE PROBES The LTC6803 includes two channels of ADC input, VTEMP1 and VTEMP2, that are intended to monitor thermistors (tempco about –4%/°C generally) or diodes (–2.2mV/°C typical) located within the cell array. Sensors can be powered directly from VREF as shown in Figure 16 (up to 60µA total).
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31
LTC6803-1/LTC6803-3 APPLICATIONS INFORMATION
For sensors that require higher drive currents, a buffer op amp may be used as shown in Figure 17. Power for the sensor is actually sourced indirectly from the VREG pin in this case. Probe loads up to about 1mA maximum are supported in this configuration. Since VREF is shutdown during the LTC6803 idle and shutdown modes, the thermistor drive is also shut off and thus power dissipation minimized. Since VREG remains always on, the buffer op amp (LT6000 shown) is selected for its ultralow power consumption (12µA). Expanding Probe Count As shown Figure 18, a dual 4:1 multiplexer is used to expand the general purpose VTEMP1 and VTEMP2 ADC inputs to accept 8 different probe signals. The channel is selected by setting the general purpose digital outputs GPIO1 and GPIO2 and the resultant signals are buffered by sections of the LT6004 micropower dual operational amplifier. The probe excitation circuitry will vary with probe type and is not shown here. Another method of multiple sensor support is possible without the use of any GPIO pins. If the sensors are PN diodes and several used in parallel, then the hottest diode will produce the lowest forward voltage and effectively establish the input signal to the VTEMP input(s). The hottest diode will therefore dominate the readout from the VTEMP inputs that the diodes are connected to. In this scenario, the specific location or distribution of heat is not known, but such information may not be important in practice. Figure 19 shows the basic concept. In any of the sensor configurations shown, a full-scale cold readout would be an indication of a failed open-sensor connection to the LTC6803.
LTC6803-1 VREG VREF VTEMP2 VTEMP1 NC V– CPO2 GPO1 VREG VTEMP2 VTEMP1 1/2 LT6004 8 +3 1 2 4 V–
680313 F18
+
LT6000
–
LTC6803-1 VREG VREF VTEMP2 VTEMP1 NC V– 10k 10k
10k NTC
680313 F17
10k NTC
Figure 17. Buffering VREF for Higher Current Sensors
PROBE8 PROBE7 PROBE6 PROBE5 1 2 3 4 5 6 7 8 Y0 VCC X2 Y2 X1 Y X Y3 74HC4052 X0 Y1 X3 INH A VEE GND B 16 15 14 13 12 11 10 9 PROBE4 PROBE3 PROBE2 PROBE1
4
Figure 18. Expanding Sensor Count with Multiplexing
100k
100k
1µF
1µF
100k NTC
680313 F16
100k NTC
Figure 19. Using Diode Sensors as Hot Spot Detectors
Figure 16. Driving Thermistors Directly from VREF
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32
+–
7
6
5 8
1/2 LT6004
–
1µF
LTC6803-1 VREG VREF VTEMP2 VTEMP1 NC V–
200k 200k
680313 F19
LTC6803-1/LTC6803-3 APPLICATIONS INFORMATION
ADDING CALIBRATION AND FULL-STACK MEASUREMENTS The general purpose VTEMP ADC inputs may be used to digitize any signals from 0V to 4V with accuracy corresponding closely with that of the cell 1 ADC input. One useful signal to provide is a high accuracy voltage reference, such as 3.300V from an LTC6655-3.3. From periodic readings of this signal, the host software can provide correction of the LTC6803 readings to improve the accuracy over that of the internal LTC6803 reference and/or validate ADC operation. Figure 20 shows a means of selectively powering an LTC6655-3.3 from the battery stack, under the control of the GPIO1 output of the LTC6803-1. Since the operational power of the reference IC would add significant
TOP CELL POTETNTIAL CZT5551 LTC6803-1 38 GPIO1 VREG VTEMP1 V– 34 31 29 1M Si2351DS 100nF LTC6655-3.3 8 GND SHDN 7 2 VOUT_F VIN 6 3 GND VOUT_S 5 4 GND GND 1
thermal loading to the LTC6803 if powered from VREG, an external high voltage NPN pass transistor is used to form a local 4.4V (Vbe below VREG) from the battery stack. The GPIO1 signal controls a PMOS FET switch to activate the reference when calibration is to be performed. Since GPIO signals default to logic high in shutdown, the reference will automatically turn off during idle periods. Another useful signal is a measure of the total stack potential. This provides a redundant operational measurement of the cells in the event of a malfunction in the normal acquisition process, or as a faster means of monitoring the entire stack potential. Figure 21 shows how a resistive divider is used to derive a scaled representation of a full cell group potential. A MOSFET is used to disconnect
1µF
10µF
680313 F20
Figure 20. Providing Measurement of Calibration Reference
CELL GROUP+ WDTB VREG
499k 1M 2N7002K 2 8 3 1µF 1 3
VTEMP1
1
+ –
1/2 LT6004 4
2
10nF 31.6k
V– CELL GROUP–
680313 F21
Figure 21. Using a VTEMP Input for Full-Stack Readings
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33
LTC6803-1/LTC6803-3 APPLICATIONS INFORMATION
the resistive loading on the cell group when the IC enters standby mode (i.e., when WDTB goes low). An LT6004 micropower operational amplifier section is shown for buffering the divider signal to preserve accuracy. This circuit has the virtue that it can be converted about four times more frequently than the entire battery array, thus offering a higher sample rate option at the expense of some precision/accuracy, reserving the high resolution cell readings for calibration and balancing data. PROVIDING HIGH SPEED ISOLATION OF THE SPI DATA PORT Isolation techniques that are capable of supporting the 1Mbps data rate of the LTC6803 require more power on the isolated (battery) side than can be furnished by the VREG output of the LTC6803. To keep battery drain minimal, this means that a DC/DC function must be implemented
Si8441AB-C-IS QUAD ISOLATOR VDD1 GND1 A1 A2 A3 A4 EN1 GND1 VDD2 GND2 B1 B2 B3 B4 EN2 GND2
along with a suitable data isolation circuit, such as shown in Figure 22. A quad (3 + 1) data isolator Si8441AB-C-IS is used to provide non-galvanic SPI signal connections between a host microprocessor and an LTC6803. An inexpensive isolated DC/DC converter provides powering of the isolator function completely from the host 5V power supply. A quad three-state buffer is used to allow SPI inputs at the LTC6803 to rise to logic high level when the isolator circuitry powers down, assuring the lowest power consumption in the standby condition. The pullups to VREG are selected to match the internal loading on VREG by ICs operating with a current mode SPI interface, thus balancing the current in all cells during operation. The additional pull-up on the SDO line (1k resistor and Schottky diode) is to improve rise time, in lower data-rate applications this may not be needed.
5V_HOST 100 100 100 100 1µF GND_HOST 1µF
1 2
16 15 14 13 12 11 10 9 1µF 12 13 11 1/4 74ABT126 2 1
CMDSH2-3
1k 4.22k
SPI_CLOCK SPI_CHIPSELECT SPI_MASTEROUT SPI_MASTERIN
3 4 5 6 7 8
VREG SCKI
4.22k 3 4 5 6 4.22k 10 8 9
680313 F22
CSB1 4.22k SCI SDO V–
1/4 74ABT126
1/4 74ABT126
1/4 74ABT126 1 LTC1693-2 8 IN1 VCC1 2 7 GND1 OUT1 3 6 IN2 VCC2 4 5 GND2 OUT2 33nF BAT54S 74ABT126 SUPPLY SHARED WITH ISOLATOR VDD2 and GND2
470pF
PE-68386 1• 3
•6
4
20.0k 10.0k
Figure 22. Providing an Isolated High Speed Data Interface
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LTC6803-1/LTC6803-3 APPLICATIONS INFORMATION
SUPPLY DECOUPLING IF BATTERY-STACK POWERED As shown in Figure 23, the LTC6803-3 can have filtering on both V+ and V–, so differential bypassing to the cell group potentials is recommended. The Zener suppresses overvoltages from reaching the IC supply pins. A small ferrite-bead inductor provides protection for the Zener, particularly from energetic ESD strikes. Since the LTC6803-1 cannot have a series resistance to V–, additional Schottky diodes are needed to prevent ESD-induced reverse-supply (substrate) currents to flow.
CELLGROUP+ BLM31PG330SN1L CMHZ5265B CELLGROUP– BAT46W 100 V+ 100nF V–
680313 F23
+ + + +
BATTERY STACK LTC6803-1
+ + + +
C1
BATTERY STACK
LTC6803-3
C1 C0
R ISUPPLY
R ISUPPLY
V
–
V–
680313 F24
Figure 24. Kelvin Connection on C0 Improving Bottom Cell Voltage Measurement Accuracy
HARDWARE SHUTDOWN To completely shut down the LTC6803 a PMOS switch can be connected to V+, or V+ can be driven from an isolated power supply. Figure 25 shows an example of a switched V+. The breakdown voltage of DZ4 is about 1.8V. If SHDN < 1.8V, no current will flow through the stacked MMBTA42s and the 1M resistors. TP0610Ks will be completely shut off. If SHDN > 2.5V, M7 will be turned on and all TP0610Ks will be turned on. Figure 26 is an example of isolated power supply. This circuit provides power for two LTC6803s used to monitor 24 series connected battery cells. When 5V is removed, the LTC6803s will draw 1nA from the battery cells. Note that use of an external V+ supply will not protect daisy-chain SPI operation at low total stack potentials (below 5V). PCB LAYOUT CONSIDERATIONS The VREG and VREF pins should be bypassed with a 1µF capacitor for best performance. The LTC6803 is capable of operation with as much as 55V between V+ and V–. Care should be taken on the PCB layout to maintain physical separation of traces at different potentials. The pinout of
LTC6803-1 Configuration
CELLGROUP+ BLM31PG330SN1L CMHZ5265B CELLGROUP– 100 V+ 100nF V–
100
LTC6803-3 Configuration
Figure 23. Supply Decoupling
ADVANTAGES OF KELVIN CONNECTION ON C0 The V– trace resistance can cause an observable voltage drop between the negative end of the bottom battery cell and V– pin of LTC6803. This voltage drop will add to the measurement error of the bottom cell voltage for LTC6803-1. The LTC6803-3 separates C0 from V–, allowing Kelvin connection on C0 as shown in Figure 24. Any voltage drop on V– trace will not affect the bottom cell voltage measurement. The Kelvin connection will also allow RC filtering on V– as shown in Figure 23.
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LTC6803-1/LTC6803-3 APPLICATIONS INFORMATION
V+ C12 LTC6803-3 IC #3 C0 V
–
TP0610K
DZ1 15V
1M
+ + +
D1
V+ C12 LTC6803-3 IC #2 C0 V–
TP0610K
DZ2 15V
1M
+ + +
D2
V+ C12 LTC6803-3 IC #1 C0 V–
TP0610K
DZ3 15V
1M SHDN DZ4 1.8V 50k
+ + +
DZ1, DZ2, DZ3: MMSZ5245B DZ4: MMSZ4678T1 ALL NPN: MMBTA42 ALL PN: RS07J
680313 F25
Figure 25. Hardware Shutdown Circuit Reduces Total Supply Current of LTC6803 to Less Than 1nA
INPUT 5V 90mA TYP 1 LTC1693-2 8 VCC1 IN1 2 7 GND1 OUT1 3 6 IN2 VCC2 4 5 GND2 OUT2 2 3 6 7 33.2k GND 1µF 8 16 15 14
1µF
1µF
1µF
1µF 100k BAT54S IMC1210ER 1µF 100V EACH OUTPUT 61V TYP +V1 CMHZ5265B COM1
BAT54S
BAT54S
BAT54S
5V 10k 10µF
1µF 1µF 1µF
1µF 1µF
1µF 1µF
1µF
11 10 9 1µF 1µF 1µF 1µF BAT54S BAT54S BAT54S 100k BAT54S IMC1210ER 1µF 100V
220pF
1
+V2 CMHZ5265B
680313 F26
EPF8119S
COM2
Figure 26. LTC6803 Powered by Isolated Power Supplies
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36
LTC6803-1/LTC6803-3 APPLICATIONS INFORMATION
the LTC6803-1 and LTC6803-3 were chosen to facilitate this physical separation. There is no more than 5.5V between any two adjacent pins. The package body is used to separate the highest voltage (e. g., 43.2V) from the lowest voltage (0V). As an example, Figure 27 shows the DC voltage on each pin with respect to V– when twelve 3.6V battery cells are connected to the LTC6803-3. ADVANTAGES OF DELTA-SIGMA ADCS The LTC6803 employs a delta-sigma analog-to-digital converter for voltage measurement. The architecture of delta sigma converters can vary considerably, but the common characteristic is that the input is sampled many times over the course of a conversion and then filtered or averaged to produce the digital output code. In contrast, a SAR converter takes a single snapshot of the input voltage and then performs the conversion on this single sample. For measurements in a noisy environment, a delta sigma converter provides distinct advantages over a SAR converter. While SAR converters can have high sample rates, the fullpower bandwidth of a SAR converter is often greater than 1MHz, which means the converter is sensitive to noise out to this frequency. And many SAR converters have much higher bandwidths—up to 50MHz and beyond. It is possible to filter the input, but if the converter is multiplexed to measure several input channels a separate filter will be required for each channel. A low frequency filter cannot reside between a multiplexer and an ADC and achieve a high scan rate across multiple channels. Another consequence of filtering a SAR ADC is that any noise reduction gained by filtering the input cancels the benefit of having a high sample rate in the first place, since the filter will take many conversion cycles to settle. For a given sample rate, a delta-sigma converter can achieve excellent noise rejection while settling completely in a single conversion—something that a filtered SAR converter cannot do. Noise rejection is particularly important in high voltage switching controllers, where switching noise will invariably be present in the measured voltage.
42.5V 42.5V 42.5V 43.2V 43.2V 43.2V 39.6V 39.6V 36V 36V 32.4V 32.4V 28.8V 28.8V 25.2V 25.2V 21.6 21.6 18V 18V 14.4V 14.4V
CSBI CSBO SDO SDOI SDI SCKO SCKI V+ VMODE C12 GPIO2 S12 GPIO1 C11 WDTB S11 C10 LTC6803-3 TOS VREG S10 VREF C9 VTEMP2 S9 VTEMP1 C8 NC S8 V– C7 C0 S7 S1 C6 C1 S6 S2 C5 C2 S5 S3 C4 C3 S4
680313 F27
0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 5V 3.1V 1.5V 1.5V 0V 0V 0V 3.6V 3.6V 7.2V 7.2V 10.8V 10.8V
Figure 27. Typical Pin Voltages for Twelve 3.6V Cells
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LTC6803-1/LTC6803-3 APPLICATIONS INFORMATION
Other advantages of delta-sigma converters are that they are inherently monotonic, meaning they have no missing codes, and they have excellent DC specifications. Converter Details The LTC6803’s ADC has a second order delta-sigma modulator followed by a SINC2, finite impulse response (FIR) digital filter. The front-end sample rate is 512ksps, which greatly reduces input filtering requirements. A simple 16kHz, 1-pole filter composed of a 100Ω resistor and a 0.1µF capacitor at each input will provide adequate filtering for most applications. These component values will not degrade the DC accuracy of the ADC. Each conversion consists of two phases—an autozero phase and a measurement phase. The ADC is autozeroed at each conversion, greatly improving CMRR. The second half of the conversion is the actual measurement. Noise Rejection Figure 28 shows the frequency response of the ADC. The roll-off follows a SINC2 response, with the first notch at 4kHz. Also shown is the response of a 1-pole, 850Hz filter (187µs time constant) which has the same integrated
10 0 –10 –20 –30 –40 –50 –60
response to wideband noise as the LTC6803’s ADC, which is about 1350Hz. This means that if wideband noise is applied to the LTC6803 input, the increase in noise seen at the digital output will be the same as an ADC with a wide bandwidth (such as a SAR) preceded by a perfect 1350Hz brick wall lowpass filter. Thus if an analog filter is placed in front of a SAR converter to achieve the same noise rejection as the LTC6803 ADC, the SAR will have a slower response to input signals. For example, a step input applied to the input of the 850Hz filter will take 1.55ms to settle to 12 bits of precision, while the LTC6803 ADC settles in a single 1ms conversion cycle. This also means that very high sample rates do not provide any additional information because the analog filter limits the frequency response. While higher order active filters may provide some improvement, their complexity makes them impractical for high channel count measurements as a single filter would be required for each input. Also note that the SINC2 response has a 2nd order rolloff envelope, providing an additional benefit over a single pole analog filter.
FILTER GAIN (dB)
10
100
1k 10k FREQUENCY (Hz)
100k
680313 F28
Figure 28. Noise Filtering of the LTC6803 ADC
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38
LTC6803-1/LTC6803-3 PACKAGE DESCRIPTION
(Reference LTC DWG # 05-08-1754 Rev Ø)
G Package 44-Lead Plastic SSOP (5.3mm)
12.50 – 13.10* (.492 – .516) 1.25 ±0.12 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20 (.291 – .323)
0.25 ±0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 – 5.60* (.197 – .221)
0.50 BSC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
1.65 – 1.85 (.065 – .073)
0° – 8°
2.0 (.079) MAX
PARTING LINE 0.10 – 0.25 (.004 – .010) 0.55 – 0.95** (.022 – .037) 1.25 (.0492) REF
0.50 (.01968) BSC
SEATING PLANE
0.20 – 0.30† (.008 – .012) TYP
0.05 (.002) MIN
G44 SSOP 0607 REV Ø
NOTE: 1.DRAWING IS NOT A JEDEC OUTLINE 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSIONS ARE IN
MILLIMETERS (INCHES)
4. DRAWING NOT TO SCALE 5. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.08mm AT SEATING PLANE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS, BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH SHALL NOT EXCEED .15mm PER SIDE **LENGTH OF LEAD FOR SOLDERRING TO A SUBSTRATE †THE MAXIMUM DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSIONS DO NOT EXCEED 0.13mm PER SIDE
680313f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
39
LTC6803-1/LTC6803-3 TYPICAL APPLICATION
Cascadable 12-Cell Li-Ion Battery Monitor
CASCADED SPI PORT TO NEXT LTC6803-1 CELL12 IMC1210ER100K MM5Z5265B BAT46W BAT46W 100 100 20 100 1M 1M 1M CSBI SDO* MAIN SPI PORT TO HOST µP OR SDI NEXT LTC6803-1 SCKI CSBI SDI SCKI RSO7J 100 RSO7J 20 RSO7J 100
1 2 100 3 4 C12FILTER DC12 C11FILTER DC11 C10FILTER DC10 C9FILTER DC9 C8FILTER DC8 C7FILTER DC7 C6FILTER DC6 C5FILTER DC5 C4FILTER DC4 C3FILTER DC3 CELL2 RQJ0503PGDQALT 100 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
CSBO SDOI SCKO V+ C12 S12 C11 S11 C10 LTC6803-3 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4
CSBI SDO SDI SCKI VMODE GPIO2 GPIO1 WDTB NC TOS VREG VREF VTEMP2 VTEMP1 NC V– S1 C1 S2 C2 S3 C3
44 43 42 41 40 39 1M 38 37 1M 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1µF 1µF 1M
100nF
*REQUIRES 1k PULL-UP RESISTOR AT HOST DEVICE (SIGNAL NOT USED FOR INTER-IC COMMUNCATION)
REPEAT INPUT CIRCUITS FOR CELL3 TO CELL12
10k 3
NTC2 100 10nF
+ – + –
8
1
2
1/2 LT6004 4
5
8 7 10k 100 10nF
680313 TA02
C2FILTER 100nF PDZ7.5B
6
1/2 LT6004 4
NTC1
33 CELL1
475 RQJ0503PGDQALT
3.3k 100 100nF PDZ7.5B
DC2 C1FILTER
33
475
3.3k
DC1
RELATED PARTS
PART NUMBER DESCRIPTION LTC6801 LTC6802-1 LTC6802-2 LTC6803-2/ LTC6803-4 Independent Multicell Battery Stack Fault Monitor Multicell Battery Stack Monitor with Parallel Addressed Serial Interface Multicell Battery Stack Monitor with an Individually Addressable Serial Interface Multicell Battery Stack Monitor with an Individually Addressable Serial Interface COMMENTS Monitors Up to 12 Series-Connected Battery Cells for Undervoltage or Overvoltage. Companion to LTC6802 and LTC6803 Family Functionally Equivalent to the LTC6803-1 and LTC6803-3, Pin Compatible with the LTC6803-1 Functionally Equivalent to LTC6803-2/LTC6803-4, Pin Compatible with the LTC6803-2 Functionality Equivalent to LTC6803-1/LTC6803-3, Allows for Parallel Communication Battery Stack Topologies
680313f LT 0211 • PRINTED IN USA
40 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
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