LTC691

LTC690/LTC691 LTC694/LTC695 Microprocessor Supervisory Circuits FEATURES n n n n n n n n n n n n DESCRIPTION The LTC®690 family provides complete power supply monitoring and battery control functions for microprocessor reset, battery back-up, CMOS RAM write protection, power failure warning and watchdog timing. A precise internal voltage reference and comparator circuit monitor the power supply line. When an out-of-tolerance condition occurs, the reset outputs are forced to active states and the chip enable output unconditionally write-protects external memory. In addition, the RESET output is guaranteed to remain logic low even with VCC as low as 1V. The LTC690 family powers the active CMOS RAMs with a charge pumped NMOS power switch to achieve low dropout and low supply current. When primary power is lost, auxiliary power, connected to the battery input pin, powers the RAMs in standby through an efficient PMOS switch. For an early warning of impending power failure, the LTC690 family provides an internal comparator with a user-defined threshold. An internal watchdog timer is also available, which forces the reset pins to active states when the watchdog input is not toggled prior to a preset timeout period. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Guaranteed Reset Assertion at VCC = 1V 1.5mA Maximum Supply Current Fast (35ns Max) Onboard Gating of RAM Chip Enable Signals SO-8 and S16 Packaging 4.65V Precision Voltage Monitor Power OK/Reset Time Delay: 50ms, 200ms or Adjustable Minimum External Component Count 1µA Maximum Standby Current Voltage Monitor for Power-Fail or Low-Battery Warning Thermal Limiting Performance Specified Over Temperature Superior Upgrade for MAX690 Family APPLICATIONS n n n n Critical μP Power Monitoring Intelligent Instruments Battery-Powered Computers and Controllers Automotive Systems TYPICAL APPLICATION RESET Output Voltage vs Supply Voltage 5 VIN ≥ 7.5V LT 1086-5 VIN 10μF ADJ VOUT ® 5V + + 100μF VOUT 0.1μF LTC690/LTC691 LTC694/LTC695 VBATT RESET PFO PFI GND WDI μP SYSTEM μP RESET μP NMI I/O LINE 690 TA01 RESET OUTPUT VOLTAGE (V) VCC POWER TO μP 0.1μF CMOS RAM POWER 4 3 TA = 25°C EXTERNAL PULL-UP = 10μA VBATT = 0V 3V 51k 2 1 10k MICROPROCESSOR RESET, BATTERY BACK-UP, POWER FAILURE WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP FOR MICROPROCESSOR SYSTEMS 0.1μF 100Ω 0 0 1 3 4 2 SUPPLY VOLTAGE (V) 5 690 TA02 690fe 1 LTC690/LTC691 LTC694/LTC695 ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2) Terminal Voltage VCC ..................................................... – 0.3V to 6.0V VBATT .................................................. –0.3V to 6.0V All Other Inputs ....................– 0.3V to (VOUT + 0.3V) Input Current VCC ................................................................200mA VBATT ...............................................................50mA GND.................................................................20mA VOUT Output Current ...................Short-Circuit Protected Power Dissipation ...............................................500mW Operating Temperature Range LTC690/91/94/95C ............................... 0°C to 70°C LTC690/91/94/95I ............................– 40°C to 85°C Storage Temperature Range .................. –65°C to 150°C Lead Temperature (Soldering, 10 sec.) ................. 300°C PIN CONFIGURATION TOP VIEW VBATT VOUT VCC GND BATT ON LOW⎯ LINE OSC IN OSC SEL 1 2 3 4 5 6 7 8 N PACKAGE 16-LEAD PDIP TJMAX = 110°C, θJA = 130°C/W TOP VIEW VOUT VCC GND 1 2 3 8 7 6 5 N8 PACKAGE 8-LEAD PDIP TJMAX = 110°C, θJA = 130°C/W (N8) VBATT RESET WDI PFO VOUT VCC GND PFI 1 2 3 4 16 RESET 15 RESET 14 WDO 13 CE IN 12 CE OUT VBATT 1 VOUT 2 VCC 3 GND 4 BATT ON 5 LOW⎯ LINE 6 OSC IN 7 OSC SEL 8 TOP VIEW 16 RESET 15 RESET 14 WDO 13 CE IN 12 CE OUT 11 WDI 10 PFO 9 PFI 11 WDI 10 PFO 9 PFI SW PACKAGE 16-LEAD WIDE PLASTIC SO TJMAX = 110°C, θJA = 130°C/W CONDITIONS: PCB MOUNT ON FR4 MATERIAL, STILL AIR AT 25°C, COPPER TRACE TOP VIEW 8 7 6 5 VBATT RESET WDI PFO PFI 4 S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 110°C, θJA = 180°C/W CONDITIONS; PCB MOUNT ON FR4 MATERIAL, STILL AIR AT 25°C, COPPER TRACE 690fe 2 LTC690/LTC691 LTC694/LTC695 ORDER INFORMATION LEAD FREE FINISH LTC691CN#PBF LTC691IN#PBF LTC695CN#PBF LTC695IN#PBF LTC691CSW#PBF LTC691ISW#PBF LTC695CSW#PBF LTC695ISW#PBF LTC690CN8#PBF LTC690IN8#PBF LTC694CN8#PBF LTC694IN8#PBF LTC690CS8#PBF LTC690IS8#PBF LTC694CS8#PBF LTC694IS8#PBF TAPE AND REEL LTC691CN#PBF LTC691IN#PBF LTC695CN#PBF LTC695IN#PBF LTC691CSW#PBF LTC691ISW#PBF LTC695CSW#PBF LTC695ISW#PBF LTC690CN8#PBF LTC690IN8#PBF LTC694CN8#PBF LTC694IN8#PBF LTC690CS8#PBF LTC690IS8#PBF LTC694CS8#PBF LTC694IS8#PBF PART MARKING LTC691CN LTC691IN LTC695CN LTC695IN LTC691CSW LTC691ISW LTC695CSW LTC695ISW LTC690CN8 LTC690IN8 LTC694CN8 LTC694IN8 LTC690CS8 LTC690IS8 LTC694CS8 LTC694IS8 PACKAGE DESCRIPTION 16-Lead PDIP 16-Lead PDIP 16-Lead PDIP 16-Lead PDIP 16-Lead Wide Plastic SO 16-Lead Wide Plastic SO 16-Lead Wide Plastic SO 16-Lead Wide Plastic SO 8-Lead PDIP 8-Lead PDIP 8-Lead PDIP 8-Lead PDIP 8-Lead Plastic SO 8-Lead Plastic SO 8-Lead Plastic SO 8-Lead Plastic SO TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ PRODUCT SELECTION GUIDE PINS LTC690 LTC691 LTC694 LTC695 LTC699 LTC1232 LTC1235 8 16 8 16 8 8 16 RESET X X X X X X X WATCHDOG TIMER X X X X X X X X X X X X X BATTERY BACK-UP X X X X POWER-FAIL WARNING X X X X X X RAM WRITE PROTECT PUSHBUTTON RESET CONDITIONAL BATTERY BACK-UP 690fe 3 LTC690/LTC691 LTC694/LTC695 ELECTRICAL CHARACTERISTICS PARAMETER Battery Back-Up Switching Operating Voltage Range VOUT Output Voltage VCC VBATT IOUT = 1mA IOUT = 50mA VOUT in Battery Back-Up Mode Supply Current (Exclude IOUT) Supply Current in Battery Back-Up Mode Battery Standby Current (+ = Discharge, – = Charge) Battery Switchover Threshold, VCC – VBATT Battery Switchover Hysteresis BATT ON Output Voltage (Note 4) BATT ON Output Short-Circuit Current (Note 4) Reset and Watchdog Timer Reset Voltage Threshold Reset Threshold Hysteresis Reset Active Time (LTC690/91) (Note 5) Reset Active Time (LTC694/95) (Note 5) Watchdog Timeout Period, Internal Oscillator OSC SEL HIGH, VCC = 5V OSC SEL HIGH, VCC = 5V Long Period, VCC = 5V Short Period, VCC = 5V Watchdog Timeout Period, External Clock (Note 6) Reset Active Time PSRR Watchdog Timeout Period PSRR, Internal OSC Minimum WDI Input Pulse Width RESET Output Voltage at VCC = 1V RESET and LOW⎯LINE Output Voltage (Note 4) RESET and WDO Output Voltage (Note 4) VIL = 0.4V, VIH = 3.5V ISINK = 10μA, VCC = 1V ISINK = 1.6mA, VCC = 4.25V ISOURCE = 1μA, VCC = 5V ISINK = 1.6mA, VCC = 5V ISOURCE = 1μA, VCC = 4.25V 3.5 0.4 3.5 l l l l l l l The l denotes specifications which apply over the operating temperature range, otherwise specifications are at TA = 25°C. VCC = full operating range, VBATT = 2.8V, unless otherwise noted. CONDITIONS MIN 4.75 2.00 VCC – 0.05 VCC – 0.005 VCC – 0.10 VCC – 0.005 VCC – 0.50 VCC – 0.250 VBATT – 0.1 VBATT – 0.2 l l l TYP MAX 5.50 4.25 UNITS V V V V V V IOUT = 250μA, VCC < VBATT IOUT = 50mA VCC = 0V, VBATT = 2.8V 5.5 > VCC > VBATT + 0.2V Power Up Power Down ISINK = 3.2mA BATT ON = VOUT Sink Current BATT ON = 0V Source Current 0.6 0.6 0.04 0.04 –0.1 –0.1 70 50 20 1.5 2.5 1 5 +0.02 +0.10 mA mA μA μA μA μA mV mV mV 0.4 35 0.5 4.5 40 35 160 140 1.2 1 80 70 4032 960 1 1 200 4 200 0.4 1 4.65 40 50 50 200 200 1.6 1.6 100 100 60 70 240 280 2.00 2.25 120 140 4097 1025 25 4.75 V m μA V mV ms ms ms ms sec sec ms ms Clock Cycles ms/V ms/V ns mV V V V V Long Period Short Period 690fe 4 LTC690/LTC691 LTC694/LTC695 ELECTRICAL CHARACTERISTICS PARAMETER RESET, RESET, WDO, LOW⎯ LINE Output Short-Circuit Current (Note 4) WDI Input Threshold WDI Input Current Power-Fail Detector PFI Input Threshold PFI Input Threshold PSRR PFI Input Current PFO Output Voltage (Note 4) PFO Short-Circuit Source Current (Note 4) PFI Comparator Response Time (Falling) PFI Comparator Response Time (Rising) (Note 4) Chip Enable Gating CE IN Threshold CE IN Pull-Up Current (Note 7) CE OUT Output Voltage ISINK = 3.2mA ISOURCE = 3.0mA ISOURCE = 1μA, VCC = 0V VCC = 5V, CL = 20pF Output Source Current Output Sink Current l The l denotes specifications which apply over the operating temperature range, otherwise specifications are at TA = 25°C. VCC = full operating range, VBATT = 2.8V, unless otherwise noted. CONDITIONS Output Source Current Output Sink Current Logic Low Logic high WDI = VOUT WDI = 0V VCC = 5V l l l MIN 1 TYP 3 25 MAX 25 0.8 UNITS μA mA V μA 3.5 –50 1.25 4 –8 1.3 0.3 ±0.01 ±25 0.4 3.5 1 3 25 2 40 8 0.8 2 3 0.4 VOUT – 1.50 VOUT – 0.05 20 20 30 35 ±2 5 35 45 ns mA μA V 25 μA mA μs μs 50 1.35 V mV/V nA V ISINK = 3.2mA ISOURCE = 1μA PFI = HIGH, PFO = 0V PFI = LOW, PFO = VOUT ΔVIN = –20mV, VOD = 15mV ΔVIN = 20mV, VOD = 15mV with 10kΩ Pull-Up VIL VIH V CE Propagation Delay CE OUT Output Short-Circuit Current Oscillator OSC IN Input Current (Note 7) OSC SEL Input Pull-Up Current (Note 7) OSC IN Frequency Range OSC IN Frequency with External Capacitor μA μA 250 kHz kHz OSC SEL = 0V OSC SEL = 0V, COSC = 47pF l 0 4 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: For military temperature range parts or for the LTC692 and LTC693, consult the factory. Note 4: The output pins of BATT ON, LOW⎯LINE, PFO, WDO, RESET and RESET have weak internal pull-ups of typically 3μA. However, external pullup resistors may be used when higher speed is required. Note 5: The LTC690 and LTC691 have minimum reset active time of 35ms (50ms typically) while the LTC694 and LTC695 have longer minimum reset active time of 140ms (200ms typically). The reset active time of the LTC691 and LTC695 can be adjusted (see Table 2 in Applications Information section). Note 6: The external clock feeding into the circuit passes through the oscillator before clocking the watchdog timer (See Block Diagram). Variation in the timeout period is caused by phase errors which occur when the oscillator divides the external clock by 64. The resulting variation in the timeout period is 64 clocks plus one clock of jitter. Note 7: The input pins of CE IN, OSC IN and OSC SEL have weak internal pullups which pull to the supply when the input pins are floating. 690fe 5 LTC690/LTC691 LTC694/LTC695 BLOCK DIAGRAM VBATT VCC M2 M1 VOUT CHARGE PUMP – + C2 BATT ON LOW⎯LINE + C1 – 1.3V CE OUT CE IN GND – C3 PFI OSC IN OSC OSC SEL + PFO RESET RESET PULSE GENERATOR RESET WDO 690 BD WDI TRANSITION DETECTOR WATCHDOG TIMER PIN FUNCTIONS VCC: 5V Supply Input. The VCC pin should be bypassed with a 0.1μF capacitor. VOUT: Voltage Output for Backed Up Memory. Bypass with a capacitor of 0.1μF or greater. During normal operation, VOUT obtains power from VCC through an NMOS power switch, M1, which can deliver up to 50mA and has a typical on resistance of 5Ω. When VCC is lower than VBATT, VOUT is internally switched to VBATT. If VOUT and VBATT are not used, connect VOUT to VCC. VBATT: Back-Up Battery Input. When VCC falls below VBATT, auxiliary power, connected to VBATT, is delivered to VOUT through PMOS switch, M2. If back-up battery or auxiliary power is not used, VBATT should be connected to GND. GND: Ground pin. BATT ON: Battery On Logic Output from Comparator C2. BATT ON goes low when VOUT is internally connected to VCC. The output typically sinks 35mA and can provide base drive for an external PNP transistor to increase the output current above the 50mA rating of VOUT. BATT ON goes high when VOUT is internally switched to VBATT. PFI: Power Failure Input. PFI is the noninverting input to the power-fail comparator, C3. The inverting input is internally connected to a 1.3V reference. The power failure output remains high when PFI is above 1.3V and goes low when PFI is below 1.3V. Connect PFI to GND or VOUT when C3 is not used. 690fe 6 LTC690/LTC691 LTC694/LTC695 PIN FUNCTIONS PFO: Power Failure Output from C3. PFO remains high when PFI is above 1.3V and goes low when PFI is below 1.3V. When VCC is lower than VBATT, C3 is shut down and PFO is forced low. RESET: Logic Output for μP Reset Control. Whenever VCC falls below either the reset voltage threshold (4.65V, typically) or VBATT, RESET goes active low. After VCC returns to 5V, reset pulse generator forces RESET to remain active low for a minimum of 35ms for the LTC690 /LTC691 (140ms for the LTC694/LTC695). When the watchdog timer is enabled but not serviced prior to a preset timeout period, reset pulse generator also forces RESET to active low for a minimum of 35ms for the LTC690/LTC691 (140ms for the LTC694/5) for every preset timeout period (see Figure 11). The reset active time is adjustable on the LTC691/LTC695. An external pushbutton reset can be used in connection with the RESET output. See Pushbutton Reset in Applications Information section. RESET: RESET is an active high logic ouput. It is the inverse of RESET. LOW LINE : Logic Output from Comparator C1. LOW⎯LINE indicates a low line condition at the VCC input. When VCC falls below the reset voltage threshold (4.65V typically), LOW⎯LINE goes low. As soon as VCC rises above the reset voltage threshold, LOW⎯LINE returns high (see Figure 1). LOW⎯LINE goes low when VCC drops below VBATT (see Table 1). WDI: Watchdog Input, WDI, is a three level input. Driving WDI either high or low for longer than the watchdog timeout period, forces both RESET and WDO low. Floating WDI disables the watchdog timer. The timer resets itself with each transition of the watchdog input (see Figure 11). WDO: Watchdog Logic Output. When the watchdog input remains either high or low for longer than the watchdog timeout period, WDO goes low. WDO is set high whenever there is a transition on the WDI pin, or LOW⎯LINE goes low. The watchdog timer can be disabled by floating WDI (see Figure 11). CE IN: Logic input to the Chip⎯Enable gating circuit. CE IN can be derived from microprocessor’s address line and/or decoder output. See Applications Information section and Figure 5 for additional information. CE OUT: Logic Output on the Chip⎯Enable Gating Circuit. When VCC is above the reset voltage threshold, CE OUT is a buffered replica of CE IN. When VCC is below the reset voltage threshold CE OUT is forced high (see Figure 5). OSC SEL: Oscillator Selection Input. When OSC SEL is high or floating, the internal oscillator sets the reset active time and watchdog timeout period. Forcing OSC SEL low, allows OSC IN be driven from an external clock signal or external capacitor be connected between OSC IN and GND. OSC IN: Oscillator Input. OSC IN can be driven by an external clock signal or external capacitor can be connected between OSC IN and GND when OSC SEL is forced low. In this configuration the nominal reset active time and watchdog timeout period are determined by the number of clocks or set by the formula (see Applications Information section). When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is fixed at 50ms typical for the LTC691 and 200ms typical for the LTC695. OSC IN selects between the 1.6 seconds and 100ms typical watchdog timeout periods. In both cases, the timeout period immediately after a reset is 1.6 seconds typical. 690fe 7 LTC690/LTC691 LTC694/LTC695 TYPICAL PERFORMANCE CHARACTERISTICS VOUT vs IOUT 5.00 VCC = 5V VBATT = 2.8V TA = 25°C OUTPUT VOLTAGE (V) 2.80 VCC = 0V VBATT = 2.8V TA = 25°C 2.78 SLOPE = 125Ω 2.76 VOUT vs IOUT 1.308 1.306 PFI INPUT THRESHOLD (V) 1.304 1.302 1.300 1.298 1.296 Power Failure Input Threshold vs Temperature VCC = 5V 4.95 OUTPUT VOLTAGE (V) 4.90 SLOPE = 5Ω 4.85 2.74 4.80 4.75 0 10 30 40 20 LOAD CURRENT (mA) 50 690 G01 2.72 0 100 300 400 200 LOAD CURRENT (μA) 500 690 G02 1.294 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 690 G03 Reset Active Time vs Temperature LTC690-1 58 VCC = 5V 56 RESET ACTIVE TIME 54 52 50 48 46 –50 –25 RESET ACTIVE TIME 224 216 208 200 192 232 Reset Active Time vs Temperature LTC694-5 4.66 VCC = 5V RESET VOLTAGE THRESHOLD (V) 4.65 4.64 4.63 4.62 4.61 Reset Voltage Threshold vs Temperature 50 25 75 0 TEMPERATURE (°C) 100 125 690 G04 184 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 690 G05 4.60 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 690 G06 Power-Fail Comparator Response Time PFO OUTPUT VOLTAGE (V) PFO OUTPUT VOLTAGE (V) 6 5 4 3 2 1 0 VPFI 1.3V + PFO – 30pF Power-Fail Comparator Response Time VCC = 5V TA = 25°C 5 4 3 2 1 0 VPFI 1.3V + PFO – Power-Fail Comparator Response Time with Pull-Up Resistor PFO OUTPUT VOLTAGE (V) 6 5 4 3 2 1 0 5V VPFI 1.3V + – PFO 10k 30pF 6 VCC = 5V TA = 25°C VCC = 5V TA = 25˚C 30pF 1.305V 1.285V 0 1 VPFI = 20mV STEP 1.315V 1.295V 6 7 8 690 G07 VPFI = 20mV STEP 1.315V 1.295V 0 2 VPFI = 20mV STEP 2 345 TIME (μs) 0 20 40 60 80 100 120 140 160 180 TIME (μs) 690 G08 4 6 8 10 12 14 16 18 TIME (μs) 690 G09 690fe 8 LTC690/LTC691 LTC694/LTC695 APPLICATIONS INFORMATION Microprocessor Reset The LTC690 family uses a bandgap voltage reference and a precision voltage comparator C1 to monitor the 5V supply input on VCC (see Block Diagram). When VCC falls below the reset voltage threshold, the RESET output is forced to active low state. The reset voltage threshold accounts for a 5% variation on VCC, so the RESET output becomes active low when VCC falls below 4.75V (4.65V typical). On power-up, the RESET signal is held active low for a minimum of 35ms for the LTC690/LTC691 (140ms for the LTC694/LTC695) after reset voltage threshold is reached to allow the power supply and microprocessor to stabilize. The reset active time is adjustable on the LTC691/LTC695. On power-down, the RESET signal remains active low even with VCC as low as 1V. This capability helps hold the microprocessor in stable shutdown condition. Figure 1 shows the timing diagram of the RESET signal. The precision voltage comparator, C1, typically has 40mV of hysteresis which ensures that glitches at VCC pin do not activate the RESET output. Response time is typically 10μs. To help prevent mistriggering due to transient loads, VCC pin should be bypassed with a 0.1μF capacitor with the leads trimmed as short as possible. The LTC691 and LTC695 have two additional outputs: RESET and LOW⎯LINE . RESET is an active high output and is the inverse of RESET. LOW⎯LINE is the output of the precision voltage comparator C1. When VCC falls V2 VCC V1 below the reset voltage threshold, LOW⎯LINE goes low. LOW⎯LINE returns high as soon as VCC rises above the reset voltage threshold. Battery Switchover The battery switchover circuit compares VCC to the VBATT input, and connects VOUT to whichever is higher. When VCC rises to 70mV above VBATT, the battery switchover comparator, C2, connects VOUT to VCC through a charge pumped NMOS power switch, M1. When VCC falls to 50mV above VBATT, C2 connects VOUT to VBATT through a PMOS switch, M2. C2 has typically 20mV of hysteresis to prevent spurious switching when VCC remains nearly equal to VBATT. The response time of C2 is approximately 20μs. During normal operation, the LTC690 family uses a charge pumped NMOS power switch to achieve low dropout and low supply current. This power switch can deliver up to 50mA to VOUT from VCC and has a typical on resistance of 5Ω. The VOUT pin should be bypassed with a capacitor of 0.1μF or greater to ensure stability. Use of a larger bypass capacitor is advantageous for supplying current to heavy transient loads. When operating currents larger than 50mA are required from VOUT, or a lower dropout (VCC-VOUT voltage differential) is desired, the LTC691 and LTC695 should be used. These products provide BATT ON output to drive the base of V2 V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS V1 RESET t1 t1 t1 = RESET ACTIVE TIME LOW LINE 690 F01 Figure 1. Reset Active Time 690fe 9 LTC690/LTC691 LTC694/LTC695 APPLICATIONS INFORMATION external PNP transistor (Figure 2). If higher currents are needed with the LTC690 and LTC694, a high current Schottky diode can be connected from the VCC pin to the VOUT pin to supply the extra current. ANY PNP POWER TRANSISTOR farad-size double layer capacitors, can be used for short term memory back-up instead of a battery. The charging resistor for both capacitors and rechargeable batteries should be connected to VOUT since this eliminates the discharge path that exists when the resistor is connected to VCC (Figure 3). I= VOUT – VBATT R R 5V 0.1μF VCC VOUT 0.1μF 5 5V 0.1μF 1 3V BATT ON 3 2 VOUT VCC LTC691 LTC695 VBATT GND 4 690 F02 0.1μF LTC690 LTC691 LTC694 LTC695 3V VBATT GND Figure 2. Using BATT ON to Drive External PNP Transistor The LTC690 family is protected for safe area operation with short-circuit limit. Output current is limited to approximately 200mA. If the device is overloaded for long period of time, thermal shutdown turns the power switch off until the device cools down. The threshhold temperature for thermal shutdown is approximately 155°C with about 10°C of hysteresis which prevents the device from oscillating in and out of shutdown. The PNP switch used in competitive devices was not chosen for the internal power switch because it injects unwanted current into the substrate. This current is collected by the VBATT pin in competitive devices and adds to the charging current of the battery which can damage lithium batteries. The LTC690 family uses a charge pumped NMOS power switch to eliminate unwanted charging current while achieving low dropout and low supply current. Since no current goes to the substrate, the current collected by VBATT pin is strictly junction leakage. A 125Ω PMOS switch connects the VBATT input to VOUT in battery back-up mode. The switch is designed for very low dropout voltage (input-to-output differential). This feature is advantageous for low current applications such as battery back-up in CMOS RAM and other low power CMOS circuitry. The supply current in battery back-up mode is 1μA maximum. The operating voltage at the VBATT pin ranges from 2.0V to 4.25V. High value capacitors, such as electrolytic or 690 F03 Figure 3. Charging External Battery Through VOUT Replacing the Back-Up Battery When changing the back-up battery with system power on, spurious resets can occur while battery is removed due to battery standby current. Although battery standby current is only a tiny leakage current, it can still charge up the stray capacitance on the VBATT pin. The oscillation cycle is as follows: When VBATT reaches within 50mV of VCC, the LTC690 switches to battery back-up. VOUT pulls VBATT low and the device goes back to normal operation. The leakage current then charges up the VBATT pin again and the cycle repeats. If spurious resets during battery replacement pose no problems, then no action is required. Otherwise, a resistor from VBATT to GND will hold the pin low while changing the battery. For example, the battery standby current is 1μA maximum over temperature and the external resistor required to hold VBATT below VCC is: R≤ VCC –50mV 1 μA With VCC = 4.5V, a 4.3M resistor will work. With a 3V battery, this resistor will draw only 0.7μA from the battery, which is negligible in most cases. 690fe 10 LTC690/LTC691 LTC694/LTC695 APPLICATIONS INFORMATION If battery connections are made through long wires, a 10Ω to 100Ω series resistor and a 0.1μF capacitor are recommended to prevent any overshoot beyond VCC due to the lead inductance (Figure 4). 10Ω VBATT 4.3M 0.1μF LTC690 LTC691 LTC694 LTC695 GND 690 F04 input of battery-backed up CMOS RAM. CE OUT can also be used to drive the Store or Write input of an EEPROM, EAROM or NOVRAM to achieve similar protection. Figure 5 shows the timing diagram of CE IN and CE OUT. CE IN can be derived from the microprocessor’s address decoder output. Figure 6 shows a typical nonvolatile CMOS RAM application. Memory protection can also be achieved with the LTC690 and LTC694 by using RESET as shown in Figure 7. Table 1. Input and Output Status in Battery Back-Up Mode SIGNAL VCC VOUT VBATT BATT ON PFI PFO RESET RESET WDI WDO CE IN CE OUT OSC IN OSC SEL STATUS C2 monitors VCC for active switchover. VOUT is connected to VBATT through an internal PMOS switch. The supply current is 1μA maximum. Logic high. The open-circuit output voltage is equal to VOUT . Power failure input is ignored. Logic low Logic low Logic high. The open-circuit output voltage is equal to VOUT. Watchdog input is ignored. Logic high. The open-circuit output voltage is equal to VOUT. Chip⎯Enable Input is ignored. Logic high. The open-circuit output voltage is equal to VOUT. OSC IN is ignored. OSC SEL is ignored. Figure 4. 10Ω/0.1μF Combination Eliminates Inductive Overshoot and Prevents Spurious Resets During Battery Replacement Table 1 shows the state of each pin during battery back-up. When the battery switchover section is not used, connect VBATT to GND and VOUT to VCC . Memory Protection The LTC691 and LTC695 include memory protection circuitry that ensures the integrity of the data in memory by preventing write operations when VCC is at invalid level. Two additional pins, CE IN and CE OUT, control the Chip Enable or Write inputs of CMOS RAM. When VCC is 5V, CE OUT follows CE IN with a typical propagation delay of 20ns. When VCC falls below the reset voltage threshold or VBATT, CE OUT is forced high, independent of CE IN. CE OUT is an alternative signal to drive the CE, CS, or Write VCC V2 V1 LOW⎯LINE Logic low V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS CE IN CE OUT VOUT = VBATT VOUT = VBATT 690 F05 Figure 5. Timing Diagram for CE IN and CE OUT 690fe 11 LTC690/LTC691 LTC694/LTC695 APPLICATIONS INFORMATION 5V 0.1μF VCC VOUT LTC691 LTC695 CE OUT VBATT 3V GND 20ns PROPAGATION DELAY CE IN RESET RESET TO μP 690 F06 + 10μF VCC 0.1μF 62512 RAM CS GND FROM DECODER Power-Fail Warning The LTC690 family generates a Power Failure Output (PFO) for early warning of failure in the microprocessor’s power supply. This is accomplished by comparing the Power Failure Input (PFI) with an internal 1.3V reference. PFO goes low when the voltage at the PFI pin is less than 1.3V. Typically PFI is driven by an external voltage divider (R1 and R2 in Figures 8 and 9) which senses either an unregulated DC input or a regulated 5V output. The voltage divider ratio can be chosen such that the voltage at the PFI pin falls below 1.3V several milliseconds before the 5V supply falls below the maximum reset voltage threshold 4.75V. PFO is normally used to interrupt the microprocessor to execute shutdown procedure between PFO and RESET or RESET. The power-fail comparator, C3, does not have hysteresis. Hysteresis can be added however, by connecting a resistor between the PFO output and the noninverting PFI input pin as shown in Figures 8 and 9. The upper and lower trip points in the comparator are established as follows: When PFO output is low, R3 sinks current from the summing junction at the PFI pin. ⎛ R1 R1⎞ VH = 1.3V ⎜ 1+ +⎟ ⎝ R2 R3 ⎠ When PFO output is high, the series combination of R3 and R4 source current into the PFI summing junction. ⎛ R1 (5V – 1.3V)R1⎞ VL = 1.3V ⎜ 1 + – ⎟ ⎝ R2 1.3V(R3 + R4)⎠ Assuming R4