Electrical Specifications Subject to Change
FEATURES
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LTC6992-1/-2/-3/-4 TimerBlox Voltage-Controlled Pulse Width Modulator (PWM) DESCRIPTION
The LTC®6992 is a silicon oscillator with an easy-to-use analog voltage-controlled pulse width modulation (PWM) capability. The LTC6992 is part of the TimerBlox™ family of versatile silicon timing devices. A single resistor, RSET, programs the LTC6992’s internal master oscillator frequency. The output frequency is determined by this master oscillator and an internal frequency divider, NDIV, programmable to eight settings from 1 to 16384. fOUT = 1MHz 50kΩ • , N = 1,4,16 …16384 NDIV RSET DIV
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Pulse Width Modulation (PWM) Controlled by Simple 0V to 1V Analog Input Four Available Options Define Duty Cycle Limits – Minimum Duty Cycle at 0% or 5% – Maximum Duty Cycle at 95% or 100% Frequency Range: 3.81Hz to 1MHz Single Resistor Programs Frequency with < 2.4% Maximum Error PWM Duty Cycle Error < 4.5% Maximum Frequency Modulation (VCO) Capability 2.25V to 5.5V Single Supply Operation 115μA Supply Current at 100kHz 500μs Start-Up Time CMOS Output Driver Sources/Sinks 20mA –40°C to 125°C Operating Temperature Range Available in Low Profile (1mm) SOT-23 (ThinSOT™) and 2mm × 3mm DFN
Applying a voltage between 0V and 1V on the MOD pin sets the duty cycle, according to the following formula: Duty Cycle = − 100mV VMOD 1V − ≅ MOD 0.8 • VSET 8 800mV
APPLICATIONS
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LED Dimming Control PWM Servo Loops High Vibration, High Acceleration Environments Portable and Battery-Powered Equipment
The four versions differ in their minimum/maximum duty cycle. Note that a minimum duty cycle limit of 0% or maximum duty cycle limit of 100% allows oscillations to stop at the extreme duty cycle settings.
DEVICE NAME LTC6992-1 LTC6992-2 LTC6992-3 LTC6992-4 PWM DUTY CYCLE RANGE 0% to 100% 5% to 95% 0% to 95% 5% to 100% OUTPUT DUTY CYCLE LIMITS MIN MAX GND V+ GND V+
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and TimerBlox and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1MHz Pulse Width Modulator
ANALOG PWM DUTY CYCLE CONTROL (0V TO 1V) MOD OUT V+ V+ C1 0.1μF SET RSET 50k DIV
6992 TA01a
LTC6992 GND
MOD 0.5V/DIV
OUT 1V/DIV
2μs/DIV
6992 TA01b
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 ABSOLUTE MAXIMUM RATINGS
(Note 1)
Supply Voltage (V+) to GND .........…………………….6V Maximum Voltage On Any Pin .............................(GND – 0.3V) ≤ VPIN ≤ (V+ + 0.3V) Operating Temperature Range (Note 2) LTC6992C ................................................ 0°C to 70°C LTC6992I .............................................–40°C to 85°C LTC6992H .......................................... –40°C to 125°C
Specified Temperature Range (Note 3) LTC6992C ................................................ 0°C to 70°C LTC6992I .............................................–40°C to 85°C LTC6992H .......................................... –40°C to 125°C Junction Temperature .......................................... 150°C Storage Temperature Range .................. –65°C to 150°C Lead Temperature (Soldering, 10 sec)................... 300°C
PIN CONFIGURATION
TOP VIEW TOP VIEW V+ 1 DIV 2 SET 3 7 GND 6 OUT 5 GND 4 MOD MOD 1 GND 2 SET 3 6 OUT 5 V+ 4 DIV
DCB PACKAGE 6-LEAD (2mm 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 64°C/W, θJC = 10.6°C/W EXPOSED PAD (PIN 7) IS GND, PCB CONNECTION IS OPTIONAL
S6 PACKAGE 6-LEAD PLASTIC TSOT-23 TJMAX = 150°C, θJA = 230°C/W, θJC = 51°C/W
ORDER INFORMATION
LEAD FREE FINISH LTC6992CDCB6-1#PBF LTC6992IDCB6-1#PBF LTC6992HDCB6-1#PBF LTC6992CS6-1#PBF LTC6992IS6-1#PBF LTC6992HS6-1#PBF LTC6992CDCB6-2#PBF LTC6992IDCB6-2#PBF LTC6992HDCB6-2#PBF LTC6992CS6-2#PBF LTC6992IS6-2#PBF LTC6992HS6-2#PBF LTC6992CDCB6-3#PBF LTC6992IDCB6-3#PBF LTC6992HDCB6-3#PBF LTC6992CS6-3#PBF LTC6992IS6-3#PBF TAPE AND REEL LTC6992CDCB6-1#TRPBF LTC6992IDCB6-1#TRPBF LTC6992HDCB6-1#TRPBF LTC6992CS6-1#TRPBF LTC6992IS6-1#TRPBF LTC6992HS6-1#TRPBF LTC6992CDCB6-2#TRPBF LTC6992IDCB6-2#TRPBF LTC6992HDCB6-2#TRPBF LTC6992CS6-2#TRPBF LTC6992IS6-2#TRPBF LTC6992HS6-2#TRPBF LTC6992CDCB6-3#TRPBF LTC6992IDCB6-3#TRPBF LTC6992HDCB6-3#TRPBF LTC6992CS6-3#TRPBF LTC6992IS6-3#TRPBF PART MARKING* XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX PACKAGE DESCRIPTION 6-Lead (2mm × 3mm) Plastic DFN 6-Lead (2mm × 3mm) Plastic DFN 6-Lead (2mm × 3mm) Plastic DFN 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead (2mm × 3mm) Plastic DFN 6-Lead (2mm × 3mm) Plastic DFN 6-Lead (2mm × 3mm) Plastic DFN 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead (2mm × 3mm) Plastic DFN 6-Lead (2mm × 3mm) Plastic DFN 6-Lead (2mm × 3mm) Plastic DFN 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 SPECIFIED TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C –40°C to 125°C 0°C to 70°C –40°C to 85°C –40°C to 125°C 0°C to 70°C –40°C to 85°C –40°C to 125°C 0°C to 70°C –40°C to 85°C –40°C to 125°C 0°C to 70°C –40°C to 85°C –40°C to 125°C 0°C to 70°C –40°C to 85°C
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 ORDER INFORMATION
LEAD FREE FINISH LTC6992HS6-3#PBF LTC6992CDCB6-4#PBF LTC6992IDCB6-4#PBF LTC6992HDCB6-4#PBF LTC6992CS6-4#PBF LTC6992IS6-4#PBF LTC6992HS6-4#PBF TAPE AND REEL LTC6992HS6-3#TRPBF LTC6992CDCB6-4#TRPBF LTC6992IDCB6-4#TRPBF LTC6992HDCB6-4#TRPBF LTC6992CS6-4#TRPBF LTC6992IS6-4#TRPBF LTC6992HS6-4#TRPBF PART MARKING* XXXX XXXX XXXX XXXX XXXX XXXX XXXX PACKAGE DESCRIPTION 6-Lead Plastic TSOT-23 6-Lead (2mm × 3mm) Plastic DFN 6-Lead (2mm × 3mm) Plastic DFN 6-Lead (2mm × 3mm) Plastic DFN 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 SPECIFIED TEMPERATURE RANGE –40°C to 125°C 0°C to 70°C –40°C to 85°C –40°C to 125°C 0°C to 70°C –40°C to 85°C –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, VMOD = 0V to VSET, DIVCODE = 0 to 15 (NDIV = 1 to 16,384), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
SYMBOL fOUT ΔfOUT ΔfOUT/ΔT ΔfOUT/ΔV+ PARAMETER Output Frequency Frequency Accuracy (Note 4) Frequency Drift Over Temperature Frequency Drift Over Supply Period Jitter (Note 11) V+ = 4.5V to 5.5V V+ = 2.25V to 4.5V NDIV = 1 NDIV = 4 NDIV = 16 Long-Term Stability of Output Frequency (Note 9) BWFM tS,FM Frequency Modulation Bandwidth Frequency Change Settling Time (Note 10) PWM Duty Cycle Accuracy Maximum Duty Cycle Limit Minimum Duty Cycle Limit PWM Duty Cycle Bandwidth Duty Cycle Setting Time (Note 6) tMASTER = tOUT/NDIV tMASTER = tOUT/NDIV 3.81Hz ≤ fOUT ≤ 1MHz
l l l l
ELECTRICAL CHARACTERISTICS
Oscillation Frequency
CONDITIONS
MIN 3.81
TYP
MAX 1000000
UNITS Hz % % %/°C %/V %/V %P-P %P-P %RMS %P-P %RMS ppm/√kHz kHz μs
±0.8 ±0.005 0.25 0.08 1.2 0.4 0.07 0.15 0.022 TBD TBD TBD
±1.7 ±2.4 0.65 0.18
Pulse Width Modulation ΔD DMAX DMIN BWPWM tS,PWM VMOD = 0.2 • VSET to 0.8 • VSET VMOD < 0.2 • VSET or VMOD > 0.8 • VSET
l l
±1.5 ±2.0 100 90.5 1 95 5 TBD TBD
±4.5 ±4.9 99 0 9.5
% % % % % % kHz μs
LTC6992-1/LTC6992-3, POL = 0, VMOD = 1V l LTC6992-2/LTC6992-4, POL = 0, VMOD = 1V l LTC6992-1/LTC6992-4, POL = 0, VMOD = 0V l LTC6992-2/LTC6992-3, POL = 0, VMOD = 0V l
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, VMOD = 0V to VSET, DIVCODE = 0 to 15 (NDIV = 1 to 16,384), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
SYMBOL V+ IS PARAMETER Operating Supply Voltage Range Power-On Reset Voltage Supply Current RL = ∞, RSET = 50k, NDIV = 1 RL = ∞, RSET = 50k, NDIV = 4 RL = ∞, RSET = 50k, NDIV ≥ 16 RL = ∞, RSET = 800k, NDIV = 1 to 16, 384 Analog Inputs VSET ΔVSET/ΔT RSET Voltage at SET Pin VSET Drift Over Temperature Frequency-Setting Resistor MOD Pin Input Capacitance MOD Pin Input Current VMOD,HI VMOD,LO VDIV ΔVDIV/ΔV+ VMOD Voltage for Maximum Duty Cycle VMOD Voltage for Minimum Duty Cycle DIV Pin Voltage DIV Pin Valid Code Range (Note 5) DIV Pin Input Current Digital Output IOUT(MAX) VOH Output Output Current High Level Output Voltage V+ = 5.5V V+ = 3.3V V+ = 2.25V VOL Low Level Output Voltage V+ = 5.5V V+ = 3.3V V+ = 2.25V IOUT = –1mA IOUT = –16mA IOUT = –1mA IOUT = –10mA IOUT = –1mA IOUT = -8mA IOUT = 1mA IOUT = 16mA IOUT = 1mA IOUT = 10mA IOUT = 1mA IOUT = 8mA
l l l l l l l l l l l l l l l l l
ELECTRICAL CHARACTERISTICS
Power Supply
CONDITIONS
l l
MIN 2.25
TYP
MAX 5.5 1.95
UNITS V V μA μA μA μA μA μA μA μA V μV/°C kΩ pF nA V V V V
V+ = 5.5V V+ = 2.25V V+ = 5.5V V+ = 2.25V V+ = 5.5V V+ = 2.25V V+ = 5.5V V+ = 2.25V
l l l l l l l l
365 225 350 225 325 215 120 105 0.97 50 2.5 1.00 ±75
450 285 420 280 390 265 170 150 1.03 800 ±10
LTC6992-1/LTC6992-4, POL = 0, D = 100% LTC6992-2/LTC6992-3, POL = 0, D = 95% LTC6992-1/LTC6992-3, POL = 0, D = 0% LTC6992-2/LTC6992-4, POL = 0, D = 5% Deviation from Ideal VDIV/V+ = (DIVCODE + 0.5)/16
l l 0.064 • VSET l l l
0.90 • VSET 0.86 • VSET 0.10 • VSET 0.14 • VSET
0.936•VSET
0
V+ ±1.5 ±10nA ±20
V %
mA V V V V V V 0.04 0.54 0.05 0.46 0.07 0.54 V V V V V V
5.45 4.84 3.24 2.75 2.17 1.58
5.48 5.15 3.27 2.99 2.21 1.88 0.02 0.26 0.03 0.22 0.03 0.26
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 ELECTRICAL CHARACTERISTICS
SYMBOL tr PARAMETER Output Rise Time (Note 8) V+ = 5.5V V+ = 3.3V V+ = 2.25V V+ = 5.5V V+ = 3.3V V+ = 2.25V
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, VMOD = 0V to VSET, DIVCODE = 0 to 15 (NDIV = 1 to 16,384), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
CONDITIONS MIN TYP 1.1 1.7 2.7 1.0 1.6 2.4 MAX UNITS ns ns ns ns ns ns
tf
Output Fall Time (Note 8)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC6992C is guaranteed functional over the operating temperature range of –40°C to 85°C. Note 3: The LTC6992C is guaranteed to meet specified performance from 0°C to 70°C. The LTC6992C is designed, characterized and expected to meet specified performance from –40°C to 85°C but it is not tested or QA sampled at these temperatures. The LTC6992I is guaranteed to meet specified performance from –40°C to 85°C. The LTC6992H is guaranteed to meet specified performance from –40°C to 125°C. Note 4: Frequency accuracy is defined as the deviation from the fOUT equation, assuming RSET is used to program the frequency. Note 5: See Operation section, Table 1 and Figure 2 for a full explanation of how the DIV pin voltage selects the value of DIVCODE. Note 6: Duty cycle setting time is the is the amount of time required for the output to settle within ±1% of the final duty cycle after a ±10% change in the setting (±80mV step in VMOD).
Note 7: To conform to the Logic IC Standard, current out of a pin is arbitrarily given a negative value. Note 8: Output rise and fall times are measured between the 10% and the 90% power supply levels with 5pF output load. These specifications are based on characterization. Note 9: Long term drift on silicon oscillators is primarily due to the movement of ions and impurities within the silicon and is tested at 30°C under otherwise nominal operating conditions. Long term drift is specified as ppm/√kHr due to the typically non-linear nature of the drift. To calculate drift for a set time period, translate that time into thousands of hours, take the square root and multiply by the typical drift number. For instance, a year is 8.77kHr and would yield a drift of 888ppm at 300ppm/√kHr. Drift without power applied to the device may be approximated as 1/10th of the drift with power, or 30ppm/√kHr for a 300ppm/√kHr device. Note 10: Frequency change settling time is the amount of time required for the output to settle within ±1% of the final frequency after a 0.5x or 2x change in ISET. Note 11: Jitter is the ratio of the peak-to-peak deviation of the period to the mean of the period. This specification is based on characterization and is not 100% tested.
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 TYPICAL PERFORMANCE CHARACTERISTICS
otherwise noted. Frequency Error vs Temperature
3 GUARANTEED MAX OVER TEMPERATURE 2 1 ERROR (%) ERROR (%) 0 –1 –2 GUARANTEED MIN OVER TEMPERATURE –3 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 RSET = 50k 3 PARTS 2 1 0 –1 –2 GUARANTEED MIN OVER TEMPERATURE –3 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 –3 –50 ERROR (%) 3 GUARANTEED MAX OVER TEMPERATURE RSET = 200k 3 PARTS 2 1 0 –1 –2 GUARANTEED MIN OVER TEMPERATURE –25 75 0 25 50 TEMPERATURE (°C) 100 125
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
Frequency Error vs Temperature
3
Frequency Error vs Temperature
GUARANTEED MAX OVER TEMPERATURE RSET = 800k 3 PARTS
6992 G01
6992 G02
6992 G03
Frequency Error vs RSET
3 GUARANTEED MAX OVER TEMPERATURE 2 1 ERROR (%) DRIFT (%) 0 –1 –2 GUARANTEED MIN OVER TEMPERATURE –3 50 100 200 RSET (k) 400 800
6992 G04
Frequency Drift vs Supply Voltage
0.5 0.4 0.3 RSET = 50k NUMBER OF UNITS 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 2 REFERENCED TO V+ = 4.5V 4 5 3 SUPPLY VOLTAGE (V)
6992 G05
Typical VSET Distribution
250 2 LOTS DFN AND SOT-23 1274 UNITS
3 PARTS
200
150
100
RSET = 200k
RSET = 800k
50
6
0 0.98
0.988
0.996 1.004 VSET (V)
1.012
1.02
6992 G06
VSET Drift vs ISET
1.0 0.8 0.6 0.4 VSET (mV) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 5 REFERENCED TO ISET = 10μA 10 ISET (μA) 15 20
6992 G07
VSET Drift vs Supply
1.0 0.8 0.6 0.4 DRIFT (mV) VSET (V) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 2 3 REFERENCED TO V+ = 4V 4 SUPPLY (V) 5
6992 G08
VSET vs Temperature
1.020 1.015 1.010 1.005 1.000 0.995 0.990 0.985 6 0.980 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 3 PARTS
6992 G09
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 TYPICAL PERFORMANCE CHARACTERISTICS
otherwise noted. NDIV = 1 Duty Cycle Error vs RSET
5 4 3 2 ERROR (%) ERROR (%) 1 0 –1 –2 –3 –4 –5 50 100 200 RSET (k) 400 800
6992 G10
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
NDIV = 1 Duty Cycle Error vs RSET
5 VMOD/VSET = 0.5 (50%) 4 DIVCODE = 0 3 PARTS 3 2 1 0 –1 –2 –3 –4 –5 50 100 200 RSET (k) 400 800
6992 G11
NDIV = 1 Duty Cycle Error vs RSET
5 VMOD/VSET = 0.8 (87.5%) 4 DIVCODE = 0 3 PARTS 3 2 ERROR (%) 1 0 –1 –2 –3 –4 –5 50 100 200 RSET (k) 400 800
6992 G12
VMOD/VSET = 0.2 (12.5%) DIVCODE = 0 3 PARTS
NDIV > 1 Duty Cycle Error vs RSET
5 VMOD/VSET = 0.2 (12.5%) 4 DIVCODE = 4 3 PARTS 3 2 ERROR (%) 1 0 –1 –2 –3 –4 –5 50 100 200 RSET (k) 400 800
6992 G13
NDIV > 1 Duty Cycle Error vs RSET
5 VMOD/VSET = 0.5 (50%) 4 DIVCODE = 4 3 PARTS 3 2 ERROR (%) ERROR (%) 1 0 –1 –2 –3 –4 –5 50 100 200 RSET (k) 400 800
6992 G14
NDIV > 1 Duty Cycle Error vs RSET
5 VMOD/VSET = 0.8 (87.5%) 4 DIVCODE = 4 3 PARTS 3 2 1 0 –1 –2 –3 –4 –5 50 100 200 RSET (k) 400 800
6992 G15
NDIV = 1 Duty Cycle Clamps vs RSET
97 DIVCODE = 0 96 3 PARTS 95 94 93 ERROR (%) 92 8 7 6 5 4 3 50 100 200 RSET (k) 400 800
6992 G16
NDIV > 1 Duty Cycle Error vs RSET
97 DIVCODE = 4 96 3 PARTS 95
LTC6992-2/LTC6992-3 VMOD = VSET ERROR (%)
94 93 92 8 7 6 5 4 3 50 100 200 RSET (k) 400 800
6992 G17
LTC6992-2/LTC6992-3 VMOD = VSET
LTC6992-2/LTC6992-4 VMOD = VSET
LTC6992-2/LTC6992-4 VMOD = VSET
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 TYPICAL PERFORMANCE CHARACTERISTICS
otherwise noted. NDIV = 1 Duty Cycle Error vs Temperature
5 4 3 2 ERROR (%) 1 0 –1 –2 –3 –4 –5 –50 –25 GUARANTEED MIN 75 0 25 50 TEMPERATURE (°C) 100 125 GUARANTEED MAX VMOD/VSET = 0.2 (12.5%) DIVCODE = 0 3 PARTS ERROR (%) 5 4 V /V = 0.5 (50%) 3 MOD SET DIVCODE = 0 2 3 PARTS 1 0 –1 –2 –3 –4 –5 –50 –25 GUARANTEED MIN 75 0 25 50 TEMPERATURE (°C) 100 125 ERROR (%) GUARANTEED MAX
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless NDIV = 1 Duty Cycle Error vs Temperature
5 4 V /V = 0.8 (87.5%) 3 MOD SET DIVCODE = 0 2 3 PARTS 1 0 –1 –2 –3 –4 –5 –50 –25 GUARANTEED MIN 75 0 25 50 TEMPERATURE (°C) 100 125 GUARANTEED MAX
NDIV = 1 Duty Cycle Error vs Temperature
6992 G18
6992 G19
6992 G20
NDIV > 1 Duty Cycle Error vs Temperature
5 4 VMOD/VSET = 0.2 (12.5%) DIVCODE = 4 2 3 PARTS 3 ERROR (%) ERROR (%) 1 0 –1 –2 –3 –4 –5 –50 –25 GUARANTEED MIN 75 0 25 50 TEMPERATURE (°C) 100 125 GUARANTEED MAX 5 4
NDIV > 1 Duty Cycle Error vs Temperature
5 GUARANTEED MAX 4
NDIV > 1 Duty Cycle Error vs Temperature
GUARANTEED MAX
VMOD/VSET = 0.5 (50%) DIVCODE = 4 2 3 PARTS 3 ERROR (%) GUARANTEED MIN –25 75 0 25 50 TEMPERATURE (°C) 100 125 1 0 –1 –2 –3 –4 –5 –50
VMOD/VSET = 0.8 (87.5%) DIVCODE = 4 2 3 PARTS 3 1 0 –1 –2 –3 –4 –5 –50 –25 GUARANTEED MIN 75 0 25 50 TEMPERATURE (°C) 100 125
6992 G21
6992 G22
6992 G23
NDIV = 1 Duty Cycle Clamps vs Temperature
97 DIVCODE = 0 96 3 PARTS 95 94 93 ERROR (%) 92 8 7 6 5 4 3 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 LTC6992-2/LTC6992-4 VMOD = GND DUTY CYCLE (%) LTC6992-2/LTC6992-3 VMOD = VSET 97
NDIV > 1 Duty Cycle Clamps vs Temperature
DIVCODE = 4 96 3 PARTS 95 94 93 92 8 7 6 5 4 3 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 LTC6992-2/LTC6992-4 VMOD = GND LTC6992-2/LTC6992-3 VMOD = VSET
6992 G24
6992 G25
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 TYPICAL PERFORMANCE CHARACTERISTICS
otherwise noted. Duty Cycle Error vs DIVCODE
5 VMOD / VSET = 0.2 (12.5%) 4 3 PARTS 3 2 ERROR (%) ERROR (%) 1 0 –1 –2 –3 –4 –5 0 2 4 10 6 8 DIVCODE 12 14
6992 G26
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
Duty Cycle Error vs DIVCODE
5 VMOD /VSET = 0.5 (50%) 4 3 PARTS 3 2 1 0 –1 –2 –3 –4 –5 0 2 4 10 6 8 DIVCODE 12 14
6992 G27
Duty Cycle Error vs DIVCODE
5 VMOD /VSET = 0.8 (87.5%) 4 3 PARTS 3 2 ERROR (%) 1 0 –1 –2 –3 –4 –5 0 2 4 10 6 8 DIVCODE 12 14
6992 G28
NDIV = 1 Duty Cycle vs VMOD/ VSET
100 DIVCODE = 0 90 3 PARTS 80 DUTY CYCLE (%) DUTY CYCLE (%) 70 60 50 40 30 20 10 0 0 0.2 0.4 0.6 VMOD/VSET (V/V) 0.8
6992 G29
NDIV > 1 Duty Cycle vs VMOD/ VSET
100 DIVCODE = 4 90 3 PARTS 80 DUTY CYCLE (%) 100 LTC6992-1/ LTC6992-4 LTC6992-2/ LTC6992-3 90 80
NDIV > 1 Duty Cycle vs VMOD/ VSET
LTC6992-1/LTC6992-3
LTC6992-1/ LTC6992-4 LTC6992-2/ LTC6992-3
70 60 50 40 30 20 LTC6992-2/ LTC6992-4
70 LTC6992-2/ LTC6992-4 60 50 40 30 20 LTC6992-2/ LTC6992-3
LTC6992-2/ LTC6992-4
LTC6992-1/LTC6992-3 1
10 0 0 0.2
LTC6992-1/LTC6992-3 0.4 0.6 VMOD/VSET (V/V) 0.8
6992 G30
1
LTC6992-1/ 10 DIVCODE = 11 LTC6992-4 3 PARTS 0 0.4 0.6 0 0.2 VMOD/VSET (V/V)
0.8
6992 G31
1
NDIV = 1 Duty Cycle Error vs Ideal
5 DIVCODE = 0 4 3 PARTS 3 2 ERROR (%) ERROR (%) 1 0 –1 –2 –3 –4 –5 0 75 25 50 IDEAL DUTY CYCLE (%) 100
6992 G32
NDIV > 1 Duty Cycle Error vs Ideal
5 DIVCODE = 4 4 3 PARTS 3 2 ERROR (%) 5
NDIV > 1 Duty Cycle Error vs Ideal
DIVCODE = 11 4 3 PARTS 3 2 PART A PART C
PART C PART B
1 0 –1 –2 –3 –4 –5 0
PART B
PART C
1 0 –1 –2 –3 –4 –5 PART B
PART A
PART A
75 25 50 IDEAL DUTY CYCLE (%)
100
6992 G33
0
75 25 50 IDEAL DUTY CYCLE (%)
100
6992 G34
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 TYPICAL PERFORMANCE CHARACTERISTICS
otherwise noted. Linearity Near 100% Duty Cycle
100 DIVCODE = 4 99 LTC6992-1/LTC6992-4 98 3 PARTS 97 DUTY CYCLE (%) 96 95 94 93 92 91 90 89 88 0.804 0.868 0.836 VMOD/VSET (V/V) 0.9
6992 G35
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
Linearity Near 95% Duty Cycle
100 DIVCODE = 4 99 LTC6992-2/LTC6992-3 98 3 PARTS 97 DUTY CYCLE (%) 96 95 94 93 92 91 90 89 88 0.804 0.868 0.836 VMOD/VSET (V/V) 0.9
6992 G36
Linearity Near 67% Duty Cycle
72 DIVCODE = 4 71 3 PARTS 70 DUTY CYCLE (%) 69 68 67 66 65 64 63 62 0.596 0.612 0.628 0.644 VMOD/VSET (V/V) 0.66 0.676
6992 G37
Linearity Near 0% Duty Cycle
12 DIVCODE = 4 11 LTC6992-1/LTC6992-3 10 3 PARTS 9 DUTY CYCLE (%) DUTY CYCLE (%) 8 7 6 5 4 3 2 1 0 0.084 0.116 0.148 VMOD/VSET (V/V) 0.18
6992 G38
Linearity Near 5% Duty Cycle
12 DIVCODE = 4 11 LTC6992-2/LTC6992-4 10 3 PARTS 9 8 7 6 5 4 3 2 1 0 0.084 0.116 0.148 VMOD/VSET (V/V) 0.18
6992 G39
Linearity Near 31% Duty Cycle
36 DIVCODE = 4 35 3 PARTS 34 DUTY CYCLE (%) 33 32 31 30 29 28 27 26 0.308 0.324 0.34 0.356 VMOD/VSET (V/V) 0.372 0.388
6992 G40
Duty Cycle Drift vs Supply
0.5 0.4 0.3 0.2 DRIFT (%) DRIFT (%) 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 2 3 VMOD/VSET = 0.8 VMOD/VSET = 0.2 VMOD/VSET = 0.5 REFERENCED TO V+ = 4V 4 SUPPLY (V) 5 6
6992 G41
NDIV > 1 Duty Cycle Drift vs Supply
0.5 0.4 0.3 0.2 5% CLAMP VMOD/VSET = 0.2 95% CLAMP POWER SUPPLY CURRENT (μA) DIVCODE = 4 400 350 300 250
Supply Current vs VMOD
LTC6992-2
DIVCODE = 0
RSET = 50k, ÷1 RSET = 50k, ÷16
5% CLAMP
95% CLAMP
0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 2 3
200 150 100 50 RSET = 100k, ÷4 RSET = 800k, ÷1
VMOD/VSET = 0.5 VMOD/VSET = 0.8 REFERENCED TO V+ = 4V 4 SUPPLY (V) 5 6
6992 G42
0 0 0.2 0.4 0.6 VMOD (V) 0.8
1
6992 G43
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 TYPICAL PERFORMANCE CHARACTERISTICS
otherwise noted. Supply Current vs Supply Voltage
400 350 POWER SUPPLY CURRENT (μA) 300 250 200 150 100 50 0 2 3 4 5 SUPPLY VOLTAGE (V) 6
6992 G44
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
Supply Current vs Temperature
400 2.0 5.0V, RSET = 50k, ÷1 5.0V, RSET = 50k, ÷16 2.5V, RSET = 50k, ÷1 JITTER (%P-P) 350 POWER SUPPLY CURRENT (μA) 300 250 200 150 100 50 0 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 5.0V, RSET = 800k, ÷1 2.5V, RSET = 800k, ÷1
Jitter vs Frequency
PEAK-TO-PEAK PERIOD 1.8 DEVIATION MEASURED OVER 30s INTERVALS 1.6 VMOD/VSET = 0.5 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0.01 ÷64 0.1 ÷4, V+ = 5V ÷4, V+ = 2.5V ÷16
LTC6992-2 RSET = 50k, ÷1 RSET = 50k, ÷4
÷1, V+ = 5V
RSET = 50k, ÷16 RSET = 100k, ÷1
÷1, V+ = 2.5V
RSET = 800k, ÷1
10 1 FREQUENCY (kHz)
100
1000
6992 G46
6992 G45
Supply Current vs Frequency, 5V
400 350 POWER SUPPLY CURRENT (μA) 300 ÷16,384 250 200 150 ÷1 100 50 0 0.001 0.01 10 0.1 1 FREQUENCY (kHz) 100 1000 V+ = 5V POWER SUPPLY CURRENT (μA) ÷4 400 350 300 250 200 150
Supply Current vs Frequency, 2.5V
V+ = 2.5V
÷16,384
÷4
÷1 100 50 0 0.001 0.01 10 0.1 1 FREQUENCY (kHz) 100 1000
6992 G47
6992 G48
Output Resistance vs Supply Voltage
50 45 OUTPUT RESISTANCE (Ω) 40 35 30 25 20 15 10 5 0 2 3 4 5 SUPPLY VOLTAGE (V) 6
6992 G50
Rise and Fall Time vs Supply Voltage
3.0 2.5 RISE/FALL TIME (ns) CLOAD = 5pF 1000
Typical ISET Current Limit vs V+
SET PIN SHORTED TO GND
800
OUTPUT SOURCING CURRENT
2.0 1.5 tFALL 1.0 0.5 0 200 ISET (μA) 6
6992 G51
tRISE
600
400
OUTPUT SINKING CURRENT
2
3
4 5 SUPPLY VOLTAGE (V)
0
2
3
4 5 SUPPLY VOLTAGE (V)
6
6992 G52
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 TYPICAL PERFORMANCE CHARACTERISTICS
otherwise noted. Typical Start-Up, POL = 0 V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
Typical Start-Up, POL = 1
V+ 1V/DIV
V+ 1V/DIV
OUT 1V/DIV
500μs
OUT 1V/DIV
500μs
100μs/DIV V+ = 2.5V DIVCODE = 3 (÷64) RSET = 50k VMOD = 0.3V (~25% DUTY CYCLE)
6992 G53
100μs/DIV V+ = 2.5V DIVCODE = 12 (÷64, POL = 1) RSET = 50k VMOD = 0.2V (~87.5% DUTY CYCLE)
6992 G54
PIN FUNCTIONS
(DCB/S6)
V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This supply must be kept free from noise and ripple. It should be bypassed directly to the GND pin with a 0.1μF capacitor. DIV (Pin 2/Pin 4): Programmable Divider and Polarity Input. A V+ referenced A/D converter monitors the DIV pin voltage (VDIV) to determine a 4-bit result (DIVCODE). VDIV may be generated by a resistor divider between V+ and GND. Use 1% resistors to ensure an accurate result. The DIV pin and resistors should be shielded from the OUT pin or any other traces that have fast edges. Limit the capacitance on the DIV pin to less than 100pF so that VDIV settles quickly. The MSB of DIVCODE (POL) determines if the PWM signal is inverted before driving the output. Setting POL = 1 results in a negative transfer function (duty cycle decreasing as VMOD increases). SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage on the SET pin (VSET) is regulated to 1V above GND. The amount of current sourced from the SET pin (ISET) programs the master oscillator frequency. The ISET current range is 1.25μA to 20μA. The output oscillation will stop
if ISET drops below approximately 500nA. A resistor connected between SET and GND is the most accurate way to set the frequency. For best performance, use a precision metal or thin film resistor of 0.5% or better tolerance and 50ppm/°C or better temperature coefficient. For lower accuracy applications an inexpensive 1% thick film resistor may be used. Limit the capacitance on the SET pin to less than 10pF to minimize jitter and ensure stability. Capacitance less than 100pF maintains the stability of the feedback circuit regulating the VSET voltage.
V+ MOD OUT V+ V+ C1 0.1μF
LTC6992 GND
R1
SET RSET
DIV
6992 PF
R2
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 PIN FUNCTIONS
(DCB/S6)
MOD (Pin 4/Pin 1): Pulse-Width Modulation Input. The voltage on the MOD pin controls the output duty cycle. The linear control range is between 0.1 • VSET and 0.9 • VSET (approximately 100mV to 900mV). Beyond those limits the output will either clamp at 5% or 95%, or stop oscillating (0% or 100% duty cycle), depending on the version.
GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground plane for best performance. OUT (Pin 6/Pin 6): Oscillator Output. The OUT pin swings from GND to V+ with an output resistance of approximately 30Ω. The duty cycle is determined by the voltage on the MOD pin. When driving an LED or other low-impedance load a series output resistor should be used to limit source/sink current to 20mA.
BLOCK DIAGRAM
V+ 5 R1 DIV 4 R2 4-BIT A/D CONVERTER DIGITAL FILTER
(S6 Package Pin Numbers Shown)
POL
OUTPUT POLARITY
fOSC = 1MHz • 50kΩ •
MASTER OSCILLATOR ISET VSET
PULSE WIDTH MODULATOR MCLK PROGRAMMABLE DIVIDER ÷1, 4, 16, 64, 256, 1024, 4096, 16384 DUTY CYCLE = VMOD(LIM) – 0.1•VSET 0.8•VSET 6 OUT tOUT D= tON tOFF tON
HALT OSCILLATOR IF ISET < 500nA
DISABLE OUTPUT UNTIL SETTLED VMOD(LIM)
+ –
VSET = 1V 3 ISET SET
POR
VOLTAGE LIMITER
+ –
2
VREF 1V
VMOD 1 MOD
6992 BD
GND
RSET
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 OPERATION
The LTC6992 is built around a master oscillator with a 1MHz maximum frequency. The oscillator is controlled by the SET pin current (ISET) and voltage (VSET), with a 1MHz • 50k conversion factor that is accurate to ±0.8% under typical conditions. I 1 fMASTER = = 1MHz • 50k • SET tMASTER VSET A feedback loop maintains VSET at 1V ±30mV, leaving ISET as the primary means of controlling the output frequency. The simplest way to generate ISET is to connect a resistor (RSET) between SET and GND, such that ISET = VSET/RSET. The master oscillator equation reduces to: 1 1MHz • 50k fMASTER = = tMASTER RSET From this equation it is clear that VSET drift will not affect the output frequency when using a single program resistor (RSET). Error sources are limited to RSET tolerance and the inherent frequency accuracy ΔfOUT of the LTC6992. RSET may range from 50k to 800k (equivalent to ISET between 1.25μA and 20μA). The LTC6992 includes a programmable frequency divider which can further divide the frequency by 1, 4, 16, 64, 256, 1024, 4096 or 16384 before driving the OUT pin. The divider ratio NDIV is set by a resistor divider attached to the DIV pin. 1 1MHz • 50k ISET fOUT = = • tOUT NDIV VSET With RSET in place of VSET/ISET the equation reduces to: fOUT = 1 tOUT = 1MHz • 50k NDIV • RSET DIVCODE The DIV pin connects to an internal, V+ referenced 4-bit A/D converter that monitors the DIV pin voltage (VDIV) to determine the DIVCODE value. DIVCODE programs two settings on the LTC6992: 1. DIVCODE determines the output frequency divider setting, NDIV. 2. DIVCODE determines the output polarity, via the POL bit. VDIV may be generated by a resistor divider between V+ and GND as shown in Figure 1.
2.25V TO 5.5V V+ LTC6992 DIV R2 GND
6992 F01
R1
Figure 1. Simple Technique for Setting DIVCODE
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 OPERATION
Table 1. DIVCODE Programming
DIVCODE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 POL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 NDIV 1 4 16 64 256 1024 4096 16384 16384 4096 1024 256 64 16 4 1 RECOMMENDED fOUT 62.5kHz to 1MHz 15.63kHz to 250kHz 3.906kHz to 62.5kHz 976.6Hz to 15.63kHz 244.1Hz to 3.906kHz 61.04Hz to 976.6Hz 15.26Hz to 244.1Hz 3.815Hz to 61.04Hz 3.815Hz to 61.04Hz 15.26Hz to 244.1Hz 61.04Hz to 976.6Hz 244.1Hz to 3.906kHz 976.6Hz to 15.63kHz 3.906kHz to 62.5kHz 15.63kHz to 250kHz 62.5kHz to 1MHz R1 (kΩ) Open 976 976 1000 1000 1000 1000 1000 887 681 523 392 280 182 102 Short R2 (kΩ) Short 102 182 280 392 523 681 887 1000 1000 1000 1000 1000 976 976 Open VDIV /V+ ≤0.03125 ±0.015 0.09375 ±0.015 0.15625 ±0.015 0.21875 ±0.015 0.28125 ±0.015 0.34375 ±0.015 0.40625 ±0.015 0.46875 ±0.015 0.53125 ±0.015 0.59375 ±0.015 0.65625 ±0.015 0.71875 ±0.015 0.78125 ±0.015 0.84375 ±0.015 0.90625 ±0.015 ≥0.96875 ±0.015
Table 1 offers recommended 1% resistor values that accurately produce the correct voltage division as well as the corresponding NDIV and POL values for the recommended resistor pairs. Other values may be used as long as: 1. The VDIV/V+ ratio is accurate to ±1.5% (including resistor tolerances and temperature effects) 2. The driving impedance (R1||R2) does not exceed 500kΩ. If the voltage is generated by other means (i.e. the output of a DAC) it must track the V+ supply voltage. The last
1000 100 fOUT (kHz) 10 1 0.1 0.01 0.001 0 1 2 3 4 5 6 7 POL BIT = 0
column in Table 1 shows the ideal ratio of VDIV to the supply voltage, which can also be calculated as: VDIV V+ = DIVCODE + 0.5 ±1.5% 16
For example, if the supply is 3.3V and the desired DIVCODE is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV. Figure 2 illustrates the information in Table 1, showing that NDIV is symmetric around the DIVCODE midpoint.
POL BIT = 1 15 14 13 12 11 10 9 8
0V
0.5•V+ INCREASING VDIV
V+
6992 F02
Figure 2. Frequency Range and POL Bit vs DIVCODE
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 OPERATION
Pulse Width (Duty Cycle) Modulation The MOD pin is a high impedance analog input providing direct control of the output duty cycle. The duty cycle is proportional to the voltage applied to the MOD pin, VMOD. VMOD 1 Duty Cycle = D = − 0.8 • VSET 8 The PWM duty cycle accuracy ΔD specifies that the above equation is valid to within ±4.5% for VMOD between 0.2 • VSET and 0.8 • VSET (12.5% to 87.5% duty cycle). Since VSET = 1V ±30mV, the duty cycle equation may be approximated by the following equation. Duty Cycle = D ≅ VMOD − 100mV 800mV
POL = 1 D•tOUT
Output Polarity (POL Bit) The duty cycle equation describes a proportional transfer function, where duty cycle increases as VMOD increases. The LTC6992 includes a POL bit (determined by the DIVCODE as described earlier) that inverts the output signal. This makes the duty cycle gain negative, reducing duty cycle as VMOD increases.
POL = 0 D•tOUT
D
VMOD 0.8 • VSET
1 8
OUT tOUT
D1
VMOD 0.8 • VSET
1 8
The VMOD control range is approximately 0.1V to 0.9V. Driving VMOD beyond that range (towards GND or V+) will have no further affect on the duty cycle. Duty Cycle Limits The only difference between the four versions of the LTC6992 is the limits, or clamps, placed on the output duty cycle. The LTC6992-1 generates output duty cycles ranging from 0% to 100%, meaning the output can stop oscillating and rest at GND or V+. The LTC6992-2 will never stop oscillating, regardless of the VMOD level. Internal clamping circuits limit its duty cycle to a 5% to 95% range (1% to 99% guaranteed). Therefore, its VMOD control range is 0.14 • VSET to 0.86 • VSET (approximately 0.14V to 0.86V). The LTC6992-3 and LTC6992-4 complete the family by providing one-sided clamping. The LTC6992-3 allows 0% to 95% duty cycle, and the LTC6992-4 allows 5% to 100% duty cycle.
OUT tOUT
6992 F03
Figure 3. POL Bit Functionality
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 OPERATION
POL = 1 forces a simple logic inversion, so it changes the duty cycle range of the LTC6992-3 (making it 100% to 5%) and LTC6992-4 (making it 95% to 0%). These transfer functions are detailed in Figure 4.
Table 2. Duty Cycle Ranges
DUTY CYCLE RANGE vs VMOD = 0V → 1V PART NUMBER LTC6992-1 LTC6992-2 LTC6992-3 LTC6992-4 POL = 0 0% to 100% 5% to 95% 0% to 95% 5% to 100% POL = 1 100% to 0% 95% to 5% 100% to 5% 95% to 0%
100 90 80 DUTY CYCLE (%)
VMOD /VSET = 0.1
100 90 80 VMOD /VSET = 0.14
60 50 40 30 20 10 0 0
POL = 1
POL = 0
DUTY CYCLE (%)
70
70 60 50 40 30 20 POL = 1 POL = 0
VMOD /VSET = 0.9 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VMOD/VSET (V/V) 1
10 0 0
VMOD /VSET = 0.86 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VMOD/VSET (V/V) 1
6992 F04a
6992 F04b
LTC6992-1
100 90 80 DUTY CYCLE (%) DUTY CYCLE (%) 70 60 50 40 30 20 10 0 0 VMOD /VSET = 0.86 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VMOD/VSET (V/V) 1 POL = 1 POL = 0 VMOD /VSET = 0.1 100 90 80 70 60 50 40 30 20 10 0 0
LTC6992-2
VMOD /VSET = 0.14
POL = 1
POL = 0
VMOD /VSET = 0.9 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VMOD/VSET (V/V) 1
6992 F02c
6992 F02d
LTC6992-3
LTC6992-4
Figure 4. PWM Transfer Functions for All LTC6992 Family Parts
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 OPERATION
Changing DIVCODE After Start-Up Following start-up, the A/D converter will continue monitoring VDIV for changes. Changes to DIVCODE will be recognized slowly, as the LTC6992 places a priority on eliminating any “wandering” in the DIVCODE. The typical delay depends on the difference between the old and new DIVCODE settings and is proportional to the master oscillator period. tDIVCODE = 16 • (ΔDIVCODE + 6) • tMASTER A change in DIVCODE will not be recognized until it is stable, and will not pass through intermediate codes. A digital filter is used to guarantee the DIVCODE has settled to a new value before making changes to the output. Then the output will make a clean (glitchless) transition to the new divider setting. Start-Up Time When power is first applied to the LTC6992 the power-on reset (POR) circuit will initiate the start-up time, tSTART. The OUT pin is held low during this time. The typical value for tSTART ranges from 0.5ms to 8ms depending on the master oscillator frequency (independent of NDIV): tSTART(TYP) = 500 • tMASTER The output will begin oscillating after tSTART. If POL = 0 the first pulse has the correct width. If POL = 1 (DIVCODE ≥ 8), the first pulse width can be shorter or longer than expected, depending on the duty cycle setting, and will never be less than 25% of tOUT. During start-up, the DIV pin A/D converter must determine the correct DIVCODE before the output is enabled. The start-up time may increase if the supply or DIV pin voltages are not stable. For this reason, it is recommended to minimize the capacitance on the DIV pin so it will properly track V+. Less than 100pF will not affect performance.
V+
DIV
STABLE VDIV tDIVCODE tSTART
OUT
6992 F06
1ST PULSE WIDTH MAY BE INACCURATE
Figure 5. DIVCODE Change from 5 to 2
Figure 6. Start-Up Timing Diagram
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 APPLICATIONS INFORMATION
Basic Operation The simplest and most accurate method to program the LTC6992 is to use a single resistor, RSET, between the SET and GND pins. The design procedure is a four step process. After choosing the POL bit setting and proper LTC6992 version, select the NDIV value and then calculate the value for the RSET resistor. Step 1: Selecting the POL Bit Setting Most applications will use POL = 0, resulting in a positive transfer function. However, some applications may require a negative transfer function, where increasing VMOD reduces the output duty cycle. For example, if the LTC6992 is used in a feedback loop, POL = 1 may be required to achieve negative feedback. Step 2: Selecting the LTC6992 Version The difference between the LTC6992 versions is observed at the endpoints of the duty cycle control range. Applications that require the output never stop oscillating should use the LTC6992-2. If it is better to allow the output to rest at GND or V+ (0% or 100% duty cycle, respectively), select the LTC6992-1. The LTC6992-3 and LTC6992-4 clamp the duty cycle at only one end of the control range, allowing the output to stop oscillating at the other extreme. If POL = 1 the clamp will swap from low duty cycle to high, or vice-versa. Refer to Table 2 and Figure 4 for assistance in selecting the proper version. Step 3: Selecting the NDIV Frequency Divider Value As explained earlier, the voltage on the DIV pin sets the DIVCODE which determines both the POL bit and the NDIV value. For a given output frequency, NDIV should be selected to be within the following range. 1MHz 62.5kHz ≤ NDIV ≤ fOUT fOUT (1a) With POL already chosen, this completes the selection of DIVCODE. Use Table 1 to select the proper resistor divider or VDIV/V+ ratio to apply to the DIV pin. Step 4: Calculate and Select RSET The final step is to calculate the correct value for RSET using the following equation. RSET = 1MHz • 50k NDIV • fOUT (1b)
Select the standard resistor value closest to the calculated value. Example : Design a PWM circuit that satisfies the following requirements: • fOUT = 20kHz • Positive VMOD to duty cycle response • Output can reach 100% duty cycle, but not 0% • Minimum power consumption Step 1: Selecting the POL Bit Setting For positive transfer function (duty cycle increases with VMOD), choose POL = 0. Step 2: Selecting the LTC6992 Version To limit the minimum duty cycle, but allow the maximum duty cycle to reach 100%, choose LTC6992-4. (Note that if POL = 1 the LTC6992-3 would be the correct choice.) Step 3: Selecting the NDIV Frequency Divider Value Choose an NDIV value that meets the requirements of Equation (1a). 3.125 ≤ NDIV ≤ 50 Potential settings for NDIV include 4 and 16. NDIV = 4 is the best choice, as it minimizes supply current by using a large RSET resistor. POL = 0 and NDIV = 4 requires DIVCODE = 1. Using Table 1, choose the R1 and R2 values to program DIVCODE = 1.
To minimize supply current, choose the lowest NDIV value (generally recommended). For faster start-up or decreased jitter, choose a higher NDIV setting. Alternatively, use Table 1 as a guide to select the best NDIV value for the given application.
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 APPLICATIONS INFORMATION
Step 4: Select RSET Calculate the correct value for RSET using Equation (1b). RSET = 1MHz • 50k = 625k 4 • 20kHz Some applications can eliminate ΔVSET sensitivity by making VMOD proportional to VSET. For example, Figure 9 shows a simple circuit for generating an arbitrary duty cycle. The equation for duty cycle does not depend on VSET at all.
100 90 80 DUTY CYCLE (%) 70 60 50 40 30 20 2.25V TO 5.5V R1 976k SET RSET 625k DIV
6992 F07
Since 625k is not available as a standard 1% resistor, substitute 619k if a 0.97% frequency shift is acceptable. Otherwise, select a parallel or series pair of resistors such as 309k and 316k to attain a more precise resistance. The completed design is shown in Figure 7.
ΔVSET = –30mV
ΔVSET = 0mV ΔVSET = 30mV
VMOD
MOD
OUT
LTC6992-4 GND V+
10 0 0 0.2 0.6 0.4 VMOD (V) 0.8 1
6992 F08
DIVCODE = 1 R2 102k
Figure 8. Duty Cycle Variation Due to ΔVSET
Figure 7. 20kHz PWM Oscillator
MOD
OUT 2.25V TO 5.5V
LTC6992-X
Duty Cycle Sensitivity to ΔVSET The output duty cycle is proportional to the ratio of VMOD/ VSET. Since VSET can vary up to ±30mV from 1V it can effectively gain or attenuate VMOD, as shown below when ΔVSET is added to the equation. VMOD 1 D= − 0.8 • ( VSET + ΔVSET ) 8 The simplifying assumption of ΔVSET = 0V creates the potential for additional duty cycle error, which increases with VMOD, reaching a maximum of 3.4% if ΔVSET = –30mV. V ΔV 1 ⎞ ΔV ⎛ ΔD ≅ MOD • SET ≅ − ⎜ Dideal + ⎟ • SET ⎝ 800mV VSET 8 ⎠ VSET Figure 8 demonstrates the worst-case impact of this variation (if VSET is at its 0.97V or 1.03V limits). This error is in addition to the inherent PWM duty cycle accuracy spec ΔD (±4.5%), so care should be taken if accuracy at high duty cycles (VMOD near 0.9V) is critical.
GND
V+ R1
SET RSET1 D
DIV
6992 F09
R2 1 8
RSET2
RSET2 5 • 4 RSET1 RSET2
Figure 9. Fixed-Frequency, Arbitrary Duty Cycle Oscillator
ISET Extremes (Master Oscillator Frequency Extremes) Pushing ISET outside of the recommended 1.25μA to 20μA range forces the master oscillator to operate outside of the 62.5kHz to 1MHz range in which it is most accurate. The oscillator will still function with reduced accuracy for ISET < 1.25μA. At approximately 500nA, the oscillator output will be frozen in its current state. The output could halt in a high or low state. This avoids introducing short pulses while frequency modulating a very low frequency output.
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 APPLICATIONS INFORMATION
At the other extreme, it is not recommended to operate the master oscillator beyond 2MHz because the accuracy of the DIV pin ADC will suffer. Pulse Width Modulation Bandwidth and Settling Time The LTC6992 will respond to changes in VMOD up to a –3dB bandwidth of TBD (see Figure 10). This makes it easy to stabilize a feedback loop around the LTC6992, since it does not introduce a low frequency pole. Duty cycle settling time depends on the master oscillator frequency. Following a ±100mV step change in VMOD, the duty cycle takes approximately TBD master clock cycles (TBD • tMASTER) to settle to within 1% of the final value. An example is shown in Figure 11. Frequency Modulation and Settling Time In addition to pulse-width modulation, the LTC6992 can be frequency modulated by varying ISET. The LTC6992 will respond to changes in ISET up to a –3dB bandwidth of TBD • fOUT (see Figure 12). Following a 2x or 0.5x step change in ISET, the output frequency takes approximately TBD master clock cycles (TBD • tMASTER) to settle to within 1% of the final value. An example is shown in Figure 13.
PL
AC
E
L HO
DE
R PL AC E
L HO
DE
R
Figure 10. PWM Frequency Response
Figure 12. Frequency Modulation Bandwidth
PL
AC
E
L HO
DE
R PL AC E
L HO
DE
R
Figure 11. PWM Settling Time
Figure 13. Frequency Change Settling Time
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 APPLICATIONS INFORMATION
Power Supply Current The power supply current varies with frequency, supply voltage and output loading. It can be estimated under any condition using the following equation:
If N DIV = 1 (DIVCODE = 0 or 15): IS(TYP) ≈ V + • fOUT • ( 39pF + CLOAD ) L+ V+ V+ + + 2.2 •ISET + 85µA 320kΩ 2 • RLOAD fOUT NDIV • 27pF + V + • fOUT • ( 27pF + CLOAD )
If N DIV > 1 (DIVCODE = 1 or 14): IS(TYP) ≈ V + • L+
1. Connect the bypass capacitor, C1, directly to the V+ and GND pins using a low inductance path. The connection from C1 to the V+ pin is easily done directly on the top layer. For the DFN package, C1’s connection to GND is also simply done on the top layer. For the TSOT-23, OUT can be routed through the C1 pads to allow a good C1 GND connection. If the PCB design rules do not allow that, C1’s GND connection can be accomplished through multiple vias to the ground plane. Multiple vias for both the GND pin connection to the ground plane and the C1 connection to the ground plane are recommended to minimize the inductance. Capacitor C1 should be a 0.1μF ceramic capacitor. 2. Place all passive components on the top side of the board. This minimizes trace inductance. 3. Place RSET as close as possible to the SET pin and make a direct, short connection. The SET pin is a current summing node and currents injected into this pin directly modulate the operating frequency. Having a short connection minimizes the exposure to signal pickup. 4. Connect RSET directly to the GND pin. Using a long path or vias to the ground plane will not have a significant affect on accuracy, but the direct, short connection is recommended and easy to apply. 5. Use a ground trace to shield the SET pin. This provides another layer of protection from radiated signals. 6. Place R1 and R2 close to the DIV pin. A direct, short connection to the DIV pin minimizes the external signal coupling.
V+ V+ + + 2.6 •ISET + 90µA 320kΩ 2 • RLOAD
SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES The LTC6992 is a 2.4% accurate silicon oscillator when used in the appropriate manner. The part is simple to use and by following a few rules, the expected performance is easily achieved. The most important use issues involve adequate supply bypassing and proper PCB layout. Figure 14 shows example PCB layouts for both the TSOT-23 and DFN packages using 0603 sized passive components. The layouts assume a two layer board with a ground plane layer beneath and around the LTC6992. These layouts are a guide and need not be followed exactly.
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22
LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 APPLICATIONS INFORMATION
MOD OUT LTC6992 GND V+ C1 0.1μF V+ R1
SET RSET
DIV R2
V+ R1 V+ DIV R2 SET RSET C1 OUT GND MOD MOD GND SET RSET C1 OUT V+ DIV R1 R2 V+
DFN PACKAGE
TSOT-23 PACKAGE
6992 F14
Figure 14. Supply Bypassing and PCB Layout
TYPICAL APPLICATIONS
Constant On-Time Modulator
VMOD MOD VIN 0V TO 2V RIN* 11.8k VCTRL RM1 1.05k RSET 44.2k RM2 9.31k OUT OUT VCC C1 0.1μF R1 182k DIVCODE = 2 (÷16, POL = 1) R2 976k LTC6992-1 GND VSET V+
SET
DIV
6992 TA02
*OPTIONAL RESISTOR ADJUSTS FOR DESIRED VIN RANGE.
IF
RM2 RM1 +RM2
0.9 THEN tON = NDIV • 1.125μs •
RSET 50k
AS VIN INCREASES, tOUT INCREASES AND DUTY CYCLE DECREASES (BECAUSE POL = 1) TO MAINTAIN A CONSTANT tON. FOR CONSTANT OFF-TIME, JUST CHANGE DIVCODE SO POL = 0.
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23
LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 TYPICAL APPLICATIONS
Digitally Controlled Duty Cycle with Internal VREF Reference Variation Eliminated
MOD
OUT V+ C1 0.1μF
LTC6992-X V+ GND V+
R1
+
1/2 LTC6078 RSET
SET
DIV
6992 TA03
R2
–
V+ REF VOUT LTC1659 GND VCC DIN CLK CS/LD μP
Programming NDIV Using an 8-Bit DAC
ANALOG PWM DUTY CYCLE CONTROL (0V TO 1V) DIVCODE MOD OUT 2.25V TO 5.5V C1 0.1μF C2 0.1μF LTC6992-X GND V+ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DAC CODE 0 24 40 56 72 88 104 120 136 152 168 184 200 216 232 ≥255
6992 TA04
SET RSET
DIV VCC SDI VOUT LTC2630-LZ8 SCK CS/LD GND μP
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 TYPICAL APPLICATIONS
Changing Between Two Frequencies
ANALOG PWM DUTY CYCLE CONTROL (0V TO 1V) ANALOG PWM DUTY CYCLE CONTROL (0V TO 1V) V+ R1 SET fMIN ‘HC04 fMAX 2N7002 ‘HC04
6992 TA05
MOD
OUT
MOD
OUT
LTC6992-X GND V+
LTC6992-X GND V+ R1 SET DIV R2 V+
V+ fMAX RVCO
DIV R2 fMIN V+ RSET2
RSET
RSET1
NOTES WHILE THIS CIRCUIT IS SIMPLER THAN THE CIRCUIT TO THE RIGHT, ITS FREQUENCY ACCURACY IS WORSE DUE TO THE EFFECT OF V+ SUPPLY VARIATION FROM SYSTEM TO SYSTEM AND OVER TEMPERATURE.
NOTES 1. WHEN THE NMOSFET IS OFF THE FREQUENCY IS SET BY RSET = RSET1. , 2. WHEN THE NMOSFET IS ON, THE FREQUENCY IS SET BY RSET = RSET1 || RSET2. + SUPPLY VARIATION IS NOT A FACTOR AS THE SWITCHING RESISTOR IS 3. V EITHER FLOATING OR CONNECTED TO GROUND.
Simple Diode Temperature Sensor
5V R6 R7 45.3k 16.9k D1 1N458 R8 84.5k 5V +10mV/C R9 365Ω MOD LT6003 OUT LTC6992-2 GND V+ 5V R4 1000k R5 186k MOC207M D3 Q1 5V
ADJUST FOR 50% DUT CYCLE AT 25°C
+ –
OUTPUT R11 422Ω C1 1μF
SET R1 130k R2 50k R3 130k
DIV
6992 TA06
NDIV = 16 f = 10kHz PWM OUTPUT FOR ISOLATED MEASUREMENT +1% DUTY CYCLE CHANGE PER DEGREE C –10°C TO 65°C RANGE WITH OPTO-ISOLATOR (DC: 15% TO 95%)
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25
LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 TYPICAL APPLICATIONS
Motor Speed/Direction Control for Full H-Bridge (Locked Anti-Phase Drive)
VS 12V A1
2.6kHz, 5% TO 95% PWM 5% DC = CLOCKWISE 50% DC = STOPPED 95% DC = COUNTER CLOCKWISE INPUT 0V TO 1V MOD OUT
CW CURRENT FLOW MOTOR
LTC6992-2 GND V+ V+ R1 1000k SET R3 300k DIV R2 280k A2
POWER H-BRIDGE HIGH = SWITCH ON
6992 TA07
Motor Speed/Direction Control for Full H-Bridge (Sign/Magnitude Drive)
VS 12V A4 2.6kHz, 5% TO 95% PWM 5% DC = SLOW 95% DC = FAST INPUT 0V TO 1V MOD OUT CW CURRENT FLOW MOTOR A5
LTC6992-2 GND V+ V+ R4 1000k R5 280k DIRECTION H = CCW, L = CW
6992 TA08
SET R3 300k
DIV A3
POWER H-BRIDGE HIGH = SWITCH ON
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26
LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 TYPICAL APPLICATIONS
Ratiometric Sensor to Pulse Width, Non-Inverting Response
R6 9.09k VS C1 0.15μF C2 0.22μF R5 10M
R4 90.9k 2.5V TO 5.5V K=1 RSENSOR K=0 K • VS R3 10k
Ratiometric Sensor to Pulse Width, Inverting Response
R6 9.09k R6 90.9k R3 100k VS C1 0.15μF C2 0.22μF
2.5V TO 5.5V VS K=1 RSENSOR R4 10k VS K=0
R5 10k
+ –
K • VS
+ –
MOD LT1490
OUT
OUTPUT DUTY CYCLE = K • 100% VS R1 1000k R2 186k
LTC6992-1 GND V+
SET RSET 316k
DIV
6992 TA09
NDIV = 16 fOUT = 10kHz
MOD LT1490
OUT
OUTPUT DUTY CYCLE = (1–K) • 100% VS R1 1000k R2 186k
LTC6992-1 GND V+
SET RSET 316k
DIV
6992 TA10
NDIV = 16 fOUT = 10kHz
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27
LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 TYPICAL APPLICATIONS
Ratio Control Servo Pulse Generator
R6 9.09k C1 1μF C2 0.22μF
2.5V TO 5.5V VS
R6 90.9k VS
R6 8.66k SERVO CONTROL POT 10k 2ms
1ms
Direct Voltage Controlled PWM Dimming 0 to 15000 Cd/m2 Intensity
R3 90.9Ω VDIMMING MOD OUT D1 5V R1 1M SET RSET 105k DIV
6992 TA12
28
+ –
R5 130k
MOD LT1490
OUT
OUTPUT 1ms TO 2ms PULSE EVERY 16ms VS R1 1000k R2 681k
LTC6992-1 GND V+
SET RSET 316k
DIV
6992 TA11
NDIV = 4096 fOUT = 62.5kHz, 16ms PERIOD
LTC6992-1 GND V+ HIGH INTENSITY LED SSL-LX5093XUWC
C1 0.1μF
R2 280k
f = 7.5kHz NDIV = 64
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LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 TYPICAL APPLICATIONS
Wide Range LED Dimming (0 to 85000 Cd/m2 Brightness)
R2 7.5k 5V R1 10k LT6004 5V VFAST FAST PWM CONTROLS 6000 TO 85000 Cd/m2 BRIGHTNESS OUT LTC6992-4 GND V+ RDIV1 1M SET RSET1 61.9k DIV RDIV2 280k 5–100% NDIV = 64 f = 12.6kHz A1 PWM LT3518UF D2 VDIMMING 0V TO 1.65V VSLOW MOD OUT LTC6992-1 GND V+ RDIV3 1M SET RSET2 124k DIV RDIV4 681k
6992 TA13
R4 7.5k
R3 10k VREF
+ –
+ –
MOD LT6004
5V C4 0.1μF
3.3V 3.3VIN
5V PVIN LED+ D1
SLOW PWM CONTROLS 0 TO 6000 Cd/m2 BRIGHTNESS LUMILEDS LXHL-BW02
5V C1 0.1μF
0–100% NDIV = 4096 fOUT = 100kHz
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29
LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 PACKAGE DESCRIPTION
DCB Package 6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
0.70 ± 0.05
3.55 ± 0.05
1.65 ± 0.05 (2 SIDES) PACKAGE OUTLINE
2.15 ± 0.05
0.25 ± 0.05 0.50 BSC 1.35 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 2.00 ± 0.10 (2 SIDES) R = 0.115 TYP R = 0.05 TYP 0.40 ± 0.10 4 6
3.00 ± 0.10 (2 SIDES) PIN 1 BAR TOP MARK (SEE NOTE 6)
1.65 ± 0.10 (2 SIDES) PIN 1 NOTCH R0.20 OR 0.25 × 45° CHAMFER 3 1
(DCB6) DFN 0405
0.200 REF
0.75 ± 0.05
0.25 ± 0.05 0.50 BSC
1.35 ± 0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD
NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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30
LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 PACKAGE DESCRIPTION
S6 Package 6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636 Rev B)
0.62 MAX
0.95 REF
2.90 BSC (NOTE 4)
1.22 REF
3.85 MAX 2.62 REF
1.4 MIN
2.80 BSC
1.50 – 1.75 (NOTE 4) PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR
0.95 BSC
0.30 – 0.45 6 PLCS (NOTE 3)
0.80 – 0.90 0.20 BSC DATUM ‘A’ 1.00 MAX 0.01 – 0.10
0.30 – 0.50 REF
NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193
0.09 – 0.20 (NOTE 3)
1.90 BSC
S6 TSOT-23 0302 REV B
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC6992-1/LTC6992-2/ LTC6992-3/LTC6992-4 TYPICAL APPLICATION
LED Driver with 5000:1 Dimming Range
L1 6.8μH D1 R1 3.92M R2 124k ISP RSENSE 330mΩ ISN TG RT C3 0.1pF SS GND C2 4.7μF C1 0.22μF
VIN 5V TO 16V SHDN VIN
SW FB
ANALOG PWM DUTY CYCLE CONTROL (0V TO 1V)
LT3517 MOD OUT 5V C1 2.2μF 1M SET 102k DIV 681k C4 0.1pF PWM TGEN VREF CTRL SYNC VC RT 6.04k 2MHz
300mA
LTC6992-1 GND V+
6992 TA14
C1: KEMET C0806C225K4RAC C2: KEMET C1206C475K3RAC C3, C4: MURATA GRM21BR71H104KA01B C5: MURATA GRM21BR71H224KA01B D1: DIODE DFL5160 L1: TOKO B992A5-6RBN LEDS: LUXEON I (WHITE) M1: ZETEX ZXMP6A13FTA
RELATED PARTS
PART NUMBER LTC1799 LTC6900 LTC6906/LTC6907 LTC6990 LTC6991 LTC6993-1 LTC6993-2 LTC6994-1 LTC6994-2 DESCRIPTION 1MHz to 33MHz ThinSOT Silicon Oscillator 1MHz to 20MHz ThinSOT Silicon Oscillator 10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillator TimerBlox, Voltage Controlled Oscillator TimerBlox, Very Low Frequency Clock with Reset TimerBlox, Monostable Pulse Generator TimerBlox, Retriggerable Monostable Pulse Generator TimerBlox, Delay Block, First Edge Only Delayed TimerBlox, Delay Block/Debouncer, Both Edges Delayed COMMENTS Wide Frequency Range Low Power, Wide Frequency Range Micropower, ISUPPLY = 35μA at 400kHz Frequency from 488Hz to 1MHz, No Caps, 2% Accurate Cycle Time from 2ms to 9.5 Hours, No Caps, 2% Accurate Resistor Set Pulse Width from 1μs to 2ms, No Caps, 2% Accurate Resistor Set Pulse Width from 1μs to 2ms, No Caps, 2% Accurate Resistor Set Delay from 1μs to 2ms, No Caps, 2% Accurate Resistor Set Delay from 1μs to 2ms, No Capacitors Required, 2% Accurate
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32 Linear Technology Corporation
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