LTC6993-4

LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 TimerBlox: Monostable Pulse Generator (One Shot) FEATURES n n n DESCRIPTION The LTC®6993 is a monostable multivibrator (also known as a “one-shot” pulse generator) with a programmable pulse width of 1µs to 33.6 seconds. The LTC6993 is part of the TimerBlox™ family of versatile silicon timing devices. A single resistor, RSET, programs an internal master oscillator frequency, setting the LTC6993’s time base. The output pulse width is determined by this master oscillator and an internal clock divider, NDIV , programmable to eight settings from 1 to 221. tOUT = NDIV • RSET • 1µs, NDIV = 1 , 8, 64,...,221 50kΩ n n n n n n n n n Pulse Width Range: 1µs to 33.6 Seconds Configured with 1 to 3 Resistors Pulse Width Max Error: – 512µs – 1) 1.0 0.8 0.6 0.4 DRIFT (%) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 2 3 RSET = 50k, NDIV = 8 RSET = 50k TO 800k, NDIV ≥ 512 RSET = 800k, NDIV = 8 4 SUPPLY (V) 5 6 69931234 G09 LTC6993-1/LTC6993-2 DIVCODE = 0 REFERENCED TO V+ = 4V LTC6993-3/LTC6993-4 DIVCODE = 0 REFERENCED TO V+ = 4V REFERENCED TO V+ = 4V 0.2 69931234f 6 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 TYPICAL PERFORMANCE CHARACTERISTICS + V = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted. tOUT Error vs RSET (NDIV = 1, Rising Edge) 5 4 3 2 ERROR (%) ERROR (%) 1 0 –1 –2 –3 –4 –5 50 100 200 RSET (k ) 400 800 69931234 G10 LTC6993-1/LTC6993-2 DIVCODE = 0 3 PARTS 5 4 3 2 tOUT Error vs RSET (8 ≤ NDIV ≤ 64) 3 PARTS 5 4 3 2 ERROR (%) 1 0 –1 –2 –3 –4 tOUT Error vs RSET (NDIV ≥ 512) 3 PARTS 1 0 –1 –2 –3 –4 –5 50 100 200 RSET (k ) 400 800 69931234 G11 –5 50 100 200 RSET (k ) 400 800 69931234 G12 tOUT Error vs RSET (NDIV = 1, Falling Edge) 5 4 3 2 ERROR (%) ERROR (%) 1 0 –1 –2 –3 –4 –5 50 100 200 RSET (k ) 400 800 69931234 G13 tOUT Error vs DIVCODE (Rising Edge) 5 4 3 2 ERROR (%) 1 0 –1 –2 –3 –4 –5 0 2 4 6 8 10 DIVCODE 12 14 LTC6993-1/LTC6993-2 RSET = 50k 3 PARTS 5 4 3 2 1 0 –1 –2 –3 –4 –5 tOUT Error vs DIVCODE (Falling Edge) LTC6993-3/LTC6993-4 RSET = 50k 3 PARTS LTC6993-3/LTC6993-4 DIVCODE = 0 3 PARTS 0 2 4 6 8 10 DIVCODE 12 14 69931234 G14 69931234 G15 1.0 0.8 0.6 0.4 VSET Drift vs ISET 1.0 0.8 0.6 0.4 DRIFT (mV) VSET Drift vs Supply Voltage 1.020 1.015 1.010 1.005 VSET (V) 1.000 0.995 0.990 VSET vs Temperature 3 PARTS VSET (mV) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 5 REFERENCED TO ISET = 10µA 10 ISET (µA) 15 20 69931234 G16 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 2 3 REFERENCED TO V+ = 4V 4 SUPPLY (V) 5 69931234 G17 0.985 6 0.980 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 69931234 G18 69931234f 7 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted. Typical VSET Distribution 2 LOTS DFN AND SOT-23 1274 UNITS 300 POWER SUPPLY CURRENT (µA) 250 200 150 100 50 0 TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Supply Voltage “ACTIVE” = 50% TIMING DUTY CYCLE POWER SUPPLY CURRENT (µA) RSET = 50k ÷1, ACTIVE RSET = 50k ÷1, IDLE RSET = 100k, ÷8, ACTIVE RSET = 100k, ÷8, IDLE CLOAD = 5pF RLOAD = ∞ 2 3 RSET = 800k, ÷512 6 69931234 G20 Supply Current vs Temperature 250 “ACTIVE” = 50% TIMING DUTY CYCLE RSET = 50k, ÷1, ACTIVE RSET = 50k, ÷1, IDLE RSET = 100k, ÷8, ACTIVE RSET = 100k, ÷8, IDLE 50 CLOAD = 5pF RLOAD = ∞ –25 RSET = 800k, ÷512 250 200 NUMBER OF UNITS 200 150 150 100 100 50 0 0.98 0.988 0.996 1.004 VSET (V) 1.012 1.02 4 5 SUPPLY VOLTAGE (V) 0 –50 0 25 50 75 TEMPERATURE (°C) 100 125 69931234 G19 69931234 G21 Supply Current vs TRIG Pin Voltage 250 POWER SUPPLY CURRENT (µA) POWER SUPPLY CURRENT (µA) 5V TRIG FALLING 5V TRIG RISING 250 200 Supply Current vs tOUT (5V) ACTIVE CURRENT MEASURED WITH TRIGGER PERIOD = 2 • tOUT (50% DUTY CYCLE) ÷1 150 ÷8 ÷64 ÷512 250 POWER SUPPLY CURRENT (µA) 200 Supply Current vs tOUT (2.5V) ACTIVE CURRENT MEASURED WITH TRIGGER PERIOD = 2 • tOUT (50% DUTY CYCLE) 200 150 3.3V TRIG FALLING 3.3V TRIG RISING 150 ÷1 ÷8 ÷64 100 50 CLOAD = 5pF RLOAD = ∞ 0 0.2 0.6 0.4 VTRIG/V+ (V/V) 0.8 1.0 100 50 V+ = 5V CLOAD = 5pF RLOAD = ∞ 0 0.01 0.001 100 50 V+ = 2.5V CLOAD = 5pF RLOAD = ∞ 0 0.01 0.001 ÷512 0 ACTIVE IDLE 0.1 1 tOUT (ms) 10 100 ACTIVE IDLE 0.1 1 tOUT (ms) 10 100 69931234 G22 69931234 G23 69931234 G24 TRIG Threshold Voltage vs Supply Voltage 3.5 3.0 POSITIVE GOING RST PIN VOLTAGE (V) 2.5 JITTER (%P-P) 2.0 1.5 1.0 0.5 0 2 3 4 5 SUPPLY VOLTAGE (V) 6 69931234 G25 Peak-to-Peak Jitter vs tOUT 1.0 0.9 0.8 0.7 ÷1, 5.5V PEAK-TO-PEAK tOUT VARIATION MEASURED OVER 30s INTERVALS Typical ISET Current Limit vs V+ 1000 SET PIN SHORTED TO GND 800 NEGATIVE GOING 0.5 0.4 0.3 0.2 0.1 0 0.001 ÷1, 2.25V ÷8, 5.5V ÷512 ÷8, 2.25V 0.01 ÷64 0.1 1 tOUT (ms) ÷4096 10 100 ISET (µA) 0.6 600 400 200 0 2 3 4 5 SUPPLY VOLTAGE (V) 6 69931234 G27 69931234 G26 69931234f 8 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 TYPICAL PERFORMANCE CHARACTERISTICS + V = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted. Trigger Propagation Delay (tPD) vs Supply Voltage 30 25 PROPAGATION DELAY (ns) RISE/FALL TIME (ns) 20 15 10 5 0 CLOAD = 5pF 3.0 2.5 OUTPUT RESISTANCE (Ω) 2.0 tRISE 1.5 tFALL 1.0 0.5 0 Rise and Fall Time vs Supply Voltage CLOAD = 5pF 50 45 40 35 30 25 20 15 10 5 2 3 4 5 SUPPLY VOLTAGE (V) 6 6990 G29 Output Resistance vs Supply Voltage OUTPUT SOURCING CURRENT OUTPUT SINKING CURRENT 2 3 4 5 SUPPLY VOLTAGE (V) 6 69931234 G28 0 2 3 4 5 SUPPLY VOLTAGE (V) 6 69931234 G30 PIN FUNCTIONS (DCB/S6) V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This supply should be kept free from noise and ripple. It should be bypassed directly to the GND pin with a 0.1µF capacitor. DIV (Pin 2/Pin 4): Programmable Divider and Polarity Input. The DIV pin voltage (VDIV) is internally converted into a 4-bit result (DIVCODE). VDIV may be generated by a resistor divider between V+ and GND. Use 1% resistors to ensure an accurate result. The DIV pin and resistors should be shielded from the OUT pin or any other traces that have fast edges. Limit the capacitance on the DIV pin to less than 100pF so that VDIV settles quickly. The MSB of DIVCODE (POL) determines the polarity of the OUT pins. When POL = 0 the output produces a positive pulse. When POL = 1 the output produces a negative pulse. SET (Pin 3/Pin 3): Pulse Width Setting Input. The voltage on the SET pin (VSET) is regulated to 1V above GND. The amount of current sourced from the SET pin (ISET) programs the master oscillator frequency. The ISET current range is 1.25µA to 20µA. The output pulse will continue indefinitely if ISET drops below approximately 500nA, and will terminate when ISET increases again. A resistor connected between SET and GND is the most accurate way to set the pulse width. For best performance, use a precision metal or thin film resistor of 0.5% or better tolerance and 50ppm/°C or better temperature coefficient. For lower accuracy applications an inexpensive 1% thick film resistor may be used. Limit the capacitance on the SET pin to less than 10pF to minimize jitter and ensure stability. Capacitance less than 100pF maintains the stability of the feedback circuit regulating the VSET voltage. V+ TRIG OUT V+ V+ C1 0.1µF LTC6993 GND R1 SET RSET DIV 69931234 PF R2 69931234f 9 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 PIN FUNCTIONS (DCB/S6) TRIG (Pin 4/Pin 1): Trigger Input. Depending on the version, a rising or falling edge on TRIG will initiate the output pulse. LTC6993-1 and LTC6993-2 are rising-edge sensitive. LTC6993-3 and LTC6993-4 are falling-edge sensitive. The LTC6993-2 and LTC6993-4 are retriggerable, allowing the pulse width to be extended by additional trigger signals that occur while the output is active. The LTC6993-1/ LTC6993-3 will ignore additional trigger inputs until the output pulse has terminated. GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground plane for best performance. OUT (Pin 6/Pin 6): Output. The OUT pin swings from GND to V+ with an output resistance of approximately 30Ω. When driving an LED or other low impedance load a series output resistor should be used to limit source/sink current to 20mA. BLOCK DIAGRAM (S6 package pin numbers shown) 5 R1 4 R2 TRIGGER/ RETRIGGER LOGIC V+ DIV 4-BIT A/D CONVERTER DIGITAL FILTER POL 1 TRIG S OUTPUT POLARITY OUT MASTER OSCILLATOR V 1µs tMASTER = • SET ISET 50k Q MCLK PROGRAMMABLE DIVIDER ÷1, 8, 64, 512, 4096, 215, 218, 221 R 6 tOUT HALT OSCILLATOR IF ISET < 500nA ISET POR + – VSET = 1V SET 3 ISET RSET 1V + – GND 2 69931234 BD 69931234f 10 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 OPERATION The LTC6993 is built around a master oscillator with a 1µs minimum period. The oscillator is controlled by the SET pin current (ISET) and voltage (VSET), with a 1µs/50kΩ conversion factor that is accurate to ±1.7% under typical conditions. 1µs VSET tMASTER = • 50kΩ ISET A feedback loop maintains VSET at 1V ±30mV, leaving ISET as the primary means of controlling the pulse width. The simplest way to generate ISET is to connect a resistor (RSET) between SET and GND, such that ISET = VSET/RSET . The master oscillator equation reduces to: R tMASTER = 1µs • SET 50kΩ From this equation, it is clear that VSET drift will not affect the pulse width when using a single program resistor (RSET). Error sources are limited to RSET tolerance and the inherent pulse width accuracy ∆tOUT of the LTC6993. RSET may range from 50k to 800k (equivalent to ISET between 1.25µA and 20µA). A trigger signal (rising or falling edge on TRIG pin) latches the output to the active state, beginning the output pulse. At the same time, the master oscillator is enabled to time the duration of the output pulse. When the desired pulse width is reached, the master oscillator resets the output latch. The LTC6993 also includes a programmable frequency divider which can further divide the frequency by 1, 8, 64, 512, 4096, 215, 218 or 221. This extends the pulse width duration by those same factors. The divider ratio NDIV is set by a resistor divider attached to the DIV pin. tOUT = NDIV VSET • • 1µs 50kΩ ISET NDIV • RSET • 1µs 50kΩ DIVCODE The DIV pin connects to an internal, V+ referenced 4-bit A/D converter that determines the DIVCODE value. DIVCODE programs two settings on the LTC6993: 1. DIVCODE determines the frequency divider setting, NDIV . 2. DIVCODE determines the polarity of OUT pin, via the POL bit. VDIV may be generated by a resistor divider between V+ and GND as shown in Figure 1. 2.25V TO 5.5V V+ LTC6993 DIV R2 GND 69931234 F01 R1 Figure 1. Simple Technique for Setting DIVCODE Table 1 offers recommended 1% resistor values that accurately produce the correct voltage division as well as the corresponding NDIV and POL values for the recommended resistor pairs. Other values may be used as long as: 1. The VDIV/V+ ratio is accurate to ±1.5% (including resistor tolerances and temperature effects). 2. The driving impedance (R1||R2) does not exceed 500kΩ. If the voltage is generated by other means (i.e., the output of a DAC) it must track the V+ supply voltage. The last column in Table 1 shows the ideal ratio of VDIV to the supply voltage, which can also be calculated as: VDIV V + = DIVCODE + 0.5 ± 1.5% 16 With RSET in place of VSET/ISET the equation reduces to: tOUT = For example, if the supply is 3.3V and the desired DIVCODE is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV. Figure 2 illustrates the information in Table 1, showing that NDIV is symmetric around the DIVCODE midpoint. 69931234f 11 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 OPERATION Table 1. DIVCODE Programming DIVCODE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 POL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 NDIV 1 8 64 512 4,096 32,768 262,144 2,097,152 2,097,152 262,144 32,768 4,096 512 64 8 1 Recommended tOUT 1µs to 16µs 8µs to 128µs 64µs to 1.024ms 512µs to 8.192ms 4.096ms to 65.54ms 32.77ms to 524.3ms 262.1ms to 4.194sec 2.097sec to 33.55sec 2.097sec to 33.55sec 262.1ms to 4.194sec 32.77ms to 524.3ms 4.096ms to 65.54ms 512µs to 8.192ms 64µs to 1.024ms 8µs to 128µs 1µs to 16µs R1 (k) Open 976 976 1000 1000 1000 1000 1000 887 681 523 392 280 182 102 Short R2 (k) Short 102 182 280 392 523 681 887 1000 1000 1000 1000 1000 976 976 Open VDIV /V+ ≤ 0.03125 ±0.015 0.09375 ±0.015 0.15625 ±0.015 0.21875 ±0.015 0.28125 ±0.015 0.34375 ±0.015 0.40625 ±0.015 0.46875 ±0.015 0.53125 ±0.015 0.59375 ±0.015 0.65625 ±0.015 0.71875 ±0.015 0.78125 ±0.015 0.84375 ±0.015 0.90625 ±0.015 ≥ 0.96875 ±0.015 POL BIT = 0 10000 1000 100 tOUT (ms) 10 1 0.1 1 0.01 0.001 0V 0 0.5 • V+ INCREASING VDIV 2 3 4 5 6 7 8 9 10 POL BIT = 1 11 12 13 14 15 V+ 69931234 F02 Figure 2. Pulse Width Range and POL Bit vs DIVCODE 69931234f 12 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 OPERATION Monostable Multivibrator (One Shot) The LTC6993 is a monostable multivibrator. A trigger signal on the TRIG input will force the output to the active (unstable) state for a programmable duration. This type of circuit is commonly referred to as a one-shot pulse generator. Figures 3 details the basic operation. A rising edge on the TRIG pin initiates the output pulse. The pulse width (tOUT) is determined by the NDIV setting and by the resistor (RSET) connected to the SET pin. Subsequent rising edges on TRIG have no affect until the completion of the one shot and for a short rearming time (tARM) thereafter. To ensure proper operation, positive and negative TRIG pulses should be at least tWIDTH wide. The LTC6993-2 and LTC6993-4 allow the output pulse to be “retriggered”. As shown in Figure 4, the output pulse will stay high until tOUT after the last rising-edge on TRIG. Successive trigger signals can extend the pulse width indefinitely. Consequtive trigger signals must be separated by tRETRIG to be recognized. Negative Trigger Versions In addition to the retrigger option, the LTC6993 family also includes negative input (falling-edge) versions. These four combinations are detailed in Table 2. Table 2. Retrigger and Input Polarity Options DEVICE LTC6993-1 LTC6993-2 LTC6993-3 LTC6993-4 INPUT POLARITY Rising-Edge Rising-Edge Falling-Edge Falling-Edge RETRIGGER No Yes No Yes Output Polarity (POL Bit) Each variety of LTC6993 also offers the ability to invert the output, producing negative pulses. This option is programmed, along with NDIV, by the choice of DIVCODE. (The previous section describes how to program DIVCODE using the DIV pin). tWIDTH TRIG tPD OUT tOUT tOUT tOUT 69931234 F03 tPD tARM Figure 3. Non-Retriggering Timing Diagram (LTC6993-1, POL = 0) t WIDTH TRIG tPD OUT tOUT t RETRIG tPD tPD tPD tOUT tOUT 69931234 F04 Figure 4. Retriggering Timing Diagram (LTC6993-2, POL = 0) 69931234f 13 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 OPERATION Changing DIVCODE After Start-Up Following start-up, the A/D converter will continue monitoring VDIV for changes. Changes to DIVCODE will be recognized slowly, as the LTC6993 places a priority on eliminating any “wandering” in the DIVCODE. The typical delay depends on the difference between the old and new DIVCODE settings and is proportional to the master oscillator period. tDIVCODE = 16 • (∆DIVCODE + 6) • tMASTER A change in DIVCODE will not be recognized until it is stable, and will not pass through intermediate codes. A digital filter is used to guarantee the DIVCODE has settled to a new value before making changes to the output. However, if the output pulse is active during the transition, the pulse width can take on a value between the two settings. DIV 500mV/DIV TRIG 2V/DIV OUT 2V/DIV LTC6993-1 V+ = 3.3V RSET = 200k 4µs 256µs 200µs/DIV 69931234 F05a Start-Up Time When power is first applied, the power-on reset (POR) circuit will initiate the start-up time, tSTART . The OUT pin is held low during this time. The typical value for tSTART ranges from 0.5ms to 8ms depending on the master oscillator frequency (independent of NDIV): tSTART(TYP) = 500 • tMASTER During start-up, the DIV pin A/D converter must determine the correct DIVCODE before an output pulse can be generated. The start-up time may increase if the supply or DIV pin voltages are not stable. For this reason, it is recommended to minimize the capacitance on the DIV pin so it will properly track V+. Less than 100pF will not extend the start-up time. The DIVCODE setting is recognized at the end of the startup up. If POL = 1, the output will transition high. Otherwise (if POL = 0) OUT simply remains low. At this point, the LTC6993 is ready to respond to rising/falling edges on the TRIG input. V+ 512µs TRIG tSTART (TRIG IGNORED) OUT POL = 0 POL = 1 tOUT 512µs 69931234 F06 Figure 5a. DIVCODE Change from 0 to 2 DIV 500mV/DIV TRIG 2V/DIV OUT 2V/DIV Figure 6. Start-Up Timing Diagram 4µs 256µs LTC6993-1 V+ = 3.3V RSET = 200k 200µs/DIV 69931234 F05b Figure 5b. DIVCODE Change from 2 to 0 69931234f 14 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 APPLICATIONS INFORMATION Basic Operation The simplest and most accurate method to program the LTC6993 is to use a single resistor, RSET , between the SET and GND pins. The design procedure is a four step process. Step 1: Select the POL Bit Setting. The LTC6993 can generate positive or negative output pulses, depending on the setting of the POL bit. The POL bit is the DIVCODE MSB, so any DIVCODE ≥ 8 has POL = 1 and produces active-low pulses. Step 2: Select LTC6993 Version. Two input-related choices dictate the proper LTC6993 for a given application: • Is TRIG a rising or falling-edge input? • Should retriggering be allowed? Use Table 2 to select a particular variety of LTC6993. Step 3: Select the NDIV Frequency Divider Value. As explained earlier, the voltage on the DIV pin sets the DIVCODE which determines both the POL bit and the NDIV value. For a given output pulse width (tOUT), NDIV should be selected to be within the following range: tOUT t ≤ NDIV ≤ OUT 16µs 1µs (1) Step 4: Calculate and Select RSET. The final step is to calculate the correct value for RSET using the following equation: RSET = 50k tOUT • 1µs NDIV (2) Select the standard resistor value closest to the calculated value. Example: Design a one-shot circuit that satisfies the following requirements: • tOUT = 100µs • Negative Output Pulse • Rising-Edge Trigger Input • Retriggerable Input • Minimum power consumption Step 1: Select the POL Bit Setting. For inverted (negative) output pulse, choose POL = 1. Step 2: Select the LTC6993 Version. A rising-edge retriggerable input requires the LTC6993-2. Step 3: Select the NDIV Frequency Divider Value. Choose an NDIV value that meets the requirements of Equation (1), using tOUT = 100µs: 6.25 ≤ NDIV ≤ 100 Potential settings for NDIV include 8 and 64. NDIV = 8 is the best choice, as it minimizes supply current by using a large RSET resistor. POL = 1 and NDIV = 8 requires DIVCODE = 14. Using Table 1, choose R1 = 102k and R2 = 976k values to program DIVCODE = 14. Step 4: Select RSET . Calculate the correct value for RSET using Equation (2): RSET = 50k 100µs • = 625k 1µs 8 To minimize supply current, choose the lowest NDIV value. However, in some cases a higher value for NDIV will provide better accuracy (see Electrical Characteristics). Table 1 can also be used to select the appropriate NDIV values for the desired tOUT . With POL already chosen, this completes the selection of DIVCODE. Use Table 1 to select the proper resistor divider or VDIV/V+ ratio to apply to the DIV pin. 69931234f 15 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 APPLICATIONS INFORMATION Since 625k is not available as a standard 1% resistor, substitute 619k if a –0.97% shift in tOUT is acceptable. Otherwise, select a parallel or series pair of resistors such as 309k and 316k to attain a more precise resistance. The completed design is shown in Figure 7. TRIG OUT 2.25V TO 5.5V 0.1µF SET RSET 625k DIV R1 102k DIVCODE = 14 R2 976k 69931234 F07 TRIG OUT V+ V+ C1 0.1µF LTC6993 GND RMOD RSET R1 VCTRL SET DIV R2 69931234 F08 LTC6993-2 GND V+ Figure 8. Voltage-Controlled Pulse Width Digital Pulse Width Control The control voltage can be generated by a DAC (digital-toanalog converter), resulting in a digitally-controlled pulse width. Many DACs allow for the use of an external reference. If such a DAC is used to provide the VCTRL voltage, the VSET dependency can be eliminated by buffering VSET and using it as the DAC’s reference voltage, as shown in Figure 9. The DAC’s output voltage now tracks any VSET variation and eliminates it as an error source. The SET pin cannot be tied directly to the reference input of the DAC because the current drawn by the DAC’s REF input would affect the pulse width. Figure 7. 100µs Negative Pulse Generator Voltage-Controlled Pulse Width With one additional resistor, the LTC6993 output pulse width can be manipulated by an external voltage. As shown in Figure 8, voltage VCTRL sources/sinks a current through RMOD to vary the ISET current, which in turn modulates the pulse width as described in Equation (3). tOUT = NDIV • RMOD • 50kΩ 1µs RMOD VCTRL 1+ – RSET VSET (3) TRIG V+ OUT V+ V+ C1 0.1µF LTC6993 0.1µF GND R1 1/2 LTC6078 0.1µF V+ + – SET DIV R2 69931234 F09 DIN µP CLK CS/LD VCC REF VOUT RMOD N •R tOUT = DIV MOD • 50k DIN = 0 TO 4095 1µs RMOD DIN 1+ – RSET 4096 LTC1659 GND RSET Figure 9. Digitally Controlled Pulse Width 69931234f 16 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 APPLICATIONS INFORMATION ISET Extremes (Master Oscillator Frequency Extremes) When operating with ISET outside of the recommended 1.25µA to 20µA range, the master oscillator operates outside of the 62.5kHz to 1MHz range in which it is most accurate. The oscillator will still function with reduced accuracy for ISET < 1.25µA. At approximately 500nA, the oscillator will stop. Under this condition, the output pulse can still be initiated, but will not terminate until ISET increases and the master oscillator starts again. At the other extreme, it is not recommended to operate the master oscillator beyond 2MHz because the accuracy of the DIV pin ADC will suffer. Settling Time Following a 2× or 0.5× step change in ISET , the output pulse width takes approximately six master clock cycles (6 • tMASTER) to settle to within 1% of the final value. An example is shown in Figure 10, using the circuit in Figure 8. VCTRL 2V/DIV TRIG 5V/DIV OUT 5V/DIV PULSE WIDTH 2µs/DIV LTC6993-1 V+ = 3.3V DIVCODE = 0 RSET = 200k RMOD = 464k tOUT = 3µs AND 6µs 20µs/DIV 69931234 F10 Coupling Error The current sourced by the SET pin is used to bias the internal master oscillator. The LTC6993 responds to changes in ISET almost immediately, which provides excellent settling time. However, this fast response also makes the SET pin sensitive to coupling from digital signals, such as the TRIG input. Even an excellent layout will allow some coupling between TRIG and SET. Additional error is included in the specified accuracy for NDIV = 1 to account for this. Figure 11 shows that ÷1 supply variation is dependent on coupling from rising or falling trigger inputs and, to a lesser extent, output polarity. A very poor layout can actually degrade performance further. The PCB layout should avoid routing SET next to TRIG (or any other fast-edge, wide-swing signal). 1.0 0.8 0.6 0.4 DRIFT (%) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 2 RSET = 50k NDIV = 1 3 LTC6993-3 POL = 0 LTC6993-3 POL = 1 LTC6993-1 POL = 1 LTC6993-1 POL = 0 4 SUPPLY (V) 5 6 69931234 F11 Figure 11. tOUT Drift vs Supply Voltage Figure 10. Typical Settling Time 69931234f 17 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 APPLICATIONS INFORMATION Power Supply Current POWER SUPPLY CURRENT (µA) 250 The Electrical Characteristics table specifies the supply current while the part is idle (waiting to be triggered). IS(IDLE) varies with the programmed tOUT and the supply voltage. Once triggered, the instantaneous supply current increases to IS(ACTIVE) while the timing circuit is active. IS(ACTIVE) = IS(IDLE) + ∆IS(ACTIVE) The average increase in supply current ∆IS(ACTIVE) depends on the output duty cycle (or negative duty cycle, if POL = 1), since that represents the percentage of time that the circuit is active. IS(IDLE) and ∆IS(ACTIVE) can be estimated using the equations in Table 2. Figure 12 shows how the supply current increases from IS(IDLE) as the input frequency increases. The increase is smaller at higher NDIV settings. Table 2. Typical Supply Current CONDITION NDIV ≤ 64 TYPICAL IS(IDLE) V + • (NDIV • 7pF + 4pF ) tOUT + V+ + 2.2 • ISET + 50µA 500kΩ V+ = 3.3V DUTY CYCLE = fIN • tOUT ÷1, RSET = 50k 200 ÷8, RSET = 50k ÷1, RSET = 100k ÷1, RSET = 800k 150 100 50 CLOAD = 5pF RLOAD = ∞ 20 0 IDLE 60 40 DUTY CYCLE (%) 80 100 69931234 F12 Figure 12. IS(ACTIVE) vs Output Duty Cycle TYPICAL ∆IS(ACTIVE)* V+ • Duty Cycle • (NDIV • 5pF + 18pF + CLOAD ) tOUT V+ • Duty Cycle • CLOAD tOUT NDIV ≥ 512 V + • NDIV • 7pF V+ + + 1.8 • ISET + 50µA 500kΩ tOUT *Ignoring resistive loads (assumes RLOAD = ∞) 69931234f 18 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 APPLICATIONS INFORMATION Supply Bypassing and PCB Layout Guidelines The LTC6993 is an accurate monostable multivibrator when used in the appropriate manner. The part is simple to use and by following a few rules, the expected performance is easily achieved. Adequate supply bypassing and proper PCB layout are important to ensure this. Figure 13 shows example PCB layouts for both the SOT-23 and DCB packages using 0603 sized passive components. The layouts assume a two layer board with a ground plane layer beneath and around the LTC6993. These layouts are a guide and need not be followed exactly. 1. Connect the bypass capacitor, C1, directly to the V+ and GND pins using a low inductance path. The connection from C1 to the V+ pin is easily done directly on the top layer. For the DCB package, C1’s connection to GND is also simply done on the top layer. For the SOT-23, OUT can be routed through the C1 pads to allow a good C1 GND connection. If the PCB design rules do not allow that, C1’s GND connection can be accomplished through multiple vias to the ground plane. Multiple vias for both the GND pin connection to the ground plane and the C1 connection to the ground plane are recommended to minimize the inductance. Capacitor C1 should be a 0.1µF ceramic capacitor. 2. Place all passive components on the top side of the board. This minimizes trace inductance. 3. Place RSET as close as possible to the SET pin and make a direct, short connection. The SET pin is a current summing node and currents injected into this pin directly modulate the output pulse width. Having a short connection minimizes the exposure to signal pickup. 4. Connect RSET directly to the GND pin. Using a long path or vias to the ground plane will not have a significant affect on accuracy, but a direct, short connection is recommended and easy to apply. 5. Use a ground trace to shield the SET pin. This provides another layer of protection from radiated signals. 6. Place R1 and R2 close to the DIV pin. A direct, short connection to the DIV pin minimizes the external signal coupling. TRIG OUT V+ LTC6993 GND C1 0.1µF V+ R1 SET RSET V+ R1 V+ DIV R2 SET RSET C1 OUT GND TRIG DIV R2 C1 TRIG GND SET RSET R2 69931234 F13 V+ OUT V+ DIV R1 DCB PACKAGE TSOT-23 PACKAGE Figure 13. Supply Bypassing and PCB Layout 69931234f 19 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 TYPICAL APPLICATIONS Missing Pulse Detector 25kHz INPUT 3.3V 0.1µF R1 102k SET RSET 402k DIV R2 976k 69931234 TA02a TRIG OUT V+ LTC6993-2 GND TRIG 2V/DIV OUT 2V/DIV 64µs DIVCODE = 14 (NDIV = 8, POL = 1) 50µs/DIV 69931234 TA02b Use retriggerable one shot with output inverted. Output remains low as long as retrigger occurs within tOUT = 64µs. 1.5ms Radio Control Servo Reference Pulse Generator 5V R7 10k RESET = OPEN RUN = GND (CLOSED) 20ms FRAME RATE GENERATOR RST OUT 5V V+ R4 976k R5 102k R6 10k C1 0.01µF 1.5ms REFERENCE PULSE TRIG OUT 5V R1 1M SET R8 143k 1.5ms CAL TRIM DIV R2 280k 69931234 TA03 20ms PERIOD 1.5ms PULSE LTC6991 GND LTC6993-1 GND V+ C2 0.01µF SET R3 121k DIV Pulse Delay Generator 100µs DELAY GENERATOR PULSE IN TRIG OUT 5V R4 182k SET R6 78.7k DIV R5 976k R3 61.9k C1 0.01µF V+ 10µs OUTPUT PULSE GENERATOR TRIG OUT 5V R1 976k SET DIV R2 102k C2 0.1µF V+ OUT LTC6993-1 GND LTC6993-1 GND 10µs PULSE IN 100µs DELAY 10µs PULSE OUT 69931234f 20 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 TYPICAL APPLICATIONS RC Servo Pulse Generator Controlled Retrigger Lockout Time Interval 1.5ms PULSE GENERATOR TRIG OUT 5V R1 1M R2 280k C2 0.1µF TRIGGER PULSE IN 1.5ms PULSE OUT 20ms RETRIGGER LOCKOUT V+ PULSE OUT R9 10k TRIGGER LTC6993-1 GND M1 2N7002 SET R3 147k DIV 20ms RETRIGGER LOCKOUT INTERVAL OUT R5 100k 5V 0.1µF R6 1M R7 392k V + TRIG RETRIGGER LOCKOUT TIME LTC6993-1 GND DIV SET R4 243k 69931234 TA05 Staircase Generator with Reset R8 4.99k PULSE FREQUENCY-TO-VOLTAGE CONVERTER 5V 0.1µF D1 1N4148 R11 2k C1 1µF R9 100k RETRIGGERABLE STAIRCASE RESET PULSE GENERATOR TRIG OUT 5V R1 280k R2 1M C2 0.1µF V+ R7 10k 5V 0.1µF PULSES IN R6 20k U4 2N7002 RESET STAIRCASE RESET RAMP RESET LTC6993-2 GND R3 147k SET DIV + STAIRCASE OUT PULSES IN RESETS AFTER 1.5ms IF NO PULSES APPLIED 69931234 TA06 + R10 10k U2 LT1490 – U3 LT1490 STAIRCASE OUT VOUT – 69931234f 21 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 TYPICAL APPLICATIONS Pulse Stretcher 5V R4 4.99k U2 LT1009 2.5V Q4 2N2219A R1 10k VOLTAGE VARIABLE OUTPUT PULSE WIDTH TRIG 5V 0.1µF OUT V+ PULSE OUT STRETCHED PULSE OUT 5V LTC6993-3 GND Q1 2N2907 Q2 2N2907 RAMP R6 C1 10k 2200pF U4 LT1638 R16 140k R13 113k R14 976k R15 102k C4 0.1µF Q3 2N2219A R7 10k RAMP VOLTAGE PROPORTIONAL TO INPUT PULSE WIDTH PULSE IN 1µs TO 10µs INPUT PULSE WIDTH TRIG OUT V+ 500µs RAMP RESET TIMER 5V R2 182k R5 976k 69931234 TA07 LTC6993-1 GND R3 392k SET DIV On-Time Programmable Pulsed Solenoid Driver 24V 5 SECONDS ON TRIGGER IN TRIGGER TRIG OFF OUT + D1 1N4004 R4 2k 5V R1 1M R2 887k 69931234 TA08 100mA SOLENOID DANFOSS 042 N024D TYPE AK024D Q1 2N2219A LTC6993-1 GND V C2 0.1µF R3 118k R3 118k SET DIV 22 + C2 0.1µF ENABLE PULSES – SET DIV Safety Time-Out Relay Driver TIMED (5s) TURN-OFF AFTER LOSS OF INPUT PULSES RUN RESET TRIG OUT V+ R1 1M SET DIV R2 887k 69931234 TA09 12V L D1 1N4148 R4 15k 5V C2 0.1µF C NO 1 COTO 1022 RELAY 9001-12-01 Q1 2N2219A LTC6993-2 GND 69931234f LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 PACKAGE DESCRIPTION (Reference LTC DWG # 05-08-1715 Rev A) 2.00 ±0.10 (2 SIDES) 0.70 ±0.05 R = 0.115 TYP 0.40 ± 0.10 4 6 DCB Package 6-Lead Plastic DFN (2mm × 3mm) R = 0.05 TYP 3.55 ±0.05 1.65 ±0.05 (2 SIDES) PACKAGE OUTLINE PIN 1 BAR TOP MARK (SEE NOTE 6) 3.00 ±0.10 (2 SIDES) 1.65 ± 0.10 (2 SIDES) PIN 1 NOTCH R0.20 OR 0.25 × 45° CHAMFER 3 1 (DCB6) DFN 0405 2.15 ±0.05 0.25 ± 0.05 0.50 BSC 1.35 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.200 REF 0.75 ±0.05 0.25 ± 0.05 0.50 BSC 1.35 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE (Reference LTC DWG # 05-08-1636) 0.62 MAX 0.95 REF 2.90 BSC (NOTE 4) S6 Package 6-Lead Plastic TSOT-23 1.22 REF 3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.95 BSC 0.80 – 0.90 0.30 – 0.45 6 PLCS (NOTE 3) 0.20 BSC DATUM ‘A’ 1.00 MAX 0.01 – 0.10 0.30 – 0.50 REF NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 0.09 – 0.20 (NOTE 3) 1.90 BSC S6 TSOT-23 0302 REV B 69931234f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 TYPICAL APPLICATION Consecutive Test Sequencer START TEST SEQUENCE 2s TO 30s DELAY TRIG OUT 5V R10 25k DELAY ADJUST 30s R9 274k 2s LTC6994-1 GND SET R1 63.4k V+ DIV 5V 0.1µF R2 1000k R3 887k DELAY TRIG OUT LTC6993-1 GND SET R6 191k V+ DIV 5V 0.1µF TEST 1 TRIG OUT LTC6993-3 GND SET R7 191k V+ DIV 5V 0.1µF TEST 2 TRIG OUT LTC6993-3 GND SET R8 191k 69931234 TA10 TEST 3 5V 0.1µF R5 1000k R4 681k V+ DIV SHARED DIV PIN BIASING FOR EQUAL ONE-SHOT TIMERS START DELAY TEST 1 TEST 2 TEST 3 ONE SECOND DURATION SEQUENTIAL TEST PULSES AFTER AN ADJUSTABLE DELAY TIME RELATED PARTS PART NUMBER LTC1799 LTC6900 LTC6906/LTC6907 LTC6930 LTC6990 LTC6991 LTC6992 LTC6994 DESCRIPTION 1MHz to 33MHz ThinSOT Silicon Oscillator 1MHz to 20MHz ThinSOT Silicon Oscillator 10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillator Fixed Frequency Oscillator, 32.768kHz to 8.192MHz TimerBlox: Voltage-Controlled Silicon Oscillator TimerBlox: Resettable Low Frequency Oscillator TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM) TimerBlox: Delay Block/Debouncer COMMENTS Wide Frequency Range Low Power, Wide Frequency Range Micropower, ISUPPLY = 35µA at 400kHz 0.09% Accuracy, 110µs Start-Up Time, 105µA at 32kHz Fixed-Frequency or Voltage-Controlled Operation Clock Periods up to 9.5 hours Simple PWM with Wide Frequency Range Delay Rising Edge, Falling Edge or Both Edges 69931234f 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● LT 1010 • PRINTED IN USA FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORA TION 2010