LTM2220IV-AA-PBF

LTM2220-AA 12-Bit, 170Msps ADC FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION The LTM®2220-AA is a 170Msps sampling 12-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTM2220-AA is perfect for demanding communications applications with AC performance that includes 66.2dB SNR and 84dB spurious free dynamic range. DC specs include ±0.5LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The CLK+ and CLK- inputs may be driven differentially or single ended with a sine wave, PECL, TTL or CMOS inputs. A clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. The LTM2220-AA is pin compatible with the AD9430 when used with LVDS outputs, 2’s complement output format and the 1.536VPP input range. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Pin Compatible with the AD9430 Sample Rate: 170Msps 66.2dB SNR, 84dB SFDR No Missing Codes Single 3.3V supply Power Dissipation: 1050mW LVDS Digital Outputs 1.536VPP Input Range Clock Duty Cycle Stabilizer Out-of-Range Indicator Data Ready Output Clock Integrated Bypass Capacitors 100-Pin SiPLGA Package APPLICATIONS ■ ■ Wireless and Wired Broadband Communication Spectral Analysis TYPICAL APPLICATION 3.3V AVDD REFERENCE 3.3V DRVDD + ANALOG INPUT INPUT S/H – 12-BIT PIPELINED ADC CORE CORRECTION LOGIC OUTPUT DRIVERS D11 • • • D0 LVDS OUTPUTS DRGND CLOCK/DUTY CYCLE CONTROL AGND CLOCK INPUT 2220 TA01 2220aaf 1 LTM2220-AA ABSOLUTE MAXIMUM RATINGS AVDD = DRVDD (Notes 1, 2) Supply Voltage (AVDD, DRVDD) .................................4V Analog Input Voltage (Note 3) .... -0.3V to (AVDD + 0.3V) Digital Input Voltage................... -0.3V to (AVDD + 0.3V) Digital Output Voltage ............. -0.3V to (DRVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range ..................-40°C to 85°C Storage Temperature Range....................-65°C to 125°C PACKAGE/ORDER INFORMATION TOP VIEW DRGND DRVDD AGND AGND AGND AGND AGND AGND AGND AGND AVDD AVDD AVDD AVDD AVDD AVDD AVDD D11+ D11– D10+ D10– OR+ OR– D9+ D9– 75 DRVDD 74 DRGND 73 D8+ 72 D8– 71 D7+ 70 D7– 69 D6+ 68 D6– AGND AGND 67 DRGND 66 D5+ 65 D5– 64 DCO+ 63 DCO– 62 DRVDD 61 DRGND AGND 60 D4+ AGND 59 D4– 58 D3+ 57 D3– 56 D2+ 55 D2– 54 DRVDD 53 DRGND 52 D1+ 51 D1– 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC CLK+ CLK– NC NC NC NC NC DRGND D0– AGND AVDD AVDD AVDD AGND AGND AGND AVDD AGND AGND AVDD AVDD AGND DRVDD D0+ 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC NC AGND NC NC NC AVDD AGND 1 2 3 4 5 6 7 8 9 NC 10 NC 11 AGND 12 AGND 13 AVDD 14 AVDD 15 AGND 16 AGND 17 AVDD 18 AVDD 19 AGND 20 VIN+ 21 VIN– 22 AGND 23 AVDD 24 AGND 25 SiPLGA PACKAGE 100-LEAD (16mm × 16mm) TJMAX = 125°C, θJA = 20°C/W EXPOSED PADS ARE AGND ORDER PART NUMBER LTM2220IV-AA#PBF Consult LTC Marketing for parts specified with wider operating temperature ranges. LGA PART MARKING LTM2220V-AA 2220aaf 2 LTM2220-AA CONVERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error (Note 6) (Note 5) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS ● ● ● MIN 12 –1.5 –1 –35 TYP ±0.5 ±0.3 ±3 ±0.5 MAX 1.5 1 35 UNITS Bits LSB LSB mV %FS ANALOG INPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER Differential Input Range Common Mode Input Range Lower –3dB Frequency Upper –3dB Frequency Sample and Hold Jitter RS = 75Ω SYMBOL VIN VIN, CM fL fH tJITTER CONDITIONS VIN+ – VIN– (VIN+ + VIN–)/2 ● ● MIN 0 TYP 1.536 MAX 3.6 UNITS V V kHz MHz psRMS 1.6 195 0.2 DYNAMIC ACCURACY The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) PARAMETER Signal-to-Noise Ratio Signal to Noise Plus Distortion Ratio Spurious Free Dynamic Range: 2nd or 3rd Harmonic Spurious Free Dynamic Range: 4th Harmonic or Higher Intermodulation Distortion SYMBOL SNR SINAD SFDR SFDR IMD CONDITIONS 10MHz Input 70MHz Input 10MHz Input 70MHz Input 10MHz Input 70MHz Input 10MHz Input 70MHz Input fIN1 = 138MHz, fIN2 = 140MHz ● ● ● ● MIN 63.5 63.2 70 78 TYP 66.2 66.1 66.1 65.9 84 84 90 90 81 MAX UNITS dB dB dB dB dB dB dB dB dB 2220aaf 3 LTM2220-AA DIGITAL INPUTS AND OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER Differential Input Voltage Common Mode Input Voltage Input Resistance Input Capacitance Differential Output Voltage Output Common Mode Voltage (Note 7) 100Ω Load ● ● SYMBOL VID VICM RIN CIN VOD VOS CONDITIONS ● MIN 0.2 1.1 TYP MAX UNITS V CLOCK INPUTS (CLK+, CLK–) Internally Set Externally Set 1.6 1.6 6 3 247 1.125 350 1.250 454 1.375 V V kΩ pF mV V ● 2.5 DIGITAL LOGIC OUTPUTS POWER REQUIREMENTS SYMBOL AVDD DRVDD IAVDD IDVDD PDISS PARAMETER Analog Supply Voltage Digital Supply Voltage Analog Supply Current Digital Supply Current Power Dissipation The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS (Note 8) (Note 8) ● ● ● ● ● MIN 3.1 3.0 TYP 3.3 3.3 264 55 1050 MAX 3.5 3.6 288 70 1182 UNITS V V mA mA mW TIMING CHARACTERISTICS SYMBOL fS tL tH tAP tD tC PARAMETER Sampling Frequency CLK Low Time CLK High Time Sample-and-Hold Aperture Delay CLK to DATA Delay CLK to DCO Delay DATA to DCO Skew Rise Time Fall Time Pipeline Latency The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS ● MIN 1 2 2 1.5 1.5 –0.6 ● ● TYP 2.94 2.94 0 3 3 0 0.5 0.5 5 MAX 170 500 500 4.3 4.3 0.6 UNITS MHz ns ns ns ns ns ns ns ns Cycles (Note 7) (Note 7) (Note 7) (Note 7) (tC – tD), (Note 7) ● ● ● Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with AGND and DRGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: AVDD = DRVDD = 3.3V, fSAMPLE =170MHz, differential CLK+/CLK= 2Vpp sine wave, differential analog inputs, unless otherwise noted. Note 5: Integral nonlinearity is defined as the deviation of a code from a “best fit straight line” fit to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from -0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions. 2220aaf 4 LTM2220-AA TYPICAL PERFORMANCE CHARACTERISTICS 8192 Point FFT, fIN = 5MHz, –1dB, 170Msps 0 –10 –20 –30 AMPLITUDE (dB) AMPLITUDE (dB) –40 –50 –60 –70 –80 –90 –100 –110 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 2220 G01 8192 Point FFT, fIN = 30MHz, –1dB, 170Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 2220 G02 8192 Point FFT, fIN = 70MHz, –1dB, 170Msps 0 –10 –20 –30 AMPLITUDE (dB) –40 –50 –60 –70 –80 –90 –100 –110 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 2220 G03 8192 Point FFT, fIN = 140MHz, –1dB, 170Msps 0 –10 –20 –30 AMPLITUDE (dB) ERROR (LSB) –40 –50 –60 –70 –80 –90 –100 –110 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 2220 G04 INL Error 1.0 0.8 0.6 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 – 1.0 0 1024 3072 2048 OUTPUT CODE 4096 2220 G05 DNL Error 1.0 0.8 0.6 0.4 ERROR (LSB) 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 – 1.0 0 1024 3072 2048 OUTPUT CODE 4096 2220 G06 2220aaf 5 LTM2220-AA PIN FUNCTIONS NC (Pins 1, 2, 3, 5, 6, 7, 10, 11, 33, 42, 43, 44, 45, 46): Pin is not connected internally. AGND (Pins 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 32, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100): Analog Ground. AVDD (Pins 8, 14, 15, 18, 19, 24, 27, 28, 29, 34, 39, 40, 88, 89, 90, 94, 95, 98, 99): 3.3V Analog Supply. VIN VIN + (Pin 21): Positive Analog Input. - (Pin 22): Negative Analog Input. D3+ (Pin 58): D3 True Output Bit. D4- (Pin 59): D4 Complement Output Bit. D4+ (Pin 60): D4 True Output Bit. DCO- (Pin 63): Data Clock Output Complement. DCO+ (Pin 64): Data Clock Output True. D5- (Pin 65): D5 Complement Output Bit. D5+ (Pin 66): D5 True Output Bit. D6- (Pin 68): D6 Complement Output Bit. D6+ (Pin 69): D6 True Output Bit. D7- (Pin 70): D7 Complement Output Bit. D7+ (Pin 71): D7 True Output Bit. D8- (Pin 72): D8 Complement Output Bit. D8+ (Pin 73): D8 True Output Bit. D9- (Pin 76): D9 Complement Output Bit. D9+ (Pin 77): D9 True Output Bit. D10- (Pin 78): D10 Complement Output Bit. D10+ (Pin 79): D10 True Output Bit. D11- (Pin 80): D11 Complement Output Bit (MSB). D11+ (Pin 81): D11 True Output Bit (MSB). OR- (Pin 84): Overrange Output Complement. OR+ (Pin 85): Overrange Output True. GND (Exposed Pads): The exposed pads on the bottom of the package need to be soldered to Analog Ground. CLK+ (Pin 36): Clock Input. The input sample starts on the positive edge. CLK- (Pin 37): Clock Complement Input. Conversion starts on the negative edge. Bypass to ground with a 0.1µF ceramic for a single-ended clock. DRVDD (Pins 47, 54, 62, 75, 83): 3.3V Digital Output Driver Supply. DRGND (Pins 48, 53, 61, 67, 74, 82): Digital Output Driver Ground. D0- (Pin 49): D0 Complement Output Bit (LSB). D0+ (Pin 50): D0 True Output Bit (LSB). D1- (Pin 51): D1 Complement Output Bit. D1+ (Pin 52): D1 True Output Bit. D2- (Pin 55): D2 Complement Output Bit. D2+ (Pin 56): D2 True Output Bit. D3- (Pin 57): D3 Complement Output Bit. TIMING DIAGRAM tAP ANALOG INPUT N tH tL CLK– CLK+ tD D0-D11, OR tC N–5 N–4 N–3 N–2 N–1 N+1 N+2 N+3 N+4 DCO– DCO+ 2220 TD01 2220aaf 6 LTM2220-AA APPLICATIONS INFORMATION DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to Total Harmonic Distortion (THD). IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Lower and Upper –3dB Frequencies The input frequencies at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Note that the analog input has a bandpass response. Aperture Delay Time The time from when a rising CLK+ equals the CLK– voltage to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) CONVERTER OPERATION The LTM2220-AA is a CMOS pipelined multistep converter. The converter has five pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The clock input is differential for improved common mode noise immunity. The LTM2220-AA is pin compatible with the AD9430 when used with LVDS outputs, 2’s complement output format and the 1.536VPP input range. The LTM2220-AA package contains power supply bypass capacitors, which makes the part easy to use since it is insensitive to the PC board layout. 2220aaf 7 LTM2220-AA APPLICATIONS INFORMATION SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 1 shows an equivalent circuit for the LTM2220-AA CMOS differential sample-and-hold. The analog inputs are AC coupled to the sample and hold circuit through 0.1µF capacitors and 1k bias resistors. The 25Ω resistor and 0.5pF capacitor serve two purposes: isolating the drive circuitry from the sample and hold charging glitches and limiting the wideband noise at the converter input. Single-Ended Input For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.384V around a common mode voltage of between 0V and 3.6V. LTM2220-AA VDD 0.1µF VIN+ 25Ω 15Ω CSAMPLE 1.6pF Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTM2220-AA can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 2 shows the LTM2220-AA being driven by an RF transformer with a center tapped secondary. The secondary center tap is grounded as shown, but it can also be connected to any DC bias voltage from 0V to 3.6V. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Driving the Clock Inputs The noise performance of the LTM2220-AA can depend on the encode signal quality as much as on the analog input. The CLK+/CLK– inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. 0.1µF ANALOG INPUT T1 1:1 25Ω LTM2220-AA 25Ω VIN– T1 = M/A-COM ETC1-1T OR EQUIVALENT 2220 F02 0.5pF 0.1µF VIN– 1k 25Ω 1k 15Ω VDD CSAMPLE 1.6pF VDD VREF 1.6V 6k CLK+ CLK– 6k 1.6V 2220 F01 VIN+ Figure 2. Single-Ended to Differential Conversion Using a Transformer Figure 1. Equivalent Input Circuit 2220aaf 8 LTM2220-AA APPLICATIONS INFORMATION Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies) take the following into consideration: 1. Differential drive should be used. 2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3. If the ADC is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The clock inputs have a common mode range of 1.1V to 2.5V. Each input may be driven from ground to VDD for single-ended drive. LTM2220-AA VDD 0.1µF TO INTERNAL ADC CIRCUITS 1.6V BIAS 6k CLK+ 0.1µF CLOCK INPUT 50Ω 1:4 VDD 1.6V BIAS D0 6k CLK– Q0 83Ω 2220 F03 2220 F04 Maximum and Minimum Encode Rates The maximum encode rate for the LTM2220-AA is 170Msps. For the ADC to operate properly, the encode signal should have a 50% (±20%) duty cycle. Each half cycle must have at least 2ns for the ADC internal circuitry to have enough settling time for proper operation. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. The lower limit of the LTM2220-AA sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTM2220-AA is 1Msps. VTHRESHOLD = 1.6V CLK+ 1.6V CLK– LTM2220-AA VDD Figure 4. Single-Ended CLK Drive, Not Recommended for Low Jitter 3.3V MC100LVELT22 3.3V 130Ω Q0 130Ω CLK+ CLK– LTM2220-AA 83Ω 2220 F05 Figure 3. Transformer Driven CLK+/CLK– Figure 5. CLK Drive Using a CMOS to PECL Translator 2220aaf 9 LTM2220-AA APPLICATIONS INFORMATION DIGITAL OUTPUTS Table 1. Output Codes vs Input Voltage VIN+ – VIN– >+0.768000V +0.768000V +0.767625V +0.000375V 0.000000V –0.000375V –0.000750V –0.767625V –0.768000V