LTM9001IV-AA

LTM9001-Ax/LTM9001-Bx 16-Bit IF/Baseband Receiver Subsystem FEATURES n n n DESCRIPTION The LTM®9001 is an integrated system in a package (SiP) that includes a high-speed 16-bit A/D converter, matching network, anti-aliasing filter and a low noise, differential amplifier with fixed gain. It is designed for digitizing wide dynamic range signals with an intermediate frequency (IF) range up to 300MHz. The amplifier allows either ACor DC-coupled input drive. A lowpass or bandpass filter network can be implemented with various bandwidths. Contact Linear Technology regarding semi-custom configurations. The LTM9001 is perfect for IF receivers in demanding communications applications, with AC performance that includes 72dBFS noise floor and 82dB spurious free dynamic range (SFDR) at 162.5MHz (LTM9001-AA). The digital outputs can be either differential LVDS or singleended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.3V. The differential ENC+ and ENC– inputs may be driven with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles. n n n n n n n n n Integrated 16-Bit, High-Speed ADC, Passive Filter and Fixed Gain Differential Amplifier Up to 300MHz IF Range Lowpass and Bandpass Filter Versions Low Noise, Low Distortion Amplifiers Fixed Gain: 8dB, 14dB, 20dB or 26dB 50Ω, 200Ω or 400Ω Input Impedance 75dB SNR, 83dB SFDR (LTM9001-AD) Integrated Bypass Capacitance, No External Components Required Optional Internal Dither Optional Data Output Randomizer LVDS or CMOS Outputs 3.3V Single Supply Power Dissipation: 1.65W Clock Duty Cycle Stabilizer 11.25mm × 11.25mm × 2.32mm LGA Package APPLICATIONS n n n n Telecommunications High Sensitivity Receivers Cellular Base Stations Spectrum Analyzers L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION Simplified IF Receiver Channel VCC SENSE VDD = 3.3V 64k Point FFT, fIN = 162.4MHz, –1dBFS, PGA = 1 0 LTM9001 0VDD = 0.5V TO 3.6V AMPLITUDE (dBFS) –20 –40 –60 –80 –100 OGND –120 HD3 HD2 LTM9001-AA D15 IN– SAW LO IN+ DIFFERENTIAL FIXED GAIN AMPLIFIER GND ENC+ ENC– ADC CONTROL PINS ANTI-ALIAS FILTER 16-BIT 130Msps ADC • • • RF D0 CLKOUT OF CMOS OR LVDS 9001 TA01 0 10 50 20 40 30 FREQUENCY (MHz) 60 9001 TA01b 9001fb 1 LTM9001-Ax/LTM9001-Bx ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ALL ELSE = GND TOP VIEW CONTROL 1 J IN– IN+ H G F VCC E DNC D ENC+ C ENC– B A CONTROL VDD OGND OVDD OGND OVDD 2 3 4 DATA 5 6 7 8 9 OGND Supply Voltage (VCC) ................................ –0.3V to 3.6V Supply Voltage (VDD) ................................... –0.3V to 4V Digital Output Supply Voltage (OVDD) .......... –0.3V to 4V Analog Input Current (IN+, IN–) ............................±10mA Digital Input Voltage (Except AMPSHDN) ................. –0.3V to (VDD + 0.3V) Digital Input Voltage (AMPSHDN)..............................–0.3V to (VCC + 0.3V) Digital Output Voltage ................–0.3V to (OVDD + 0.3V) Operating Temperature Range LTM9001C................................................ 0°C to 70°C LTM9001I.............................................–40°C to 85°C Storage Temperature Range...................–45°C to 125°C Maximum Junction Temperature........................... 125°C LGA PACKAGE TJMAX = 125°C, JA = 15°C/W, JCtop = 19°C/W JA DERIVED FROM 60mm 70mm PCB WITH 4 LAYERS WEIGHT = 0.71g ORDER INFORMATION LEAD FREE FINISH LTM9001CV-AA#PBF LTM9001IV-AA#PBF LTM9001CV-AD#PBF LTM9001IV-AD#PBF LTM9001CV-BA#PBF LTM9001IV-BA#PBF PART MARKING* LTM9001V-AA LTM9001V-AA LTM9001V-AD LTM9001V-AD LTM9001V-BA LTM9001V-BA PACKAGE DESCRIPTION 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL GDIFF PARAMETER Gain CONDITIONS DC, LTM9001-AA fIN = 162.5MHz (Note 3) DC, LTM9001-AD fIN = 70MHz (Note 3) DC, LTM9001-BA fIN = 140MHz (Note 3) GTEMP Gain Temperature Drift VIN = Maximum, (Note 3) l l l ELECTRICAL CHARACTERISTICS MIN 19.1 13.4 7.1 TYP 19.7 19 14 13.5 8.2 7.8 2 MAX 20.3 14.7 9.4 UNITS dB dB dB dB dB dB mdB/°C 9001fb 2 LTM9001-Ax/LTM9001-Bx The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL VINCM VIN PARAMETER Input Common Mode Voltage Range Input Voltage Range at –1dBFS CONDITIONS (IN+ + IN–)/2 LTM9001-AA at 162.5MHz LTM9001-AD at 70MHz LTM9001-BA at 140MHz LTM9001-AA LTM9001-AD LTM9001-BA Includes Parasitic Including Amplifier and ADC (LTM9001-AA) Including Amplifier and ADC (LTM9001-AD) Including Amplifier and ADC (LTM9001-BA) Including Amplifier and ADC Internal Reference External Reference 0V < SENSE < VDD l l l l ELECTRICAL CHARACTERISTICS MIN TYP 1.0–1.6 233 424 820 200 200 400 1 MAX UNITS V mVP-P mVP-P mVP-P Ω Ω Ω pF RINDIFF Differential Input Impedance CINDIFF VOS Differential Input Capacitance Offset Error (Note 6) –8 –11 –20 –3.2 –6 –10 ±10 ±30 ±15 60 –0.5 –0.5 –0.5 mV mV mV μV/°C ppm/°C ppm/°C dB Offset Drift Full-Scale Drift CMRR ISENSE IMODE ILVDS tAP tJITTER Common Mode Rejection Ratio SENSE Input Leakage Current MODE Pin Pull-Down Current to GND LVDS Pin Pull-Down Current to GND Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter –3 10 10 1 70 3 μA μA μA ns fsRMS CONVERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Transition Noise The l indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. CONDITIONS l MIN 16 l l l TYP ±2.4 ±0.3 1 MAX ±8 ±10 ±1 UNITS Bits LSB LSB LSB LSBRMS Differential Input LTM9001-Ax (Notes 5, 7) Differential Input LTM9001-BA (Notes 5, 7) Differential Input (Notes 5, 7) External Reference DYNAMIC ACCURACY SYMBOL SNR PARAMETER Signal-to-Noise Ratio The l indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) CONDITIONS 162.5MHz Input (PGA = 0) LTM9001-AA 162.5MHz Input (PGA = 1) LTM9001-AA 70MHz Input (PGA = 0) LTM9001-AD 70MHz Input (PGA = 1) LTM9001-AD 140MHz Input (PGA = 0) LTM9001-BA 140MHz Input (PGA = 1) LTM9001-BA l l l MIN 67.2 71.2 67 TYP 72 68.5 75 72 69.2 67.2 MAX UNITS dBFS dBFS dBFS dBFS dBFS dBFS 9001fb 3 LTM9001-Ax/LTM9001-Bx DYNAMIC ACCURACY SYMBOL SFDR PARAMETER Spurious Free Dynamic Range, 2nd or 3rd Harmonic The l indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) CONDITIONS 162.5MHz Input (PGA = 0) LTM9001-AA 162.5MHz Input (PGA = 1) LTM9001-AA 70MHz Input (PGA = 0) LTM9001-AD 70MHz Input (PGA = 1) LTM9001-AD 140MHz Input (PGA = 0) LTM9001-BA 140MHz Input (PGA = 1) LTM9001-BA l l l MIN 72 72.6 64 TYP 78 82 83 86 72 82 95 95 95 98 95 104 71.4 68 74.3 72 67.5 66.4 90 93 85 87 91 92 MAX UNITS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dB dB dB dBm dBm dBm SFDR Spurious Free Dynamic Range 4th or Higher 162.5MHz Input (PGA = 0) LTM9001-AA 162.5MHz Input (PGA = 1) LTM9001-AA 70MHz Input (PGA = 0) LTM9001-AD 70MHz Input (PGA = 1) LTM9001-AD 140MHz Input (PGA = 0) LTM9001-BA 140MHz Input (PGA = 1) LTM9001-BA l l l 86 84.5 86 S/(N+D) Signal-to-Noise Plus Distortion Ratio 162.5MHz Input (PGA = 0) LTM9001-AA 162.5MHz Input (PGA = 1) LTM9001-AA 70MHz Input (PGA = 0) LTM9001-AD 70MHz Input (PGA = 1) LTM9001-AD 140MHz Input (PGA = 0) LTM9001-BA 140MHz Input (PGA = 1) LTM9001-BA l l l 67 71.2 64 SFDR Spurious Free Dynamic Range at –25dBFS, Dither “OFF” Spurious Free Dynamic Range at –15dBFS, Dither “OFF” Spurious Free Dynamic Range at –15dBFS, Dither “OFF” 162.5MHz Input (PGA = 0) LTM9001-AA 162.5MHz Input (PGA = 1) LTM9001-AA 70MHz Input (PGA = 0) LTM9001-AD 70MHz Input (PGA = 1) LTM9001-AD 140MHz Input (PGA = 0) LTM9001-BA 140MHz Input (PGA = 1) LTM9001-BA 162.5MHz Input (PGA = 0) LTM9001-AA 162.5MHz Input (PGA = 1) LTM9001-AA 70MHz Input (PGA = 0) LTM9001-AD 70MHz Input (PGA = 1) LTM9001-AD 140MHz Input (PGA = 0) LTM9001-BA 140MHz Input (PGA = 1) LTM9001-BA fIN = 162.5MHz LTM9001-AA fIN = 70MHz LTM9001-AD fIN = 140MHz LTM9001-BA fIN = 162.5MHz LTM9001-AA fIN = 70MHz LTM9001-AD fIN = 140MHz LTM9001-BA l l l SFDR Spurious Free Dynamic Range at –25dBFS, Dither “ON” Spurious Free Dynamic Range at –15dBFS, Dither “ON” Spurious Free Dynamic Range at –15dBFS, Dither “ON” 90 90 90 95 100 92 88 95 96 –78 –84 –84 24 26.5 29.2 IMD3 Third Order Intermodulation Distortion; 1MHz Tone Spacing, 2 Tones at –7dBFS Equivalent Third Order Input Intercept Point, 2 Tone IIP3 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL VID VICM RIN CIN PARAMETER Differential Input Voltage Common Mode Input Voltage Input Resistance Input Capacitance (Note 7) Internally Set Externally Set CONDITIONS l DIGITAL INPUTS AND OUTPUTS MIN 0.2 TYP MAX UNITS V Encode Inputs (ENC+, ENC–) 1.6 1.2 100 3 3.1 V V Ω pF 9001fb 4 LTM9001-Ax/LTM9001-Bx The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL VIH VIL IIN CIN VIH VIL IIH IIL CIN OVDD = 3.3V VOH VOL ISOURCE ISINK OVDD = 2.5V VOH VOL OVDD = 1.8V VOH VOL Standard LVDS VOD VOS Low Power LVDS VOD VOS Differential Output Voltage Output Common Mode Voltage 100Ω Differential Load 100Ω Differential Load l l DIGITAL INPUTS AND OUTPUTS PARAMETER High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance High Level Input Voltage Low Level Input Voltage Input High Current Input Low Current Input Capacitance CONDITIONS VDD = 3.3V VDD = 3.3V VIN = 0V to VDD (Note 7) VCC = 3.3V VCC = 3.3V VIN = 2V VIN = 0.8V (Note 7) l l l l l MIN 2 TYP MAX UNITS V Logic Inputs (DITH, PGA, ADCSHDN, RAND) 0.8 ±10 1.5 2 0.8 1.3 0.1 1.5 V μA pF V V μA μA pF Logic Inputs (AMPSHDN) Logic Outputs (CMOS Mode) High Level Output Voltage Low Level Output Voltage Output Source Current Output Sink Current High Level Output Voltage Low Level Output Voltage High Level Output Voltage Low Level Output Voltage VDD = 3.3V, IO = –10μA VDD = 3.3V, IO = –200μA VDD = 3.3V, IO = 10μA VDD = 3.3V, IO = 1.6mA VOUT = 0V VOUT = 3.3V VDD = 3.3V, IO = –200μA VDD = 3.3V, IO = 1.6mA VDD = 3.3V, IO = –200μA VDD = 3.3V, IO = 1.6μA 3.299 3.29 0.01 0.1 –50 50 2.49 0.1 1.79 0.1 0.4 V V V V mA mA V V V V l l 3.1 Logic Outputs (LVDS Mode) Differential Output Voltage Output Common Mode Voltage 100Ω Differential Load 100Ω Differential Load l l 247 1.125 125 1.125 350 1.2 175 1.2 454 1.375 250 1.375 mV V mV V POWER REQUIREMENTS SYMBOL VDD VCC ICC PSHDN PARAMETER ADC Analog Supply Voltage Amplifier Supply Voltage Amplifier Supply Current Total Shutdown Power The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS (Note 8) l MIN 3.135 2.85 l TYP 3.3 100 10 MAX 3.465 3.5 136 UNITS V V mA mW AMPSHDN = ADCSHDN = 3.3V 9001fb 5 LTM9001-Ax/LTM9001-Bx The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL OVDD IVDD IOVDD PDISS PARAMETER Output Supply Voltage Analog Supply Current Output Supply Current Power Dissipation LTM9001-Ax LTM9001-BA (Note 8) LTM9001-Ax LTM9001-BA LTM9001-Ax LTM9001-BA (Note 8) LTM9001-Ax LTM9001-BA LTM9001-Ax LTM9001-BA LTM9001-Ax LTM9001-BA CONDITIONS (Note 8) LTM9001-Ax LTM9001-BA l l l l l l l l l l l l l l l l l POWER REQUIREMENTS MIN 3 TYP 3.3 400 465 74 1564 1779 MAX 3.6 500 550 90 1947 2112 3.6 500 550 50 1815 1980 3.6 UNITS V mA mA mA mW mW V mA mA mA mW mW V mA mA mW mW mW mW Standard LVDS Output Mode Low Power LVDS Output Mode OVDD IVDD IOVDD PDISS CMOS Output Mode OVDD IVDD PDISS PDISS(TOTAL) Output Supply Voltage Analog Supply Current ADC Power Dissipation Total Power Dissipation 0.5 380 460 1320 1584 1650 1914 450 530 1650 1914 Output Supply Voltage Analog Supply Current Output Supply Current Power Dissipation 3 3.3 400 465 41 1455 1670 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL fS tL PARAMETER Sampling Frequency (Note 8) ENC Low Time (Note 7) CONDITIONS LTM9001-Ax LTM9001-BA Duty Cycle Stabilizer Off (LTM9001-Ax) Duty Cycle Stabilizer Off (LTM9001-BA) Duty Cycle Stabilizer On (LTM9001-Ax) Duty Cycle Stabilizer On (LTM9001-BA) Duty Cycle Stabilizer Off (LTM9001-Ax) Duty Cycle Stabilizer Off (LTM9001-BA) Duty Cycle Stabilizer On (LTM9001-Ax) Duty Cycle Stabilizer On (LTM9001-BA) (Note 7) (Note 7) (tC – tD) (Note 7) l l l l l l l l l l l l l TIMING CHARACTERISTICS MIN 1 1 3.65 2.97 2.6 2.1 3.65 2.97 2.6 2.1 1.3 1.3 TYP MAX 130 160 UNITS MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns Cycles 9001fb 3.846 3.125 3.846 3.125 3.846 3.125 3.846 3.125 2.7 2.7 4.3 0.5 0.5 7 1000 1000 1000 1000 1000 1000 1000 1000 4 4 10 tH ENC High Time (Note 7) LVDS Output Mode (Standard and Low Power) tD tC tSKEW tRISE tFALL ENC to DATA Delay ENC to CLKOUT Delay DATA to CLKOUT Skew Output Rise Time Output Fall Time Data Latency 6 LTM9001-Ax/LTM9001-Bx The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL CMOS Output Mode tD tC tSKEW ENC to DATA Delay ENC to CLKOUT Delay DATA to CLKOUT Skew Data Latency (Note 7) (Note 7) (tC – tD) (Note 7) Full Rate CMOS Demuxed l l l TIMING CHARACTERISTICS PARAMETER CONDITIONS MIN 1.3 1.3 TYP 2.7 2.7 4.3 7 7 MAX 4 4 10 UNITS ns ns ns Cycles Cycles Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: Gain is measured from IN+/IN– through the ADC. The amplifier gain is attenuated by the filter, (See the typical performance characteristics section for “IF Frequency Response”). Note 4: VCC = VDD = 3.3V, fSAMPLE = maximum sample frequency, LVDS outputs, differential ENC+/ENC – = 2VP-P with 1.6V common mode, input range = –1dBFS with PGA = 0 with differential drive, AC-coupled inputs, unless otherwise noted. Note 5: Integral nonlinearity is defined as the deviation of a code from a “best fit straight line” to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the voltage applied between the IN+ and IN– pins required to make the output code flicker between 0000 0000 0000 0000 and 1111 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions. TIMING DIAGRAM LVDS Output Mode Timing All Outputs are Differential and Have LVDS Levels tAP ANALOG INPUT N+1 N+2 N+3 N+4 N tH tL ENC– ENC+ tD D0-D15, OF tC N–7 N–6 N–5 N–4 N–3 CLKOUT+ CLKOUT – 9001 TD01 9001fb 7 LTM9001-Ax/LTM9001-Bx TIMING DIAGRAM Full-Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N+1 N+2 tH tL ENC – N+4 N+3 N ENC+ tD DA0-DA15, OFA tC CLKOUTA CLKOUTB N–7 N–6 N–5 N–4 N–3 DB0-DB15, OFB HIGH IMPEDANCE 9001 TD02 Demultiplexed CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N+1 N+2 tH tL ENC – N+4 N+3 N ENC+ tD DA0-DA15, OFA tD DB0-DB15, OFB tC CLKOUTA CLKOUTB 9001 TD03 N–8 N–6 N–4 N–7 N–5 N–3 9001fb 8 LTM9001-Ax/LTM9001-Bx TYPICAL PERFORMANCE CHARACTERISTICS Differential Non-Linearity (DNL) vs Output Code 0.5 0.4 0.3 DNL ERROR (LSB) INL ERROR (LSB) 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 49152 16384 32768 ADC OUTPUT CODE 65536 9001 G01 (LTM9001-AA) Shorted Inputs Histogram with 130k Samples 9000 8000 7000 6000 COUNT 5000 4000 3000 2000 1000 Best Fit Integral Non-Linearity (INL) vs Output Code 5 4 3 2 1 0 –1 –2 –3 –4 –5 0 49152 16384 32768 ADC OUTPUT CODE 65536 9001 G02 0 33484 33524 33504 ADC OUTPUT CODE 33544 9001 G03 Input Impedance vs Frequency 250 MAGNITUDE PHASE 0 0 IF Frequency Response IMPEDANCE MAGNITUDE (Ω) 200 –2 FILTER GAIN (dB) IMPEDANCE PHASE (deg) –4 150 –45 –6 100 –8 50 10 100 FREQUENCY (MHz) –90 1000 9001 G04 –10 120 130 140 150 160 170 180 190 200 FREQUENCY (MHz) 9001 G05 64k Point FFT, fIN = 162.4MHz, –1dBFS, PGA = 0, RAND “Off”, Dither “Off” 0 –20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –60 –80 –100 –120 HD3 HD2 0 –20 –40 –60 –80 –100 –120 64k Point FFT, fIN = 162.4MHz, –1dBFS, PGA = 1, RAND “Off”, Dither “Off” 0 –20 AMPLITUDE (dBFS) –40 –60 –80 –100 –120 64k Point 2-Tone FFT, fIN = 161.5MHz, and 163.5MHz, –7dBFS, PGA = 0, RAND “Off”, Dither “Off” HD3 HD2 0 10 50 20 40 30 FREQUENCY (MHz) 60 9001 G06 0 10 50 20 40 30 FREQUENCY (MHz) 60 9001 G07 0 10 50 20 40 30 FREQUENCY (MHz) 60 9001 G08 9001fb 9 LTM9001-Ax/LTM9001-Bx TYPICAL PERFORMANCE CHARACTERISTICS 64k Point 2-Tone FFT, fIN = 161.5MHz, and 163.5MHz, –15dBFS, PGA = 0, RAND “Off”, Dither “Off” 0 –20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –60 –80 –100 –120 0 10 0 –20 AMPLITUDE (dBFS) –40 –60 –80 –100 –120 (LTM9001-AA) 64k Point FFT, fIN = 162.4MHz, –15dBFS, PGA = 0, RAND “Off”, Dither “On” 0 –20 –40 –60 –80 –100 –120 64k Point FFT, fIN = 162.4MHz, –15dBFS, PGA = 0, RAND “Off”, Dither “Off” 50 20 40 30 FREQUENCY (MHz) 60 9001 G09 0 10 50 20 40 30 FREQUENCY (MHz) 60 9001 G10 0 10 50 20 40 30 FREQUENCY (MHz) 60 9001 G11 SFDR vs Input Level, fIN = 162.4MHz, PGA = 0, RAND “Off”, Dither = “Off” 140 120 SFDR (dBc AND dBFS) 100 80 60 40 20 0 –90 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) SFDR dBc SFDR dBFS SFDR (dBc AND dBFS) 140 120 100 80 60 40 20 SFDR vs Input Level, fIN = 162.4MHz, PGA = 0, RAND “Off”, Dither = “On” SFDR dBc SFDR dBFS SFDR (dBc) AND SNR (dBFS) 84 SFDR and SNR vs Sample Rate, fIN = 162.4MHz, –1dBFS, PGA = 0, RAND “Off”, Dither “Off” SNR SFDR 80 76 72 68 0 0 –90 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 64 0 0 200 150 50 100 ADC SAMPLE RATE (Msps) 250 9001 G14 9001 G12 9001 G13 SFDR vs Input Common Mode Voltage, fIN = 162.4MHz, –1dBFS, PGA = 0 90 85 80 SFDR (dBc) SFDR (dBc) 75 70 65 60 0.5 81.0 80.5 80.0 79.5 79.0 78.5 78.0 77.5 77.0 76.5 76.0 2.5 2.0 1.0 1.5 INPUT COMMON MODE VOLTAGE (V) 3.0 SFDR vs VCC Supply Voltage, fIN = 162.4MHz, –1dBFS, PGA = 0 75.5 2.8 2.9 3.0 3.1 3.2 3.3 3.4 VCC SUPPLY VOLTAGE (V) 3.5 9001 G15 9001 G16 9001fb 10 LTM9001-Ax/LTM9001-Bx TYPICAL PERFORMANCE CHARACTERISTICS Differential Non-Linearity (DNL) vs Output Code 1.0 0.8 0.6 DNL ERROR (LSB) INL ERROR (LSB) 0.4 0.2 0.0 – 0.2 –0.4 –0.6 –0.8 –1.0 0 16384 49152 32768 OUTPUT CODE 65536 9001 G25 (LTM9001-AD) Best Fit Integral Non-Linearity (INL) vs Output Code 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 0 16384 49152 32768 OUTPUT CODE 65536 9001 G26 SNR vs Frequency 75 74 73 72 SNR (dB) 71 70 69 68 67 66 65 1 10 100 FREQUENCY (MHz) 1000 9001 G27 Input Impedance vs Frequency 220 200 IMPEDANCE MAGNITUDE (Ω) 180 160 140 120 100 80 60 40 20 0 1 10 100 FREQUENCY (MHz) MAGNITUDE PHASE 12 10 8 IMPEDANCE PHASE (DEG) 4 2 0 –2 –4 –6 –8 –10 1000 9001 G28 IF Frequency Response 0 –1 –2 AMPLITUDE (dBFS) –3 –4 –5 –6 –7 –8 –9 –10 40 50 60 70 80 FREQUENCY (MHz) 90 100 9001 G29 6 64k Point FFT, fIN = 70MHz, –1dBFS, PGA = 0, RAND “Off”, Dither “Off” 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 60 9001 G30 64k Point 2-Tone FFT, fIN = 70MHz, and fin = 74MHz, –7dBFS Per Tone, PGA = 0, RAND “Off”, Dither “Off” 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –40 –50 –60 –70 –80 HD2 HD3 –90 –100 –110 –120 0 10 20 30 40 50 FREQUENCY (MHz) 0 10 20 30 40 50 FREQUENCY (MHz) 60 9001 G31 9001fb 11 LTM9001-Ax/LTM9001-Bx TYPICAL PERFORMANCE CHARACTERISTICS Differential Non-Linearity (DNL) vs Output Code 1.0 0.8 0.6 DNL ERROR (LSB) INL ERROR (LSB) 0.4 0.2 0.0 – 0.2 –0.4 –0.6 –0.8 –1.0 0 16384 49152 32768 OUTPUT CODE 65536 9001 G17 (LTM9001-BA) Best Fit Integral Non-Linearity (INL) vs Output Code 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 0 16384 49152 32768 OUTPUT CODE 65536 9001 G18 SNR vs Frequency 71 69 67 65 SNR (dB) 63 61 59 57 55 53 51 1 10 100 FREQUENCY (MHz) 1000 9001 G19 Input Impedance vs Frequency 400 MAGNITUDE 350 IMPEDANCE MAGNITUDE (Ω) 300 250 200 150 100 50 0 1 10 100 FREQUENCY (MHz) –32 1000 9001 G20 IF Frequency Response 0 0 –5 –8 IMPEDANCE PHASE (°C) PHASE –16 AMPLITUDE (dBFS) –10 –15 –20 –25 –30 –24 1 10 100 FREQUENCY (MHz) 1000 9001 G21 64k Point FFT, fIN = 140MHz, –1dBFS, PGA = 0, RAND “Off”, Dither “Off” 0 –10 –20 AMPLITUDE (dBFS) –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 10 50 20 30 40 FREQUENCY (MHz) 60 9001 G22 64k Point FFT, fIN = 250MHz, –1dBFS, PGA = 0, RAND “Off”, Dither “Off” 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 HD2 HD3 AMPLITUDE (dBFS) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 64k Point 2-Tone FFT, fIN = 136MHz, –7dBFS Per Tone, PGA = 0, RAND “Off”, Dither “Off” HD3 HD2 0 10 50 20 30 40 FREQUENCY (MHz) 60 9001 G24 9001 G23 9001fb 12 LTM9001-Ax/LTM9001-Bx PIN FUNCTIONS Supply Pins VCC (Pins E1, E2): 3.3V Analog Supply Pin for Amplifier. The voltage on this pin provides power for the amplifier stage only and is internally bypassed to GND. VDD (Pins E5, D5): 3.3V Analog Supply Pin for ADC. This supply is internally bypassed to GND. OVDD (Pins A6, G9): Positive Supply for the ADC Output Drivers. This supply is internally bypassed to OGND. GND (Pins A1, A2, A4, B2, B4, C2, C4, D1, D2, D4, E4, F1, F2, F4, G2, G4, H2, H4, J1, J2, J4): Analog Ground. OGND (Pins A5, A9, G8, J9): ADC Output Driver Ground. Analog Inputs IN+ (Pin G1): Positive (Non-Inverting) Amplifier Input. IN– (Pin H1): Negative (Inverting) Amplifier Input. DNC (Pins C3, D3): Do Not Connect. These pins are used for testing and should not be connected on the PCB. They may be soldered to unconnected pads and should be well isolated. The DNC pins connect to the signal path prior to the ADC inputs; therefore, care should be taken to keep other signals away from these sensitive nodes. ENC+ (Pin C1): Positive Differential Encode Input. The sampled analog input is held on the rising edge of ENC+. This input is internally biased to 1.6V through a 6.2k resistor. Output data can be latched on the rising edge of ENC+. The Encode pins have a differential 100Ω input impedance. ENC – (Pin B1): Negative Differential Encode Input. The sampled analog input is held on the falling edge of ENC –. This input is internally biased to 1.6V through a 6.2k resistor. Bypass to ground with a 0.1μF capacitor for a single-ended encode signal. The encode pins have a differential 100Ω input impedance. Control Inputs SENSE (Pin J3): Reference Mode Select and External Reference Input. Tie SENSE to VDD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set the maximum full-scale input range. AMPSHDN (Pin H3): Power Shutdown Pin for Amplifier. This pin is a logic input referenced to analog ground. AMPSHDN = low results in normal operation. AMPSHDN = high results in powered down amplifier with typically 3mA amplifier supply current. MODE (Pin G3): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and disables the clock duty cycle stabilizer. Connecting MODE to 1/3VDD selects offset binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2’s complement output format and enables the clock duty cycle stabilizer. Connecting MODE to VDD selects 2’s complement output format and disables the clock duty cycle stabilizer. RAND (Pin F3): Digital Output Randomization Selection Pin. RAND = low results in normal operation. RAND = high selects D1 to D15 to be EXCLUSIVE-ORed with D0 (the LSB). The output can be decoded by again applying an XOR operation between the LSB and all other bits. This mode of operation reduces the effects of digital output interference. PGA (Pin E3): Programmable Gain Amplifier Control Pin. PGA = low selects the normal (maximum) input voltage range. PGA = high selects a 3.5dB reduced input range for slightly better distortion performance at the expense of SNR. ADCSHDN (Pin B3): Power Shutdown Pin for ADC. ADCSHDN = low results in normal operation. ADCSHDN = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state. DITH (Pin A3): Internal Dither Enable Pin. DITH = low disables internal dither. DITH = high enables internal dither. Refer to Internal Dither section of this data sheet for details on dither operation. LVDS (Pin F5): Data Output Mode Select Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demultiplexed CMOS mode. Connecting LVDS to 2/3VDD selects low power LVDS mode. Connecting LVDS to VDD selects standard LVDS mode. 9001fb 13 LTM9001-Ax/LTM9001-Bx PIN FUNCTIONS Digital Outputs For CMOS Mode, Full Rate or Demultiplexed DA0 to DA15 (Pins E9 to H5): Digital Outputs, A Bus. DA15 is the MSB. Output bus for full rate CMOS mode and demultiplexed mode. CLKOUTA (Pin E8): Inverted Data Valid Output. CLKOUTA will toggle at the sample rate in full rate CMOS mode or at 1/2 the sample rate in demultiplexed mode. Latch the data on the rising edge of CLKOUTA. OFB (Pin E6): Overflow/Underflow Digital Output for the B Bus. OFB is high when an overflow or underflow has occurred on the B bus. OFB is in a high impedance state in full rate CMOS mode. DB0 to DB15 (Pins B5 to D9): Digital Outputs, B Bus. DB15 is the MSB. Active in demultiplexed mode. The B bus is in a high impedance state in full rate CMOS mode. Pin Configuration (LVDS Outputs/CMOS Outputs) 1 J H G F E D C B A GND IN– IN+ GND VCC GND ENC+ ENC– GND 2 GND GND GND GND VCC GND GND GND GND 3 SENSE AMPSHDN MODE RAND PGA DNC DNC ADCSHDN DITH 4 GND GND GND GND GND GND GND GND GND 5 D14+/DA12 OF–/DA15 OF+/OFA LVDS VDD VDD D0+/DB1 D0–/DB0 OGND 6 D14–/DA11 D15–/DA13 D15+/DA14 D9–/DA1 D6–/DB12 D4–/DB8 D1–/DB2 OVDD 7 D12+/DA8 D13–/DA9 D13+/DA10 D9+/DA2 D6+/DB13 D4+/DB9 D1+/DB3 D2–/DB4 8 D12–/DA7 D11–/DA5 OGND D10–/DA3 D7–/DB14 D5–/DB10 D3+/DB7 D2+/DB5 9 OGND D11+/DA6 OVDD D10+/DA4 D8+/DA0 D7+/DB15 D5+/DB11 D3–/DB6 OGND CLKOUTB (Pin E7): Data Valid Output. CLKOUTB will toggle at the sample rate in full rate CMOS mode or at 1/2 the sample rate in demultiplexed mode. Latch the data on the falling edge of CLKOUTB. OFA (Pin G5): Overflow/Underflow Digital Output for the A Bus. OFA is high when an overflow or underflow has occurred on the A bus. For LVDS Mode, Standard or Low Power D0–/D0+ to D15–/D15+ (Pins B5 to G6): LVDS Digital Outputs. All LVDS outputs require differential 100Ω termination resistors at the LVDS receiver. D15+/D15– is the MSB. CLKOUT –/CLKOUT + (Pins E6, E7): LVDS Data Valid Output. Latch data on the rising edge of CLKOUT+, falling edge of CLKOUT –. OF –/OF + (Pins H5, G5): Overflow/Underflow Digital Output. OF is high when an over or under flow has occurred. CLKOUT–/OFB CLKOUT+/CLKOUTB D8–/CLKOUTA Top View of LGA Pinout (Looking Through Component) ALL ELSE = GND TOP VIEW CONTROL 1 J IN– IN+ H G F VCC E DNC D ENC+ C ENC– B A CONTROL VDD OGND OVDD 9001 LGA01 DATA 4 5 6 7 8 9 OGND 2 3 OVDD OGND 9001fb 14 VCC VDD ANTI-ALIAS FILTER INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE IN + INPUT AMPLIFIER IN– FUNCTIONAL BLOCK DIAGRAM AMPSHDN SHIFT REGISTER AND ERROR CORRECTION DITHER SIGNAL GENERATOR VOLTAGE REFERENCE ADC REFERENCE PGA CONTROL LOGIC INTERNAL CLOCK SIGNALS OVDD D15± … D0± OUTPUT DRIVERS CLKOUT+ CLKOUT– OF+ OF– DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER SENSE RANGE SELECT 100Ω 9001 BD PGA GND ENC+ ENC– ADCSHDN RAND MODE LVDS DITH OGND LTM9001-Ax/LTM9001-Bx 15 9001fb LTM9001-Ax/LTM9001-Bx OPERATION DYNAMIC PERFORMANCE DEFINITIONS Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. Signal-to-Noise Ratio The signal-to-noise (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components, except the first five harmonics. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = –20Log ⎛ (V22 + V32 + V42 + ...Vn2 ) /V1⎞ ⎝ ⎠ where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. Intermodulation Distortion If the input signal consists of more than one spectral component, the transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the input, nonlinearities in the transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 3rd order IMD terms include (2fa + fb), (fa + 2fb), (2fa – fb) and (fa – 2fb). The 3rd order IMD is defined as the ration of the RMS value of either input tone to the RMS value of the largest 3rd order IMD product. Spurious Free Dynamic Range (SFDR) The ratio of the RMS input signal amplitude to the RMS value of the peak spurious spectral component expressed in dBc. SFDR may also be calculated relative to full-scale and expressed in dBFS. Aperture Delay Time Aperture delay is the time from when a rising ENC+ equals the ENC– voltage to the instant that the input signal is held by the sample and-hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) DESCRIPTION The LTM9001 is an integrated system in a package (SiP) μModule ® receiver that includes a high-speed, sampling 16-bit A/D converter, matching network, anti-aliasing filter and a low noise, differential amplifier with fixed gain. It is designed for digitizing high frequency, wide dynamic range signals with an intermediate frequency (IF) range up to 300MHz. μModule is a registered trademark of Linear Technology Corporation. 9001fb 16 LTM9001-Ax/LTM9001-Bx OPERATION The following sections describe in further detail the functional operation of the LTM9001. The SiP technology allows the LTM9001 to be customized and this is described in the first section. The remaining outline follows the basic functional elements as shown in Figure 1. Technology has in place a program to deliver other speed, resolution, IF range, gain and filter configurations for a wide range of applications. See Table 1 for the LTM9001-AA configuration and potential options. These semi-custom designs are based on existing ADCs and amplifiers with an appropriately modified matching network. The final subsystem is then tested to the exact parameters defined for the application. The final result is a fully integrated, accurately tested and reliable solution. For more details on the semi-custom receiver subsystem program, contact Linear Technology. Note that not all combinations of options in Table 1 are possible at this time and specified performance may differ significantly from existing values. This data sheet discusses devices with LVDS and CMOS outputs. The lower speed options that only support CMOS outputs are available on a separate data sheet. The CMOS-only options have a different pin assignment. AMPLIFIER INFORMATION The amplifiers used in the LTM9001 are low noise and low distortion fully differential ADC drivers. The amplifiers are very flexible in terms of I/O coupling. They can be AC- or DC-coupled at the inputs. Users are advised to keep the input common mode voltage between 1V and 1.6V for proper operation. If the inputs are AC-coupled, the input common mode voltage is automatically biased. The input signal can be either single-ended or differential with almost no difference in distortion performance. ADC RESOLUTION 16-bit 16-bit 16-bit 16-bit 14-bit AMPLIFIER ADC INPUT NETWORK ADC 9001 F01 Figure 1. Basic Functional Elements SEMI-CUSTOM OPTIONS The μModule construction affords a new level of flexibility in application-specific standard products. Standard ADC and amplifier components can be integrated regardless of their process technology and matched with passive components to a particular application. The LTM9001-AA, as the first example, is configured with a 16-bit ADC sampling at rates up to 130Msps. The amplifier gain is 20dB with an input impedance of 200Ω and an input range of 233mVP-P. The matching network is designed to optimize the interface between the amplifier output and the ADC under these conditions. Additionally, there is a 2-pole bandpass filter designed for 162.5MHz ±25MHz. However, other options are possible through Linear Technology’s semi-custom development program. Linear Table 1. Semi-Custom Options AMPLIFIER IF AMPLIFIER INPUT ADC SAMPLE RANGE IMPEDANCE AMPLIFIER GAIN FILTER RATE 300MHz 200Ω 20dB 162.5MHz BPF 50MHz BW , 130Msps 300MHz 200Ω 14dB 70MHz BPF, 25MHz BW 130Msps 300MHz 400Ω 8dB DC-300MHz LPF 160Msps Select Combination of Options from Columns Below DC-300MHz 50Ω 26dB LPF TBD 160Msps DC-140MHz 200Ω 20dB BPF TBD 130Msps DC-70MHz 200Ω 14dB 105Msps DC-35MHz 400Ω 8dB 80Msps 200Ω 6dB 65Msps 40Msps 25Msps 10Msps OUTPUT LVDS/CMOS LVDS/CMOS LVDS/CMOS LVDS/CMOS LVDS/CMOS CMOS CMOS CMOS CMOS CMOS CMOS PART NUMBER LTM9001-AA LTM9001-AD LTM9001-BA 9001fb 17 LTM9001-Ax/LTM9001-Bx OPERATION ADC INPUT NETWORK The passive network between the amplifier output stage and the ADC input stage can be configured for bandpass or lowpass response with different cutoff frequencies and bandwidths. The LTM9001-AA, for example, implements a 2-pole bandpass filter centered at 162.5MHz with 50MHz bandwidth. Note that the filter attenuates the signal at 162.5MHz by 1dB, making the overall gain of the subsystem 19dB. For production test purposes the filter is designed to allow DC inputs into the ADC. CONVERTER INFORMATION The analog-to-digital converter (ADC) is a CMOS pipelined multistep converter with a front-end PGA. As shown in the Functional Block Diagram, the converter has five pipelined ADC stages; a sampled analog input will result in a digitized value seven cycles later (see the Timing Diagram section). The encode input is differential for improved common mode noise immunity. APPLICATIONS INFORMATION INPUT SPAN The LTM9001 is configured with a fixed input span and input impedance. With the amplifier gain and the ADC input network described above for LTM9001-AA, the fullscale input range of the driver circuit is 233mVP-P. The recommended ADC input span is achieved by tying the SENSE pin to VDD. However, the ADC input span can be changed by applying a DC voltage to the SENSE pin. Input Impedance and Matching 9001 F02 25Ω IN+ ZIN/2 LTM9001 RF + – VIN RT 25Ω IN– ZIN/2 RF The differential input impedance of the LTM9001 can be 50Ω, 200Ω or 400Ω. In some applications the differential inputs may need to be terminated to a lower value impedance, e.g. 50Ω, in order to provide an impedance match for the source. Several choices are available. One approach is to use a differential shunt resistor (Figure 2). Another approach is to employ a wide band transformer (Figure 3). Both methods provide a wide band match. The termination resistor or the transformer must be placed close to the input pins in order to minimize the reflection due to input mismatch. Table 2. Differential Amplifier Input Termination Values ZIN 400Ω 200Ω 50Ω RT FIG 2 57Ω 66.5Ω None Figure 2. Input Termination for Differential 50Ω Input Impedance Using Shunt Resistor (See Table 2 for RT Values) LTM9001 25Ω IN+ ZIN/2 RF + – VIN •• 25Ω IN– ZIN/2 RF 9001 F03 Figure 3. Input Termination for Differential 50Ω Input Impedance Using a Wideband Transformer 9001fb 18 LTM9001-Ax/LTM9001-Bx APPLICATIONS INFORMATION Alternatively, one could apply a narrowband impedance match at the inputs for frequency selection and/or noise reduction. Referring to Figure 4, amplifier inputs can be easily configured for single-ended input without a balun. The signal is fed to one of the inputs through a matching network while the other input is connected to the same impedance. In general, the single-ended input impedance and termination resistor RT are determined by the combination of RS, ZIN/2 and RF. Table 3. Single-Ended Amplifier Input Termination Values ZIN 400Ω 200Ω 50Ω RT FIG 4 59Ω 68.5Ω 150Ω Rs/2 IN+ ZIN/2 RF LTM9001 RS 50Ω 0.1μF LTM9001 IN+ ZIN/2 RF VIN RT 0.1μF + – RS/RT 0.1μF IN– ZIN/2 RF 9001 F04 Figure 4. Input Termination for Differential 50Ω Input Impedance Using Shunt Resistor The LTM9001 amplifier is stable with all source impedances. The overall differential gain is affected by the source impedance in Figure 5: AV = | VOUT/VIN | = (1000/(RS + ZIN/2)) The noise performance of the amplifier also depends upon the source impedance and termination. For example, an input 1:4 transformer in Figure 3 improves the input noise figure by adding 6dB voltage gain at the inputs. Reference and SENSE Pin Operation Figure 6 shows the converter reference circuitry consisting of a 2.5V bandgap reference, a programmable gain amplifier and control circuit. There are three modes of reference operation: internal reference, 1.25V external reference or 2.5V external reference. To use the internal reference, + – VIN RT Rs/2 IN– ZIN/2 RF 9001 F05 Figure 5. Calculate Differential Gain tie the SENSE pin to VDD. To use an external reference, simply apply either a 1.25V or 2.5V reference voltage to the SENSE input pin. Both 1.25V and 2.5V applied to SENSE will result in the maximum full-scale range. TIE TO VDD TO USE INTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 1.25V REFERENCE RANGE SELECT AND GAIN CONTROL SENSE PGA INTERNAL ADC REFERENCE 2.5V BANDGAP REFERENCE 9001 F06 Figure 6. Reference Circuit 9001fb 19 LTM9001-Ax/LTM9001-Bx APPLICATIONS INFORMATION PGA Pin The PGA pin selects between two gain settings for the ADC front-end. PGA = low selects the maximum input span; PGA = high selects a 3.5dB lower input span. The high input range has the best SNR. For applications with high linearity requirements, the low input range will have improved distortion; however, the SNR will be 1.8dB worse. See the Typical Performance Characteristics section. Driving the Encode Inputs The noise performance of the converter can depend on the encode signal quality as much as the analog input. The encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies), take the following into consideration: 1. Differential drive should be used. 2. Use the largest amplitude possible. If using transformer coupling, use a higher turns ratio to increase the amplitude. LTM9001 VDD TO INTERNAL ADC CLOCK DRIVERS VDD 1.6V 6k 3. If the ADC is clocked with a fixed frequency sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.2V to VDD. Each input may be driven from ground to VDD for single-ended drive. The encode clock inputs have a differential 100Ω input impedance. For 50Ω inputs e.g. signal generators, an additional 100Ω impedance will provide an impedance match, as shown in Figure 7b. Maximum and Minimum Encode Rates The maximum encode rate for the LTM9001-Ax is 130Msps and 160Msps for LTM9001-BA. For the ADC to operate properly the encode signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 3.65ns (LTM9001-Ax, or 2.97ns for LTM9001-BA) for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. When using a single-ended encode signal asymmetric rise and fall times can result in duty cycles that are far from 50%. LTM9001 0.1μF ENC+ T1 50Ω 100Ω 8.2pF 50Ω ENC– 9001 F07b • • ENC + 100Ω VDD 1.6V 6k 0.1μF 0.1μF ENC– T1 = M/A-COM ETC1-1-13 9001 F07a Figure 7a. Equivalent Encode Input Circuit Figure 7b. Transformer Driven Encode 9001fb 20 LTM9001-Ax/LTM9001-Bx APPLICATIONS INFORMATION An optional clock duty cycle stabilizer can be used if the input clock does not have a 50% duty cycle. This circuit uses the rising edge of ENC to sample the analog input. The falling edge of ENC is ignored and an internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin must be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the sample rate is determined by the droop of the sample and hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTM9001 is 1Msps. ENC+ 1.6V ENC– 0.1μF 9001F8 DIGITAL OUTPUTS Digital Output Modes The LTM9001 can operate in four digital output modes: standard LVDS, low power LVDS, full rate CMOS, and demultiplexed CMOS. The LVDS pin selects the mode of operation. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An external resistive divider can be used to set the 1/3VDD and 2/3VDD logic levels. Table 4 shows the logic states for the LVDS pin. Table 4. LVDS Pin Function LVDS 0V(GND) 1/3VDD 2/3VDD VDD DIGITAL OUTPUT MODE Full-Rate CMOS Demultiplexed CMOS Low Power LVDS LVDS Digital Output Buffers (CMOS Modes) Figure 10 shows an equivalent circuit for a single output buffer in CMOS mode, full-rate or demultiplexed. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and eliminates the need for external damping resistors. LTM9001 OVDD VDD VDD 0.5V TO 3.6V VTHRESHOLD = 1.6V LTM9001 Figure 8. Single-Ended ENC Drive, Not Recommended for Low Jitter 3.3V MC100LVELT22 3.3V 261Ω Q0 D0 ENC– Q0 165Ω 165Ω 9001 F09 261Ω ENC+ LTM9001 DATA FROM LATCH PREDRIVER LOGIC OVDD 43Ω TYPICAL DATA OUTPUT OGND 100Ω 9001 F10 Figure 9. ENC Drive Using a CMOS to PECL Translator Figure 10. Equivalent Circuit for a Digital Output Buffer 9001fb 21 LTM9001-Ax/LTM9001-Bx APPLICATIONS INFORMATION As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTM9001 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF A resistor in series with the . output may be used but is not required since the ADC has a series resistor of 43Ω on chip. Lower OVDD voltages will also help reduce interference from the digital outputs. Digital Output Buffers (LVDS Modes) Figure 11 shows an equivalent circuit for an LVDS output pair. A 3.5mA current is steered from OUT+ to OUT– or vice versa, which creates a ±350mV differential voltage across the 100Ω termination resistor at the LVDS receiver. A feedback loop regulates the common mode output voltage to 1.2V. For proper operation each LVDS output pair must be terminated with an external 100Ω termination resistor, even if the signal is not used (such as OF+/OF– or CLKOUT+/CLKOUT–). To minimize noise the PC board traces for each LVDS output pair should be routed close together. To minimize clock skew all LVDS PC board traces should have about the same length. In low power LVDS mode 1.75mA is steered between the differential outputs, resulting in ±175mV at the LVDS receiver’s 100Ω termination resistor. The output common mode voltage is 1.2V, the same as standard LVDS mode. Data Format The LTM9001 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MODE pin. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An external resistive divider can be used to set the 1/3VDD and 2/3VDD logic levels. Table 5 shows the logic states for the MODE pin. Table 5. MODE Pin Function MODE 0V(GND) 1/3VDD 2/3VDD VDD OUTPUT FORMAT Offset Binary Offset Binary 2’s Complement 2’s Complement CLOCK DUTY CYCLE STABILIZER Off On On Off Overflow Bit An overflow output bit (OF) indicates when the converter is overranged or underranged. In CMOS mode, a logic high on the OFA pin indicates an overflow or underflow on the A data bus, while a logic high on the OFB pin indicates an overflow on the B data bus. In LVDS mode, a differential logic high on OF+/OF– pins indicates an overflow or underflow. OVDD 3.3V LTM9001 3.5mA VDD VDD OVDD 43Ω DATA FROM LATCH PREDRIVER LOGIC 10k 10k OVDD 43Ω 100Ω LVDS RECEIVER 1.20V + – 9001 F11 OGND Figure 11. Equivalent Output Buffer in LVDS Mode 9001fb 22 LTM9001-Ax/LTM9001-Bx APPLICATIONS INFORMATION Output Clock The ADC has a delayed version of the encode input available as a digital output, CLKOUT. The CLKOUT pin can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. In both CMOS modes, A bus data will be updated as CLKOUTA falls and CLKOUTB rises. In demultiplexed CMOS mode the B bus data will be updated as CLKOUTA falls and CLKOUTB rises. In full rate CMOS mode, only the A data bus is active; data may be latched on the rising edge of CLKOUTA or the falling edge of CLKOUTB. In demultiplexed CMOS mode CLKOUTA and CLKOUTB will toggle at 1/2 the frequency of the encode signal. Both the A bus and the B bus may be latched on the rising edge of CLKOUTA or the falling edge of CLKOUTB. Digital Output Randomizer Interference from the ADC digital outputs is sometimes unavoidable. Interference from the digital outputs may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can result in discernible unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise floor for a large reduction in unwanted tone amplitude. The digital output is “randomized” by applying an exclusiveOR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied; that is, an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT output are not affected. The output randomizer function is active when the RAND pin is high. Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For LTM9001 D2 ⊕ D0 RAND = HIGH, RANDOMIZER ENABLED RAND LTM9001 CLKOUT CLKOUT OF OF D15 D15/D0 D14 D14/D0 D2 • • • D2/D0 D1 D1/D0 D0 9001 F12 D0 Figure 12. Functional Equivalent of Digital Output Randomizer PC BOARD FPGA CLKOUT OF D15 ⊕ D0 D15 D14 ⊕ D0 D14 • • • D2 D1 ⊕ D0 D1 D0 D0 9001 F13 Figure 13. Derandomizing a Randomized Digital Output 9001fb 23 LTM9001-Ax/LTM9001-Bx APPLICATIONS INFORMATION example, if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply. OVDD can be powered with any logic voltage up to the 3.6V. OGND can be powered with any voltage from ground up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. Internal Dither The LTM9001 is a 16-bit receiver subsystem with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC element mismatches. An optional internal dither mode can be enabled to randomize the input location on the ADC transfer curve, resulting in improved SFDR for low signal levels. As shown in Figure 14, the output of the sample-and-hold amplifier is summed with the output of a dither DAC. The dither DAC is driven by a long sequence pseudo-random number generator; the random number fed to the dither DAC is also subtracted from the ADC result. If the dither DAC is precisely calibrated to the ADC, very little of the dither signal will be seen at the output. The dither signal that does leak through will appear as white noise. The dither DAC will cause a small elevation in the noise floor of the ADC, as compared to the noise floor with dither off. For best noise performance with the dither signal on, the driving impedance connected across pins IN+/IN– should closely match that of the module (see Table 1). A source impedance that is resistive and matches that of the module within 10% will give the best results. Supply Sequencing The VCC pin provides the supply to the amplifier and the VDD pin provides the supply to the ADC. The amplifier and the ADC are separate integrated circuits within the LTM9001; however, there are no supply sequencing considerations beyond standard practice. It is recommended that the amplifier and ADC both use the same low noise, 3.3V supply, but the amplifier may be operated from a lower voltage level if desired. Both devices can operate from the same 3.3V linear regulator but place a ferrite bead between the VCC and VDD pins. Separate linear regulators can be used without additional supply sequencing circuitry if they have common input supplies. LTM9001 CLKOUT OF D15 • • • D0 IN + IN – S/H AMP 16-BIT PIPELINED ADC CORE DIGITAL SUMMATION OUTPUT DRIVERS CLOCK/DUTY CYCLE CONTROL PRECISION DAC MULTIBIT DEEP PSEUDO-RANDOM NUMBER GENERATOR 9001 F14 ENC+ ENC – DITH DITHER ENABLE HIGH = DITHER ON LOW = DITHER OFF Figure 14. Functional Equivalent Block Diagram of Internal Dither Circuit 9001fb 24 LTM9001-Ax/LTM9001-Bx APPLICATIONS INFORMATION Grounding and Bypassing The LTM9001 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the LTM9001 has been optimized for a flow-through layout so that the interaction between inputs and digital outputs is minimized. A continuous row of ground pads facilitate a layout that ensures that digital and analog signal lines are separated as much as possible. The LTM9001 is internally bypassed with the amplifier (VCC) and ADC (VDD) supplies returning to a common ground (GND). The digital output supply (0VDD) is returned to OGND. Additional bypass capacitance is optional and may be required if power supply noise is significant. The differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTM9001 is transferred through the bottom-side ground pads. For good electrical and thermal performance, it is critical that all ground pins are connected to a ground plane of sufficient area with as many vias as possible. Recommended Layout The high integration of the LTM9001 makes the PC board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary, see Figures 15-18. • Use large PCB copper areas for ground. This helps to dissipate heat in the package through the board and also helps to shield sensitive on-board analog signals. Common ground (GND) and output ground (OGND) are electrically isolated on the LTM9001, but can be connected on the PCB underneath the part to provide a common return path. • Use multiple ground vias. Using as many vias as possible helps to improve the thermal performance of the board and creates necessary barriers separating analog and digital traces on the board at high frequencies. • Separate analog and digital traces as much as possible, using vias to create high-frequency barriers. This will reduce digital feedback that can reduce the signal-to-noise ratio (SNR) and dynamic range of the LTM9001. The quality of the paste print is an important factor in producing high yield assemblies. It is recommended to use a type 3 or 4 printing no-clean solder paste. The solder stencil design should follow the guidelines outlined in Application Note 100. The LTM9001 employs gold-finished pads for use with Pb-based or tin-based solder paste. It is inherently Pb-free and complies with the JEDEC (e4) standard. The materials declaration is available online at http://www.linear. com/designtools/leadfree/mat_dec.jsp. 9001fb 25 LTM9001-Ax/LTM9001-Bx APPLICATIONS INFORMATION Figure 15. Layer 1 Figure 16. Layer 2 Figure 17. Layer 3 Figure 18. Layer 4 9001fb 26 aaa Z 11.250 BSC X Y 2.17 – 2.47 0.25 × 45° CHAMFER ×3 J 10.160 BSC 0.605 – 0.665 H 0.605 – 0.665 MOLD CAP SUBSTRATE F 0.27 – 0.37 1.90 – 2.10 Z PACKAGE DESCRIPTION G 11.250 BSC 10.160 BSC E D C B A 9 8 7 6 5 4 PACKAGE BOTTOM VIEW 3 2 1 PAD 1 PAD 1 CORNER 1.27 BSC aaa Z 4 PACKAGE TOP VIEW DETAIL A PACKAGE SIDE VIEW 3 bbb Z DETAIL A 1.5875 1.270 0.9525 PADS SEE NOTES 2.540 3.810 5.080 5.080 3.810 2.540 5.080 0.000 1.270 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3 4 LAND DESIGNATION PER JESD MO-222, SPP-010 AND SPP-020 LGA Package 81-Lead (11.25mm × 11.25mm × 2.32mm) (Reference LTC DWG # 05-08-1809 Rev A) 3.810 2.540 1.270 1.5875 0.9525 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR A MARKED FEATURE COMPONENT PIN “A1” TRAY PIN 1 BEVEL LTMXXXXXX μModule Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 81 SYMBOL TOLERANCE aaa 0.15 0.10 bbb PACKAGE IN TRAY LOADING ORIENTATION LGA 81 1107 REV A 0.000 1.270 2.540 3.810 5.080 SUGGESTED PCB LAYOUT TOP VIEW LTM9001-Ax/LTM9001-Bx 27 9001fb LTM9001-Ax/LTM9001-Bx TYPICAL APPLICATION LTM9001 with Ground-Referenced Single-Ended Input 3.3V RS 50Ω 75Ω 75Ω VCC IN+ LTM9001 IN– 51.1Ω GROUND– REFERENCED SOURCE 0V + – 9001 TA02 RELATED PARTS PART NUMBER LTC2202 LTC2203 LTC2204 LTC2205 LTC2206 LTC2207 LTC2208 LTC2209 LTC6400-8/LTC6400-14/ LTC6400-20/LTC6400-26 LTC6401-8/LTC6401-14/ LTC6401-20/LTC6401-26 DESCRIPTION 16-Bit, 10Msps ADC 16-Bit, 25Msps ADC 16-Bit, 40Msps ADC 16-Bit, 65Msps ADC 16-Bit, 80Msps ADC 16-Bit, 105Msps ADC 16-Bit, 130Msps ADC 16-Bit, 160Msps ADC Low Noise, Low Distortion Differential Amplifier for 300MHz IF, Fixed Gain of 8dB, 14dB, 20dB or 26dB Low Noise, Low Distortion Differential Amplifier for 140MHz IF, Fixed Gain of 8dB, 14dB, 20dB 20dB or 26dB COMMENTS 140mW, 81.6dB SNR, 100dB SFDR 220mW, 81.6dB SNR, 100dB SFDR 480mW, 79.1dB SNR, 100dB SFDR 610mW, 79dB SNR, 100dB SFDR 725mW, 77.9dB SNR, 100dB SFDR 900mW, 77.9dB SNR, 100dB SFDR 1250mW, 77.7dB SNR, 100dB SFDR 1450mW, 77.1dB SNR, 100dB SFDR 3V, 90mA, 39.5dBm OIP3 at 300MHz, 6dB NF 3V, 45mA, 45.5dBm OIP3 at 140MHz, 6dB NF 9001fb 28 Linear Technology Corporation (408) 432-1900 ● LT 0509 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008