LTM9003IV-AA

Electrical Specifications Subject to Change LTM9003 12-Bit Digital Pre-Distortion Receiver Subsystem FEATURES n n n n n n n n n n DESCRIPTION The LTM®9003 is a 12-bit digital pre-distortion receiver subsystem for the transmit path of cellular basestations. Utilizing an integrated system in a package (SiP) tech-nology, it includes a downconverting mixer, wideband filter and analog-to-digital converter (ADC). The system is tuned for an intermediate frequency (IF) of 184MHz and a signal bandwidth of up to 125MHz. The 12-bit ADC samples at rates up to 250Msps. Contact Linear Technology regarding customization. The high signal level downconverting active mixer is optimized for high linearity, wide dynamic range IF sampling applications. It includes a differential LO buffer amplifier driving a double-balanced mixer. Broadband, integrated transformers on the RF and LO inputs provide single ended 50Ω interfaces. The RF and LO inputs are internally matched to 50Ω from 1.1GHz to 1.8GHz. The CLK input controls converter operation and may be driven differentially or single-ended. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131. Fully Integrated Receiver Subsystem for Digital Pre-Distortion Applications Down-Converting Mixer with Wide RF Frequency Range: 400MHz to 3.8GHz 125MHz Wide Bandpass Filter, 12 >12 >10 >10 –1.8 –1.8 –3 0 38 2 5 3700 3800 MAX UNITS MHz MHz MHz MHz MHz MHz MHz MHz dB dB dB dB dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm LO Input Return Loss RF Input Power for –1dBFS LO Input Power LO to RF Leakage CONVERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error (Note 4) Differential Linearity Error CONDITIONS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) MIN l TYP TBD TBD MAX UNITS Bits LSB LSB 12 IF = 184.32MHz IF = 184.32MHz 9003p 3 LTM9003 FILTER CHARACTERISTICS PARAMETER Center Frequency Lower 3dB Bandedge Upper 3dB Bandedge Lower 20dB Stopband Upper 20dB Stopband Passband Flatness Group Delay Flatness Absolute Delay LTM9003-Ax LTM9003-Ax LTM9003-Ax LTM9003-Ax LTM9003-Ax 129MHz to 239.6MHz, LTM9003-Ax 174MHz to 194MHz, LTM9003-Ax 129MHz to 239.6MHz, LTM9003-Ax 174MHz to 194MHz, LTM9003-Ax LTM9003-Ax The l denotes the specifications which apply over the full operating temperature MIN TYP 184.32 84 304 40 450 0.5 0.15 1.2 0.1 2.7 MAX UNITS MHz MHz MHz MHz MHz dB dB ns ns ns range, otherwise specifications are at TA = 25°C. CONDITIONS DYNAMIC ACCURACY SYMBOL PARAMETER SNR Signal-to-Noise Ratio at –1dBFS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS RF = 1950MHz, LO = 1766MHz RF = 1889MHz, LO = 1766MHz RF = 2011MHz, LO = 1766MHz LTM9003-AA RF = 1948MHz, 1952MHz, LO = 1766MHz LTM9003-AB RF = 1948MHz, 1952MHz, LO = 1766MHz l MIN TBD TYP 143.7 143.7 25.8 26.5 61 67 52.4 MAX UNITS dB/Hz dB/Hz dB/Hz dBm dBm dBm dBm dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB IIP3 Input 3rd Order Intercept, 2-Tone IIP2 Input 2nd Order Intercept, 1-Tone LTM9003-AA RF = 1950MHz, LO = 1766MHz LTM9003-AB RF = 1950MHz, LO = 1766MHz SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic at –1dBFS LTM9003-AA RF = 1889MHz, LO = 1766MHz RF = 1950MHz, LO = 1766MHz RF = 2011MHz, LO = 1766MHz LTM9003-AB RF = 1889MHz, LO = 1766MHz RF = 1950MHz, LO = 1766MHz RF = 2011MHz, LO = 1766MHz l TBD 67.4 61 65 71.5 63 61 l l TBD TBD SFDR Spurious Free Dynamic Range 4th or Higher at –1dBFS RF = 1950MHz, LO = 1766MHz RF = 1889MHz, LO = 1766MHz RF = 2011MHz, LO = 1766MHz S/(N+D) Signal-to-Noise Plus Distortion Ratio at –1dBFS RF = 1950MHz, LO = 1766MHz RF = 1889MHz, LO = 1766MHz RF = 2011MHz, LO = 1766MHz Intermodulation Distortion at –7dBFS per Tone Adjacent Channel Power Ratio at 2.4dBm per Carrier, Four Carriers Alternate Channel Power Ratio at 2.4dBm per Carrier, Four Carriers RF = 1950MHz, LO = 1766MHz l TBD 57 58 –67 58.5 63.3 IMD3 ACPR ALTCPR 9003p 4 LTM9003 DIGITAL INPUTS AND OUTPUTS SYMBOL VID VICM RIN CIN VIH VIL IIN CIN Mixer Enable VIH VIL IIN High Level Input Voltage Low Level Input Voltage Input Current Turn-On Time Turn-Off Time Amplifier Enable VIH VIL IIN ISENSE IMODE ILVDS OVDD = 2.5V VOD VOS Differential Output Voltage Output Common Mode Voltage 100Ω Differential Load 100Ω Differential Load l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) PARAMETER Differential Input Voltage Common Mode Input Voltage Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance VDD = 2.5V VDD = 2.5V VIN = 0V to VDD (Note 5) VCC1 = 3.3V, LTM9003-AA VCC1 = 5V, LTM9003-AB VCC1 = 3.3V, LTM9003-AA VCC1 = 5V, LTM9003-AB VIN = 0V to VCC1, LTM9003-AA 53 2.8 2.9 VCC2 = 3.3V VCC2 = 3.3V VIN = 0V to VCC2 0V < SENSE < 1V See Pin Descriptions for Voltage Levels See Pin Descriptions for Voltage Levels l l l l CONDITIONS l MIN 0.2 1.2 TYP MAX UNITS V Encode Inputs (ENC–, ENC+) Internally Set Externally Set 1.5 1.5 4.8 2 1.7 0.7 –10 10 3 2.7 3 0.3 0.3 90 V V Ω pF V V μA pF V V V V μA ms ms V 0.3 53 –1 7 7 90 1 V μA μA μA μA l 2 Logic Inputs (OE, SHDN) High Level Input Voltage Low Level Input Voltage Input Current SENSE Input Leakage MODE Pull-Down Current to GND LVDS Pull-Down Current to GND 2.7 Control Inputs (SENSE, MODE, LVDS) Logic Outputs (LVDS Mode) 247 1.125 350 1.250 454 1.375 mV V 9003p 5 LTM9003 POWER REQUIREMENTS SYMBOL VCC1 VCC2 VDD ICC1 ICC1(SHDN) ICC2 ICC2(SHDN) IDD(ADC) PD(SHDN) PD(NAP) OVDD IOVDD(ADC) PD(ADC) PD(TOTAL) PARAMETER Mixer Supply Range Amplifier Supply Range ADC Analog Supply Voltage Mixer Supply Current Mixer Shutdown Supply Current Amplifier Supply Current ADC Supply Current ADC Shutdown Power ADC Nap Mode Power ADC Digital Output Supply Voltage ADC Digital Output Supply Current ADC Power Dissipation Total Power Dissipation SHDN = 0V, MIX_EN = AMP_EN = 3V, fSAMPLE = MAX (LTM9003-AA) (LTM9003-AB) SHDN = 3V, OE = 3V, No CLK SHDN = 3V, OE = 0V, No CLK l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS LTM9003-AA LTM9003-AB MIN 2.9 4.5 2.8 2.375 MIX_EN = 3V, LTM9003-AA MIX_EN = 5V, LTM9003-AB MIX_EN = 0V AMP_EN = 3V l l l l l TYP 3.3 5 3.3 2.5 82 78 104 3 285 TBD TBD MAX 3.9 5.25 5.25 2.625 92 88 100 140 5 320 UNITS V V V V mA mA μA mA mA mA mW mW Amplifier Shutdown Supply Current AMP_EN = 0V LVDS Output Mode 2.375 2.5 58 858 1472 1591 2.625 70 975 V mA mW mW mW 9003p 6 LTM9003 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL fs tL tH tJITTER tAP tOE LVDS Output Mode tD tC ENC to DATA delay ENC to CLKOUT Delay DATA to CLKOUT Skew Rise Time Fall Time Pipeline Latency Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). (Note 5) (Note 5) (tC – tD) (Note 5) l l l TIMING CHARACTERISTICS PARAMETER Sampling Frequency ENC Low Time ENC High Time CONDITIONS l MIN 1 1.9 1.5 1.9 1.5 l l l l TYP 2 2 2 2 95 0 MAX 250 500 500 500 500 UNITS MHz ns ns ns ns fsRMS ns Duty Cycle Stabilizer Off (Note 5) Duty Cycle Stabilizer On (Note 5) Duty Cycle Stabilizer Off (Note 5) Duty Cycle Stabilizer On (Note 5) Sample-and-Hold Acquisition Delay Time Jitter Sample-and-Hold Aperture Delay Output Enable Delay (Note 5) l 5 1 1 –0.6 1.7 1.7 0 0.5 0.5 5 10 2.8 2.8 0.6 ns ns ns ns ns ns Cycles Note 3: VCC1 = VCC2 = 3.3V (LTM9003-AA) or VCC1 = 5V, VCC2 = 3.3V (LTM9003-AB), VDD = 2.5V, OVDD = 2.5V, fSAMPLE = 250MHz, input range = –1dBFS, differential ENC+/ENC– = 2VP–P sine wave, unless otherwise noted. Note 4: Integral nonlinearity is defined as the deviation of a code from a “best straight line” fit to the transfer curve. The deviation is measured from the center of the quantization band. Note 5: Guaranteed by design, not subject to test. 9003p 7 LTM9003 TIMING DIAGRAM tAP ANALOG INPUT N tH tL ENC– ENC+ tD D0-D11, OF tC N–5 N–4 N–3 N–2 N–1 N+1 N+2 N+3 N+4 CLKOUT– CLKOUT+ 9003 TD01 LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels 9003p 8 LTM9003 TYPICAL PERFORMANCE CHARACTERISTICS 64k Point FFT, LTM9003-AA fIN = 1950MHz –10 –1dBFS –20 SENSE = VDD –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 20 40 60 80 FREQUENCY (MHz) 100 120 9003 G01 64k Point 2-Tone FFT, LTM9003-AA fIN = 1948MHz, –10 f = 1952MHz IN –20 –7dBFS PER TONE SENSE = VDD –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 20 40 60 80 FREQUENCY (MHz) 100 120 9003 G02 SNR vs Frequency, LTM9003-AA 66 65 64 SNR (dBFS) 63 62 61 60 0 0 10 60 110 160 210 260 310 360 410 IF FREQUENCY (MHz) 9003 G03 IF Frequency Response, LTM9003-AA 0 –0.5 AMPLITUDE (dBFS) –1.0 –1.5 –2.0 –2.5 –3.0 110 AMPLITUDE (dBFS) 260 9003 G04 IF Frequency Response, LTM9003-AA 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 135 160 185 210 IF FREQUENCY (MHz) 235 –50 10 60 110 160 210 260 310 360 410 IF FREQUENCY (MHz) 9003 G05 9003p 9 LTM9003 TYPICAL PERFORMANCE CHARACTERISTICS 64k Point FFT, LTM9003-AB fIN = 1950MHz –10 –1dBFS –20 SENSE = VDD –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 20 40 60 80 FREQUENCY (MHz) 100 120 9003 G06 64k Point 2-Tone FFT, LTM9003-AB fIN = 1948MHz, –10 f = 1952MHz IN –20 –7dBFS PER TONE SENSE = VDD –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 20 40 60 80 FREQUENCY (MHz) 100 120 9003 G07 SNR vs Frequency, LTM9003-AB 66 65 64 SNR (dBFS) 63 62 61 60 0 0 10 60 110 160 210 260 310 360 410 IF FREQUENCY (MHz) 9003 G08 IF Frequency Response, LTM9003-AB 0 –0.5 AMPLITUDE (dBFS) –1.0 –1.5 –2.0 –2.5 –3.0 110 AMPLITUDE (dBFS) 260 9003 G09 IF Frequency Response, LTM9003-AB 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 135 160 185 210 IF FREQUENCY (MHz) 235 –50 10 60 110 160 210 260 310 360 410 IF FREQUENCY (MHz) 9003 G10 9003p 10 LTM9003 PIN FUNCTIONS VCC1 (Pins E1, E2, F2): 3.3V (LTM9003-AA) or 5V (LTM9003-AB) Supply Voltage for the Mixer. VCC1 is internally bypassed to GND. VCC2 (Pins B1, B2): 3.3V Supply Voltage for the Amplifier. VCC2 is internally bypassed to GND. VDD (Pins D11, E7, E8): 2.5V Supply Voltage for ADC. VDD is internally bypassed to GND. OVDD (Pins G12, H9, H11): Positive Supply for the Output Drivers. Bypass to ground with 0.1μF ceramic chip capacitor. OVDD can be 0.5V to 2.6V. OVDD is internally bypassed to OGND. GND (See Table for Locations): Module Ground. OGND (Pins F12, H8, H10, H12, J12): Output Driver Ground. RF (Pin G1): Single-Ended Input for the RF Signal. This pin is internally connected to the primary side of the RF input transformer, which has low DC resistance to ground. If the RF source is not DC blocked, then a series blocking capacitor must be used. The RF input is internally matched from 1.1GHz to 1.8GHz. Operation down to 400MHz or up to 3.8GHz is possible with simple external matching. LO (Pin J2): Single-Ended Input for the Local Oscillator Signal. This pin is internally connected to the primary side of the LO transformer, which is internally DC blocked. An external blocking capacitor is not required. The LO input is internally matched from 0.9GHz to 3.5GHz. Operation down to 380MHz is possible with simple external matching. MIX_EN (Pin F4): Mixer Enable Pin. Connecting MIX_EN to VCC1 results in normal operation. Connecting MIX_EN to GND disables the mixer. The MIX_EN pin should not be left floating. AMP_EN (Pin C3): Amplifier Enable Pin. This pin is internally pulled high by a typically 30k resistor to VCC2. Connecting AMP_EN to VCC2 results in normal operation. Connecting AMP_EN to GND disables the amplifier. ENC+ (Pin D12): ADC Encode Input. Conversion starts on the positive edge. ENC– (Pin E12): ADC Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1μF ceramic for single-ended ENCODE signal. 9003p SHDN (Pin B11): ADC Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin C11): Output Enable Pin. Refer to SHDN pin function. MODE (Pin C7): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 VDD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin G7): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range. LVDS (Pin D7): Output Mode Selection Pin. Connect LVDS to VDD. Digital Outputs D0–/D0+ – D11–/D11+ (See Table for Locations): LVDS Digital Outputs. All LVDS outputs require differential 100Ω termination resistors at the LVDS receiver. D11–/D11+ is the MSB. CLKOUT–/CLKOUT+ (Pins J10/J11): LVDS Data Valid Output. Latch data on rising edge of CLKOUT–, falling edge of CLKOUT+. OF–/OF+ (Pins E5/F5): LVDS Over/Under Flow Output. High when an over or under flow has occurred. 11 LTM9003 PIN FUNCTIONS Pin Configuration J H G F E D C B A GND GND RF GND VCC1 GND GND VCC2 GND 1 LO GND GND VCC1 VCC1 GND GND VCC2 GND 2 GND GND GND GND GND GND AMP_EN GND GND 3 GND GND GND MIX_EN GND GND GND GND GND 4 GND GND GND OFP OFN GND GND GND GND 5 D9+ D9– D10– D10+ D11– D11+ GND GND GND 6 D8+ D8– SENSE GND VDD LVDS MODE GND GND 7 D6+ OGND D7+ GND VDD D4+ D4– GND GND 8 D6– OVDD D7– GND GND D3+ D3– D2+ D2– 9 CLKOUT+ OGND D5+ GND GND D1+ D1– D0+ D0– 10 CLKOUT– OVDD D5– GND GND VDD OE SHDN GND 11 OGND OGND OVDD OGND ENC– ENC+ GND GND GND 12 Top View of LGA Package (Looking Through Component) BLOCK DIAGRAM VCC1 VCC2 VDD MODE LVDS SHDN OE OVDD RF OF INPUT S/H BPF LPF PIPELINED ADC SECTIONS CONTROL LOGIC SHIFT REGISTER/ ERROR CORRECTION OGND INTERNAL CLOCK SIGNALS REFH REFL OUTPUT DRIVERS CLKOUT D11 … D0 1.25V REFERENCE RANGE SELECT REFERENCE BUFFER DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER DIFFERENTIAL REFERENCE AMPLIFIER 100Ω GND ENC– ENC+ 9003 BD01 MIX_EN LO AMP_EN SENSE Figure 1. Simplified Block Diagram 9003p 12 LTM9003 OPERATION DESCRIPTION The LTM9003 is an integrated system in a package (SiP) that includes a high-speed 12-bit A/D converter, a wideband filter and an active mixer. The LTM9003 is designed for IF sampling, digital pre-distortion (DPD) applications, also known as transmit observation path receivers, with RF input frequencies up to 3.8GHz. Typical applications include multicarrier base stations and telecom test instrumentation. Digital pre-distortion is a technique often used in thirdgeneration (3G) wireless base stations to improve the linearity of power amplifiers (PA). Improved PA linearity allows for a lower power PA to be used and therefore save a significant amount of power in the base station. The DPD receiver captures the PA output, digitizes it and feeds it back where the distortion can be analyzed. A complementary distortion is then introduced to the transmit DAC thereby pre-distorting the signal. A significant factor in PA linearity is the distortion caused by the odd order intermodulation (IM) products. The bandwidth to be digitized is equivalent to the signal bandwidth multiplied by the order of the IM product to be canceled. For example, four carrier WCDMA consumes 20MHz of signal bandwidth; therefore, to capture the fifth order IM product requires 100MHz. The Nyquist theory requires that the ADC sample rate be at least twice that frequency. However, simply doubling the captured bandwidth to set the sample rate may not be the best choice. Selecting the exact ADC sample rate and intermediate frequency (IF) depends on other factors within the system. To simplify filtering, the sample rate is often set at a multiple of the chip rate. The chip rate for WCDMA is 3.84MHz; selecting an ADC sample rate of 64 times the chip rate gives 245.76Msps. Placing the IF at 3/4ths the sample rate (fS) gives 184.32MHz and allows the entire bandwidth to fall within the second Nyquist zone. Many other frequency plans may be acceptable. The following sections describe in further detail the operation of each functional element of the LTM9003. The SiP technology allows the LTM9003 to be customized and this is described in the Semi-Custom Options section. The outline of the remaining sections follows the basic functional elements as shown in Figure 2. MIXER FILTER IF AMPLIFIER FILTER ADC 9003 F02 Figure 2. Basic Functional Elements The mixer dominates the noise figure calculation as would be expected. The overall gain is optimized for the dynamic range of the ADC relative to the RF input level allowed by the mixer. The equivalent cascaded noise figure is 9.1dB (LTM9003-AA) and 9.9dB (LTM9003-AB). The bandpass filter is a second order L-C filter following the mixer and a lowpass filter following the amplifier provides anti-alias and noise limiting. SEMI-CUSTOM OPTIONS The μModule construction affords a new level of flexibility in application-specific standard products. Standard ADC and amplifier components can be integrated regardless of their process technology and matched with passive components to a particular application. The LTM9003-AA, as the first example, is configured with a 12-bit ADC sampling at rates up to 250Msps. The total system gain is approximately 10.8dB. The IF is fixed by the bandpass filter at 184MHz with 125MHz bandwidth. The RF range is matched for 1.1GHz to 1.8GHz with low side LO. However, other options are possible through Linear Technology’s semi-custom development program. Linear Technology has in place a program to deliver other speed, resolution, IF range, gain and filter configurations for nearly any specified application. These semi-custom designs are based on existing ADCs and amplifiers with an appropriately modified matching network. The final subsystem is then tested to the exact parameters defined for the application. The final result is a fully integrated, accurately tested and optimized solution in the same package. For more details on the semi-custom receiver subsystem program, contact Linear Technology. Down-Converting Mixer The mixer stage consists of a high linearity double-balanced mixer, RF buffer amplifier, high speed limiting LO buffer amplifier and bias/enable circuits. The RF and LO 9003p 13 LTM9003 OPERATION inputs are both single ended. Low side or high side LO injection can be used. The mixer’s RF input consists of an integrated transformer and a high linearity differential amplifier. The primary terminals of the transformer are connected to the RF input (Pin G1) and ground. The secondary side of the transformer is internally connected to the amplifier’s differential inputs. The mixer’s LO input consists of an integrated transformer and high speed limiting differential amplifiers. The amplifiers are designed to precisely drive the mixer for the highest linearity and the lowest noise figure. Wideband Filter Most of the IF filtering is done between the mixer and the IF amplifier. This network is a 2nd order Chebychev bandpass section, designed for 0.1dB passband ripple. The 3dB bandwidth is 220MHz, centered at 184MHz, see Figure 3. Additional lowpass filtering is done just before the ADC. This filter serves to bandlimit the out of band noise entering the converter, as well as to isolate the output of the IF amplifier from the sampling action of the converter. 0 –5 –10 AMPLITUDE (dBFS) –15 –20 –25 –30 –35 –40 –45 –50 10 60 110 160 210 260 310 360 410 IF FREQUENCY (MHz) 9003 F03 Analog to Digital Converter As shown in Figure 1, the analog-to-digital converter (ADC) is a CMOS pipelined multistep converter. The converter has five pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). The encode input is differential for improved common mode noise immunity. The ADC has two phases of operation, determined by the state of the differential ENC+/ENC– input pins. For brevity, the text will refer to ENC+ greater than ENC– as ENC high and ENC+ less than ENC– as ENC low. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and visa versa. When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the Block Diagram. At the instant that ENC transitions from low to high, the sampled input is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fifth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. Figure 3. IF Filter Response 9003p 14 LTM9003 APPLICATIONS INFORMATION RF Input Port The mixer’s RF input is shown in Figure 4 and is internally matched from 1.1GHz to 1.8GHz, requiring no external components over this frequency range. The input return loss, shown in Figure 5, is typically 12dB at the band edges. The input match at the lower band edge can be optimized with a shunt 3.3pF capacitor at Pin G1, which improves the 0.8GHz return loss to greater than 25dB. Likewise, the 2GHz match can be improved to greater than 25dB with a series 3.9nH inductor and a 1pF shunt capacitor. Measured RF input return losses for these three cases are plotted in Figure 5. LOW-PASS MATCH FOR 450MHz, 900MHz and 3.6GHz RF RFIN ZO = 50Ω L = L (mm) C5 9003 F04 This series transmission line/shunt capacitor matching topology allows the LTM9003 to be used for multiple frequency standards without circuit board layout modifications. The series transmission line can also be replaced with a series chip inductor for a more compact layout. RF input impedance and S11 versus frequency (with no external matching) are listed in Table 1 and referenced to Pin G1. The S11 data can be used with a microwave circuit simulator to design custom matching networks and simulate board-level interfacing to the RF input filter. Table 1a. RF Input Impedance vs Frequency (LTM9003-AA) FREQUENCY (MHz) 500 S11 INPUT IMPEDANCE 20.3 + j7 23.6 + j6.7 27.1 + j6.1 30.8 + j5.3 34.9 + j4.2 39.4 + j2.9 44.6 + j1.4 50.1 56 – j1 61.5 – j1.2 66 – j0.3 68.7 + j1.4 69 + j3.2 67.5 + j4.5 64.3 + j4.7 60.8 + j4.1 56.7 + j2.8 52.7 + j1.2 48.6 – j0.6 44.7 – j2.3 40.8 – j4 37 – j5.3 33.1 – j6.3 29.4 – j6.9 26 – j7 22.9 – j6.7 MAG 0.57 0.53 0.48 0.43 0.38 0.33 0.28 0.22 0.17 0.14 0.14 0.17 0.22 0.27 0.32 0.36 0.4 0.43 0.46 0.48 0.5 0.51 0.52 0.53 0.53 0.53 ANGLE 143 137.9 132.7 127 120.4 112.6 102.8 89.8 70.4 42.2 6.6 –21.5 –41 –54 –64.3 –72.2 –79.5 –85.8 –92.1 –98 –104.3 –110.5 –117.2 –124.3 –131.7 –139.6 LTM9003 TO MIXER RF 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 RFIN L5 C5 HIGH-PASS MATCH FOR 2.6GHz RF AND WIDEBAND RF Figure 4. RF Input Schematic 0 –5 –10 –15 –20 –25 –30 100 2GHz MATCH (3.9nH + 1pF) RF PORT RETURN LOSS (dB) NO MATCHING ELEMENTS 800MHz MATCH (3.3pF) 1000 FREQUENCY (MHz) 10000 9003 F05 Figure 5. RF Input Return Loss with and without Matching 9003p 15 LTM9003 APPLICATIONS INFORMATION Table 1b. RF Input Impedance vs Frequency (LTM9003-AB) FREQUENCY (MHz) 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 S11 INPUT IMPEDANCE 19.8 + j7.3 22.7 + j7 25.7 + j6.6 28.8 + j5.9 32.3 + j5.1 36.1 + j3.9 40.5 + j2.6 45.4 + j1.1 50.8 – j0.2 56.3 – j0.9 61.4 – j0.7 65.3 + j0.5 67.4 + j2.4 67.3 + j4.1 65.7 + j5.1 63.2 + j5.2 60.4 + j4.7 57.6 + j3.7 55 + j2.6 52.4 + j1.3 49.9 47.4 – j1.4 44.8 – j2.7 41.9 – j3.9 39 – j5 35.7 – j5.9 MAG 0.59 0.55 0.51 0.47 0.42 0.38 0.32 0.26 0.2 0.15 0.12 0.14 0.19 0.25 0.31 0.37 0.42 0.46 0.49 0.51 0.53 0.54 0.55 0.55 0.55 0.54 ANGLE 143 138.4 133.9 129.2 123.9 117.9 110.6 101.3 87.6 65.6 27.5 –13.1 –37.9 –52.4 –61.9 –68.9 –74.4 –79.1 –83 –86.7 –90.1 –93.7 –97.3 –101.6 –106.3 –111.9 VCC2 9003 F06 LTM9003 EXTERNAL MATCHING FOR LO < 1GHz LOIN L4 C4 REGULATOR LO LIMITER VREF TO MIXER Figure 6. LO Input Schematic Custom matching networks can be designed using the port impedance data listed in Table 2. This data is referenced to the LO pin with no external matching. Table 2a. LO Input Impedance vs Frequency (LTM9003-AA) FREQUENCY (MHz) 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 S11 INPUT IMPEDANCE 10.3 – j6.1 9.7 + j2.2 18.7 + j8.2 37 + j6.2 64.5 – j9.9 109.7 – j42.2 206.6 – j35.9 183.8 + j70 115.4 + j59.4 86.7 + j35.2 70.7 + j18.5 59.3 + j7.4 50.2 + j0.2 42.6 – j4.5 35.9 – j7.2 30.2 – j8.3 25.6 – j8.1 22.4 – j6.7 20.8 – j4.6 21.5 – j2.1 24.2 28.9 + j1.3 35.3 + j1.5 42.6 + j0.9 50.3 57.7 – j0.6 MAG 0.73 0.68 0.64 0.6 0.59 0.6 0.63 0.66 0.68 0.7 0.71 0.7 0.7 0.68 0.66 0.63 0.59 0.54 0.48 0.42 0.35 0.28 0.21 0.16 0.12 0.1 ANGLE –159.1 172.4 141.8 108.4 72.7 38.3 7.9 –17.1 –37.3 –53.7 –67.4 –79.2 –89.7 –99.6 –109.2 –118.9 –129.2 –140.3 –152.3 –165.5 –179.8 163.9 145.1 121.1 88.6 45.8 9003p LO Input Port The mixer’s LO input, shown in Figure 6, is internally matched from 0.9GHz to 3.5GHz. LO input matching near 600MHz requires the series inductor (L4)/shunt capacitor (C4) network shown in Figure 6. Likewise, the 2GHz match can be improved by using L4 = 2.7μH, C4 = 0.5pF . Measured LO input return losses for these three cases are plotted in Figure 7. The optimum LO drive is –3dBm for LO frequencies above 1.2GHz, although the amplifiers are designed to accommodate several dB of LO input power variation without significant mixer performance variation. Below 1.2GHz, 0dBm LO drive is recommended for optimum noise figure, although –3dBm will still deliver good conversion gain and linearity. 16 LTM9003 APPLICATIONS INFORMATION Table 2b. LO Input Impedance vs Frequency (LTM9003-AB) FREQUENCY (MHz) 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 S11 INPUT IMPEDANCE 14.3 – j7.5 12.6 – j2.4 15.8 + j1.9 22.7 + j4.1 32.5 + j3.8 44.2 + j1.3 56.3 – j1.2 66 – j1.3 70.7 + j1 69.9 + j3.1 66 + j3.7 61.8 + j3.3 58.1 + j2.4 54.9 + j1.5 52.7 + j0.8 50.7 + j0.2 49.4 – j0.2 47.8 – j0.5 46.7 – j0.7 45.7 – j0.8 45.5 – j0.7 46.4 – j0.4 48.7 – j0.1 50.9 + j0.1 52.9 + j0.3 54.6 + j0.5 MAG 0.68 0.61 0.53 0.44 0.35 0.25 0.18 0.15 0.18 0.21 0.25 0.27 0.28 0.29 0.28 0.28 0.27 0.25 0.23 0.2 0.17 0.13 0.1 0.09 0.09 0.11 ANGLE –150.6 –170.4 170.8 151.5 130.2 104.9 70.3 26.4 –12.8 –37.8 –54.1 –65.5 –73.4 –79.8 –84.2 –88.5 –91.4 –95.5 –98.9 –103.3 –106.8 –107.1 –97.9 –84.2 –72.5 –66.7 Mixer Enable Interface The voltage necessary to turn on the mixer is 2.7V. To disable the mixer, the enable voltage must be less than 0.3V. If the MIX_EN pin is allowed to float, the mixer will tend to remain in its last operating state. Thus it is not recommended that the enable function be used in this manner. If the shutdown function is not required, then the MIX_EN pin should be connected directly to VCC1. Amplifier Enable Interface The AMP_EN pin self-biases to VCC2 through a 30k resistor. The pin must be pulled below 0.8V in order to disable the amplifier. Driving the ADC Clock Input The noise performance of the ADC can depend on the encode signal quality as much as on the analog input. The ENC+/ENC– inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 4.8k resistor to a 1.5V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies) take the following into consideration: 1. Differential drive should be used. 2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3. If the ADC is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 0 –5 RETURN LOSS (dB) –10 –15 –20 –25 –30 100 NO MATCHING ELEMENTS 2GHz MATCH (2.7nH + 0.5pF) 1000 FREQUENCY (MHz) 10000 9003 F07 600MHz MATCH (6.8nH + 5.6pF) 4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.2V to 2.0V. Each input may be driven from ground to VDD for single-ended drive. 9003p Figure 7. LO Input Return Loss with and without Matching 17 LTM9003 APPLICATIONS INFORMATION LTM9003 VDD TO INTERNAL ADC CIRCUITS T1 MA/COM 0.1μF ETC1-1-13 VDD ENC+ 1.5V BIAS 4.8k CLOCK INPUT • • The lower limit of the sample rate is determined by the droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTM9003 is 1Msps. Clock Duty Cycle Stabilizer An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the ENC+ pin to sample the analog input. The falling edge of ENC+ is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. Clock Sources for Undersampling Undersampling is especially demanding on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. A clock source that degrades SNR of a full-scale signal by 1dB at 70MHz will degrade SNR by 3dB at 140MHz, and 4.5dB at 190MHz. In cases where absolute clock frequency accuracy is relatively unimportant and only a single ADC is required, a canned oscillator from vendors such as Saronix or Vectron can be placed close to the ADC and simply connected directly to the ADC. If there is any distance to the ADC, some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. You must not allow the clock to overshoot the supplies or performance will suffer. Do not filter the clock signal with a narrow band filter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise. 50Ω 8.2pF 50Ω ENC– 0.1μF 1.5V BIAS 100Ω V DD 4.8k 0.1μF 9003 F08 Figure 8. Transformer Driven ENC+/ENC– VTHRESHOLD = 1.5V ENC+ 1.5V ENC– 0.1μF 9003 F09 LTM9003 Figure 9. Single-Ended ENC Driver, Not Recommended for Low Jitter 0.1μF LVDS CLOCK ENC+ LTM9003 100Ω 0.1μF ENC– 9003 F10 Figure 10. ENC Drive Using LVDS Maximum and Minimum Conversion Rates The maximum conversion rate for the ADC is 250Msps. For the ADC to operate properly, the encode signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 1.9ns for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. 9003p 18 LTM9003 APPLICATIONS INFORMATION The lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a filter close to the ADC may be beneficial. This filter should be close to the ADC to both reduce roundtrip reflection times, as well as reduce the susceptibility of the traces between the filter and the ADC. If the circuit is sensitive to closein phase noise, the power supply for oscillators and any buffers must be very stable, or propagation delay variation with supply will translate into phase noise. Even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. If your clock is also used to drive digital devices such as an FPGA, you should locate the oscillator, and any clock fan-out devices close to the ADC, and give the routing to the ADC precedence. The clock signals to the FPGA should have series termination at the driver to prevent high frequency noise from the FPGA disturbing the substrate of the clock fan-out device. If you use an FPGA as a programmable divider, you must re-time the signal using the original oscillator, and the re-timing flip-flop as well as the oscillator should be close to the ADC, and powered with a very quiet supply. For cases where there are multiple ADCs, or where the clock source originates some distance away, differential clock distribution is advisable. This is advisable both from the perspective of EMI, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multilayer PCBs. The differential pairs must be close together and distanced from other signals. The differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart. Digital Outputs Table 3 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit. Table 3. Output Codes vs Input Voltage INPUT (SENSE = VDD) Overvoltage Maximum OF 1 0 0 0 0 0 0 0 0 1 D11 – D0 (OFFSET BINARY) 1111 1111 1111 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 0000 0000 0000 D11 – D0 (2’S COMPLEMENT) 0111 1111 1111 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 1000 0000 0000 0.000000V Minimum Undervoltage Digital Output Buffers Figure 11 shows an equivalent circuit for a differential output pair in the LVDS output mode. A 3.5mA current is steered from OUT+ to OUT– or vice versa which creates a ±350mV differential voltage across the 100Ω termination resistor at the LVDS receiver. A feedback loop regulates the common mode output voltage to 1.25V. For proper operation each LVDS output pair needs an external 100Ω LTM9003 OVDD 2.5V 0.1μF D – + 1.25V D 10k 10k D OUT+ 100Ω OUT– D LVDS RECEIVER 3.5mA OGND 9003 F11 Figure 11. Digital Output in LVDS Mode 9003p 19 LTM9003 APPLICATIONS INFORMATION termination resistor, even if the signal is not used (such as OF+/OF– or CLKOUT+/CLKOUT–). To minimize noise the PC board traces for each LVDS output pair should be routed close together. To minimize clock skew all LVDS PC board traces should have about the same length. Data Format The LTM9003 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MODE pin. Connecting MODE to GND or 1/3VDD selects offset binary output format. Connecting MODE to 2/3VDD or VDD selects 2’s complement output format. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 5 shows the logic states for the MODE pin. Table 5. MODE Pin Function MODE PIN 0 1/3VDD 2/3VDD VDD OUTPUT FORMAT Straight Binary Straight Binary 2’s Complement 2’s Complement CLOCK DUTY CYCLE STABILIZER Off On On Off Output Enable The outputs may be disabled with the output enable pin, OE. In LVDS output mode OE high disables all data outputs including OF and CLKOUT. The data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long periods of inactivity. The Hi-Z state is not a truly open circuit; the output pins that make an LVDS output pair have a 20k resistance between them. Sleep and Nap Modes The converter may be placed in shutdown or nap modes to conserve power. Connecting SHDN to GND results in normal operation. Connecting SHDN to VDD and OE to VDD results in sleep mode, which powers down all circuitry including the reference and the ADC typically dissipates 1mW. When exiting sleep mode, it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. Connecting SHDN to VDD and OE to GND results in nap mode and the ADC typically dissipates 30mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep and nap modes, all digital outputs are disabled and enter the Hi-Z state. Supply Sequencing The VCC1 and VCC2 pins provide the supply to the mixer and amplifier, respectively, and the VDD pin provides the supply to the ADC. The mixer, amplifier and ADC are separate integrated circuits within the LTM9003. Separate linear regulators can be used without additional supply sequencing circuitry if they have common input supplies. Overflow Bit An overflow output bit indicates when the converter is overranged or underranged. A differential logic high on the OF+/OF– pins indicates an overflow or underflow. Output Clock The LTM9003 has a delayed version of the ENC+ input available as a digital output, CLKOUT. The CLKOUT pin can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. Data will be updated just after CLKOUT+/CLKOUT– rises and can be latched on the falling edge of CLKOUT+/CLKOUT–. Output Driver Power OVDD should be connected to a 2.5V supply and OGND should be connected to GND. 9003p 20 LTM9003 APPLICATIONS INFORMATION Grounding and Bypassing The LTM9003 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the LTM9003 has been optimized for a flow-through layout so that the interaction between inputs and digital outputs is minimized. Ample ground pads facilitate a layout that ensures that digital and analog signal lines are separated as much as possible. The LTM9003 is internally bypassed with the ADC (VDD), amplifier (VCC2) and mixer (VCC1) supplies returning to a common ground (GND). The digital output supply (OVDD) is returned to OGND. Additional bypass capacitance is optional and may be required if power supply noise is significant. Heat Transfer Most of the heat generated by the LTM9003 is transferred through the bottom-side ground pads. For good electrical and thermal performance, it is critical that all ground pins are connected to a ground plane of sufficient area with as many vias as possible. Recommended Layout The high integration of the LTM9003 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. • Use large PCB copper areas for ground. This helps to dissipate heat in the package through the board and also helps to shield sensitive on-board analog signals. Common ground (GND) and output ground (OGND) are electrically isolated on the LTM9003, but can be connected on the PCB underneath the part to provide a common return path. • Use multiple ground vias. Using as many vias as possible helps to improve the thermal performance of the board and creates necessary barriers separating analog and digital traces on the board at high frequencies. • Separate analog and digital traces as much as possible, using vias to create high-frequency barriers. This will reduce digital feedback that can reduce the signal-to-noise ratio (SNR) and dynamic range of the LTM9003. Figures 12 through 15 give a good example of the recommended layout. The quality of the paste print is an important factor in producing high yield assemblies. It is recommended to use a type 3 or 4 printing no-clean solder paste. The solder stencil design should follow the guidelines outlined in Application Note 100. The LTM9003 employs gold-finished pads for use with Pb-based or tin-based solder paste. It is inherently Pb-free and complies with the JEDEC (e4) standard. The materials declaration is available online at http://www.linear. com/leadfree/mat_dec.jsp. 9003p 21 LTM9003 APPLICATIONS INFORMATION Figure 12. Layer 1 Component Side Figure 13. Layer 2 Figure 14. Layer 3 Figure 15. Backside 9003p 22 LGA Package 108-Lead (15mm × 11.25mm × 2.32mm) (Reference LTC DWG # 05-08-1757 Rev Ø) DETAIL A X Y J H G MOLD CAP SUBSTRATE 10.16 BSC 0.27 – 0.37 1.95 – 2.05 Z 1.27 BSC // bbb Z D C B DETAIL B aaa Z PADS SEE NOTES 12 11 10 9 8 3 DETAIL B 1.905 3.175 4.445 5.715 6.985 0.630 ±0.025 SQ. 108x eee S X Y 7 6 5 4 3 2 1 A DIA (0.635) PAD 1 11.25 BSC F E 2.22 – 2.42 13.97 BSC aaa Z 15 BSC 0.22 × 45° CHAMFER PACKAGE DESCRIPTION PAD 1 CORNER 4 PACKAGE TOP VIEW PACKAGE BOTTOM VIEW 6.985 5.715 4.445 3.175 1.905 5.080 3.810 2.540 DETAIL A 1.270 0.000 0.635 0.000 0.635 1.270 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3 4 LAND DESIGNATION PER JESD MO-222, SPP-010 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE COMPONENT PIN “A1” 2.540 LTMXXXXXX μModule 3.810 5.080 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. TRAY PIN 1 BEVEL SUGGESTED PCB LAYOUT TOP VIEW 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 108 SYMBOL TOLERANCE 0.15 aaa 0.10 bbb 0.05 eee PACKAGE IN TRAY LOADING ORIENTATION LGA 108 0707 REV Ø LTM9003 23 9003p LTM9003 RELATED PARTS PART NUMBER LTC2240-10 LTC2240-12 LTC2241-10 LTC2241-12 LTC2242-10 LTC2242-12 LTC6410 LT5527 LT5557 LTM9001 LTM9002 DESCRIPTION 10-Bit, 170Msps, 2.5V ADC, LVDS Outputs 12-Bit, 170Msps, 2.5V ADC, LVDS Outputs 10-Bit, 210Msps, 2.5V ADC, LVDS Outputs 12-Bit, 210Msps, 2.5V ADC, LVDS Outputs 10-Bit, 250Msps, 2.5V ADC, LVDS Outputs 12-Bit, 250Msps, 2.5V ADC, LVDS Outputs Differential IF Amplifier with Configurable Input Impedance 400MHz to 3.7GHz, 5V High Signal Level Downconverting Mixer 800MHz to 2.7GHz High Linearity Direct Conversion Quadrature Demodulator 16-Bit, IF/Receiver Subsystem COMMENTS 445mW, 60.6dB SNR, 78dB SFDR, 64-Pin QFN 445mW, 65.5dB SNR, 80dB SFDR, 64-Pin QFN 585mW, 60.6dB SNR, 78dB SFDR, 64-Pin QFN 585mW, 65.5dB SNR, 78dB SFDR, 64-Pin QFN 740mW, 60.5dB SNR, 78dB SFDR, 64-Pin QFN 740mW, 65.4dB SNR, 78dB SFDR, 64-Pin QFN 1.4GHz, –3dB BW, 6dB Fixed Voltage Gain (50Ω System), 36dBm OIP3 23.5dBm IIP3 at 1.9GHz, NF = 12.5dB, Single-Ended RF and LO Ports 24.7dBm IIP3 at 1.9GHz, NF = 11.7dB, Single-Ended RF and LO Ports, 3.3V Supply 16-Bit, 130Msps ADC, 20dB Gain Amplifier, Anti-Alias Filter, Internal Bypass Capacitance Dual 14-Bit, IF/Baseband Receiver Subsystem Dual 14-Bit, 125Msps ADC, dual 26dB Gain Amplifiers, Anti-Alias Filters, Auxiliary DAC for Gain Adjustment, Internal Bypass Capacitance 9003p 24 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0709 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2009