SPLV2.8

TVS Diode Arrays (SPA™ Family of Products) Lightning Surge Protection - SPLV2.8 Series SPLV2.8 Series 2.8V 50A TVS Array Description RoHS Pb GREEN Features Pinout 3 ±30kV contact, ±30kV air (5/50ns) 40A (8/20μs) Applications 1 2 per line (Pin 2 to 1) 1μA (MAX) at 2.8V saves board space Functional Block Diagram Notebooks 3 Application Example NC 1 2 RJ-45 Connector J1 Ethernet PHY J8 NC See Application Example Detail section on page 135 for more information ©2011 Littelfuse, Inc. Specifications are subject to change without notice. Please refer to www.littelfuse.com/SPA for current information. 121 Revision: April 14, 2011 SPLV2.8 Series SPLV2.8 The SPLV2.8 was designed to protect low voltage, CMOS devices from ESD and lightning induced transients. There is a compensating diode in parallel with the low voltage TVS to protect one unidirectional line or a high speed data pair when two devices are paired together. These robust structures can safely absorb repetitive ESD strikes at ±30kV (contact discharge) per the IEC61000-4-2 standard and each structure can safely dissipate up to 40A (IEC61000-4-5, tP=8/20μs) with very low clamping voltages. TVS Diode Arrays (SPA™ Family of Products) Lightning Surge Protection - SPLV2.8 Series Electrical Characteristics (TOP = 25°C) Parameter Reverse Standoff Voltage Reverse Breakdown Voltage Snap Back Voltage Reverse Leakage Current Clamping Voltage Clamping Voltage 1 1 Symbol VRWM VBR VSB ILEAK Test Conditions IR≤1μA IT=2μA IT=50mA VR=2.8V (Pin 2 or 3 to 1) IPP=5A, tP=8/20μs (Pin 3 to 1) Min Typ Max 2.8 Units V V V 3.0 2.8 1 5.7 8.3 7 .0 13.9 0.4 ±30 ±30 2.0 2.5 7 .0 12.5 8.5 15.0 μA V V V V Ω kV kV pF Clamping Voltage1 Clamping Voltage1 Dynamic Resistance ESD Withstand Voltage1 Diode Capacitance 1 VC IPP=24A, tP=8/20μs (Pin 3 to 1) IPP=5A, tP=8/20μs (Pin 2 to 1) IPP=24A, tP=8/20μs (Pin 2 to 1) RDYN VESD CD (VC2 - VC1) / (IPP2 - IPP1) (Pin 2 to 1) IEC61000-4-2 (Contact) IEC61000-4-2 (Air) VR=0V, f=1MHz (Pin 2 to 1) Note: 1Parameter is guaranteed by design and/or device characterization. Absolute Maximum Ratings Parameter Peak Pulse Power (tP=8/20μs) Peak Pulse Current (tP=8/20μs) Operating Temperature Storage Temperature Rating 600 40 -40 to 85 -60 to 150 Units W A ºC ºC Figure 1: Capacitance vs. Reverse Voltage 4.0 3.5 Capacitance (pF) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. DC Bias (V) Figure 2: Clamping Voltage vs. IPP 14 12 Figure 3: Pulse Waveform 110% 100% 90% Clamping Voltage-VC (V) Percent of IPP 10 8 6 4 2 0 0 5 10 15 20 25 80% 70% 60% 50% 40% 30% 20% 10% 0% 0.0 5.0 10.0 15.0 20.0 25.0 30.0 Peak Pulse Current-IPP (A) Time (μs) SPLV2.8 Series 122 Revision: April 14, 2011 ©2011 Littelfuse, Inc. Specifications are subject to change without notice. Please refer to www.littelfuse.com/SPA for current information. TVS Diode Arrays (SPA™ Family of Products) Lightning Surge Protection - SPLV2.8 Series Application Example Detail Data Line Product Characteristics Lead Plating Lead Material Lead Coplanarity Matte Tin Copper Alloy 0.0004 inches (0.102mm) Silicon Molded Epoxy UL94-V-0 Protection of one unidirectional line Subsitute Material Body Material Flammability Protection of one unidirectional data line is realized by connecting pin 3 to the protected line, and pins 1 and 2 to GND. In this configuration, the device presents a maximum loading capacitance of tens of picofarads. During positive transients, the internal TVS diode will conduct and steer current from pin 3 to 1 (GND), clamping the data line at or below the specified voltages for the device (see Electrical Characteristics section). For negative transients, the internal compensating diode is forward biased, steering the current from pin 2 (GND) to 3. D1 Notes : 1. All dimensions are in millimeters 2. Dimensions include solder plating. 3. Dimensions are exclusive of mold flash & metal burr. 4. All specifications comply to JEDEC SPEC MO-203 Issue A 5. Blo is facing up for mold and facing down for trim/form, i.e. reverse trim/form. 6. Package surface matte finish VDI 11-13. Soldering Parameters Reflow Condition Pb – Free assembly 150°C 200°C 60 – 180 secs 3°C/second max 3°C/second max 217°C 60 – 150 seconds 250+0/-5 °C 20 – 40 seconds 6°C/second max 8 minutes Max. 260°C NC - Temperature Min (Ts(min)) D2 Low capacitance protection of one high speed data pair Pre Heat - Temperature Max (Ts(max)) - Time (min to max) (ts) Low capacitance protection of a high-speed data pair is realized by connecting two devices in antiparallel. As shown, pin 1 of the first device is connected to D1 and pin 2 is connected to D2. Additionally, pin 2 of the second device is connected to D1 and pin 1 is connected to D2. Pin 3 must be NC (or not connected) for both devices. When the potential on D1 exceeds the potential on D2 (by the rated standoff voltage), pin 2 on the second device will steer current into pin 1. The compensating diode will conduct in the forward direction steering current into the avalanching TVS diode which is operating in the reverse direction. For the opposite transient, the first device will behave in the same manner. In this two device arrangement, the total loading capacitance is two times the rated capacitance from pin 2 to pin 1 which will typically be much less than 10pF making it suitable for highspeed data pair such as 10/100/1000 Ethernet. Average ramp up rate (Liquidus) Temp (TL) to peak TS(max) to TL - Ramp-up Rate Reflow - Temperature (TL) (Liquidus) - Temperature (tL) Peak Temperature (TP) Time within 5°C of actual peak Temperature (tp) Ramp-down Rate Time 25°C to peak Temperature (TP) Do not exceed TP Temperature Ramp-up Ramp-up tP Critical Zone Critical Zone TL to TP NC RJ-45 Connector J1 TL TS(max) Preheat Preheat tL Ramp-do Ramp-down TS(min) Ethernet PHY 25 tS time to peak temperature Time J8 NC ©2011 Littelfuse, Inc. Specifications are subject to change without notice. Please refer to www.littelfuse.com/SPA for current information. 123 Revision: April 14, 2011 SPLV2.8 Series SPLV2.8 TVS Diode Arrays (SPA™ Family of Products) Lightning Surge Protection - SPLV2.8 Series Package Dimensions — SOT-23 b 3 Package Pins JEDEC E1 E SOT23-3 3 TO-236 Millimetres Min Max 1.12 0.1 0.5 0.2 3.04 2.64 Min 0.035 0.0004 0.012 0.003 0.110 0.083 0.047 Inches Max 0.044 0.004 0.020 0.008 0.120 0.104 1 e e1 D 2 Recommended Pad Layout A A1 b c 0.89 0.01 0.3 0.08 2.8 2.1 1.2 0.95 BSC 1.90 BSC 0.54 REF A M P D E E1 e e1 L1 M N O P A1 1.4 0.055 0.038 BSC 0.075 BSC 0.021 REF C N O L1 2.29 0.95 0.78 .90 0.038 0.30 TYP 0.30 TYP 0.78 Part Numbering System Part Marking System SP LV2.8 H T G Silicon Protection Array (SPATM) Family of TVS Diode Arrays Series G= Green T= Tape & Reel Package H = SOT23-3 U 2.8 U2.8 Product Series U = SPLV2.8 Voltage Level Ordering Information Part Number SPLV2.8HTG Package SOT23-3 Marking U2.8 Min. Order Qty. 3000 Embossed Carrier Tape & Reel Specification — SOT23-3 Package P0 P1 D1 E D Symbol A0 B0 Millimetres Min 3.05 2.67 3.9 1.95 1.65 3.45 1.12 0.95 3.9 Max 3.25 2.87 4.1 2.05 1.85 3.55 1.32 1.05 4.1 1.6 7 .9 8.3 Inches Min 0.12 0.105 0.153 0.788 0.065 0.136 0.476 0.037 0.153 Max 0.128 0.113 0.161 0.792 0.073 0.14 0.484 0.041 0.161 0.063 0.311 0.327 F W P .99 .46 [.018] [.039] 9º MAX 8º MAX .229 ± .013 [.009 ± .0005] 2.06 [.081] .71 [.028] 13.5º MAX D D1 E F K0 P P0 P1 A0 K0 B0 W SPLV2.8 Series 124 Revision: April 14, 2011 ©2011 Littelfuse, Inc. Specifications are subject to change without notice. Please refer to www.littelfuse.com/SPA for current information.