L9D345G72BG5I15

A DVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) FEATURES DDR3 Integrated Module [iMOD]: • Vcc=VccQ=1.5V ± 0.075V • 1.5V center-terminated, push/pull I/O • Package: 25mm x 25mm, 16 x 16 matrix w/ 255 balls • Matrix ball pitch: 1.00mm Space saving footprint Thermally enhanced, Impedance matched, integrated packaging Differential, bidirectional data strobe 8n-bit prefetch architecture 8 internal banks (per word, 9 Bytes integrated in package) Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals. CAS (READ) latency (CL): 6, 8, and 10 CAS (WRITE) latency (CWL): 6, 7 and 8 Fixed burst length (BL) of 8 and burst chop (BC) of 4 Selectable BC4 or BL8 on-the-fly (OTF) Self/Auto Refresh modes Operating Temperature Range (Case Temp=Tc) • Industrial: -40˚C to 85˚C supporting SELF & AUTO REFRESH • Extended: -40˚C to 105˚C; manual REFRESH only • Mil-Temp: -55˚C to 125˚C; manual REFRESH only CORE clocking frequencies: • Industrial: 667MHz, 533MHz and 400MHz • Extended: 533MHz and 400MHz • Mil-Temp: 400MHz Data Transfer Rates: • Industrial: 1333, 1066 and 800 Mbps • Extended: 1066 and 800 Mbps • Mil-Temp: 800 Mbps Write leveling Multipurpose register Output Driver Calibration Benefits 20% space savings while providing a surface mount friendly pitch (1.00mm) Reduced I/O (46%) 25% improvement in routings for your memory array Reduced trace lengths due to the highly integrated, impedance matched packaging Thermally enhanced packaging technology allow silicon integration without performance degradation due to power dissipation (heat) High TCE organic laminate interposer for improved glass stability over a wide operating temperature Suitability of use in High Reliability applications requiring Mil-temp, nonhermetic device operation *Note: This integrated product is currently under consideration. Latest product status, information, and/ or corresponding documents should be obtained from LDI prior to your design considerations. iMOD Part Information ORDER NUMBER L9D345G72BG5I15 L9D345G72BG5E19 L9D345G72BG5M25 SPEED GRADE DDR3-1333 DDR3-1066 DDR3-800 DEVICE GRADE Industrial Extended Mil-Temp PKG FOOTPRINT I/O PITCH PKG NO. 25mm x 25mm 255 1.00mm BG5 integrated module products LOGIC Devices Incorporated www.logicdevices.com 1 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) INTEGRATED VS. MONOLITHIC SOLUTIONS - HIGHLIGHTS Monolithic Solu on O P T I O N S IMOD Solu on 25.0 DDR3 9.0mm x 15.5mm 96 ball FBGA D DR3 9.0mm x 15.5mm 96 ball FBGA DDR3 9.0mm x 15.5mm 96 ball FBGA DDR3 9.0mm x 15.5mm 96 ball FBGA DDR3 9.0mm x 15.5mm 96 ball FBGA 25.0 S A V I N G S Area I/O 5 x 139.5mm + component space = ~775mm 5 x 96 pins = 480 pins total 2 2 625 mm 2 255 Balls/Loca ons ~20% 46% TABLE 1: KEY TIMING PARAMETERS Device Grade INDUSTRIAL EXTENDED MIL-TEMP Speed Grade DDR3-1333 DDR3-1066 DDR3-800 Speed Mark 15 19 25 Part Ordering Information L9D345G72BG5I15 L9D345G72BG5E19 L9D345G72BG5M25 CORE Freq. [MHz] Support 667/533/400 533/400 400 Data Rate [Mbps] Support 1333/1066/800 1066/800 800 Target tRCD-tRP-CL tRCD tRP CL [ns] 15 15 15 [ns] 15 15 15 [ns] 15 15 15 10-10-10/8-8-8/6-6-6 8-8-8/6-6-6 6-6-6 LOGIC Devices Incorporated www.logicdevices.com 2 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A A DVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) FEATURES FIGURE 1 - 1Gb DDR3 PART NUMBERS Sample Part Number: L9D345G72BG5M15 L9D3 45G 72 BG5 DDR3 iMOD Total Density= 4.5Gb Organization= 64M x 72 Code 25 19 15 Speed Grade t CK = 2.50ns t CK = 1.875ns t CK = 1.5ns 25 x 25mm PBGA Temperature Industrial Temperature Extended Temperature Military Temperature Code I E M Note: Not all options can be combined. Please see our Part Catalog for available offerings. TABLE 2: ADDRESSING Parameter Configuration Refresh Count ROW Addressing Back Addressing Column Addressing 64 Meg x 72 [8 Meg x 8 banks x 16] x 4.5 8K 8K (A[12:0]) 8 (BA[2:0]) 1K (A[9:0]) LOGIC Devices Incorporated www.logicdevices.com 3 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) STATE DIAGRAM FIGURE 2 - SIMPLIFIED STATE DIAGRAM CKE L Power applied Power on Reset Procedure Initialization MRS, MPR, write leveling SRE MRS SRX Self refresh ZQCL From any state RESET ZQ Calibration ZQCL/ZQCS REF Idle Refreshing ACT PDE PDX Active PowerDown PDX CKE L PDE Activating Preharge PowerDown CKE L Bank Active WRITE WRITE WRITE AP READ AP READ WRITE READ READ Writing Reading WRITE AP WRITE AP READ AP READ AP PRE, PREA Writing PRE, PREA PRE, PREA Reading Preharging Automatic Sequence Command Sequence ACT = ACTIVATE MPR = Multipurpose register MRS = Mode register set PDE = Power-down entry PDX = Power-down exit PRE = PRECHARGE PREA=PRECHARGE ALL READ = RD, RDS4, RDS8 READ AP = RDAP, RDAPS4, RDAPS8 REF = REFRESH RESET = START RESET PROCEDURE SRE = Self refresh entry SRX = Self refresh exit WRITE = WR, WRS4, WRS8 WRITE AP = WRAP, WRAPS4, WRAPS8 ZQCL = ZQ LONG CALIBRATION ZQCS = ZQ SHORT CALIBRATION LOGIC Devices Incorporated www.logicdevices.com 4 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A A DVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) FUNCTIONAL DESCRIPTION The DDR3 SDRAM uses double data rate architecture to achieve high speed operation. The double data rate (DDR) architecture is an 8n prefetch with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE access for the DDR3 SDRAM consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal memory core and eight corresponding n-bit-wide, one-half-clock-cycle data transfer at the I/O pin. The differential strobes (LDQSx, LDQSx\, UDQSx, UDQSx\) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The READ data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CKx, CKx\). The crossing of CK going HIGH and CK\ going LOW is referred to as the positive edge of Clock (CK). Control, Command, and Address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. READ and WRITE accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and the starting column location for the burst access. DDR3 SDRAM devices use READ and WRITE BL8 and BC4. An AUTO PRECHARGE function may be enabled to provide a self-timed ROW PRECHARGE that is initiated at the end of the burst access. As with standard DDR SDRAM devices, the pipelined, multi-bank architecture of the DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding ROW PRECHARGE and ACTIVATION time. A SELF REFRESH mode is provided for all temperature grade offerings along with AUTO SELF REFRESH for Industrial product, as well as, powersaving, POWER-DOWN mode. INDUSTRIAL TEMPERATURE The industrial temperature (I) device requires the case temperature not exceed -40˚C or +85˚C. JEDEC specifications require the REFRESH rate to double when Tc exceeds +85˚C; this also requires use of the hightemperature SELF REFRESH option. Additionally, ODT resistance and the INPUT/OUTPUT impedance must be derated when the Tc is +85˚C. EXTENDED TEMPERATURE The Extended temperature (E) device requires the case temperature not exceed -40˚C or +105˚C. JEDEC specifications require the refresh rate to double when Tc exceeds +85˚C; this also requires use of the hightemperature SELF REFRESH option. Additionally, ODT resistance and the INPUT/OUTPUT impedance must be derated when the Tc is 85˚C. MILITARY, EXTREME OPERATING TEMPERATURE The Mil-Temp (M) device requires the case temperature not exceed -55˚C or +125˚C. JEDEC requires the REFRESH rate double when Tc exceeds +85˚C and LDI recommends an additional derating as specified in this document as to properly maintain the DRAM core cell charge at temperatures above Tc>105˚C. LOGIC Devices Incorporated www.logicdevices.com 5 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A A DVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) FIGURE 3 - FUNCTIONAL BLOCK DIAGRAM VCCQ VCC VSSQ VSS RESET\ A0-A12, BA0-1 CS0\ CK0 CK0\ LDQS0 LDQS0\ UDQS0 UDQS0\ CKE0 CAS0\ RAS0\ WE0\ LDM0 UDM0 A, BA RST\ VSS VSSQ VCC VCCQ DQ 0 DQ 0 D0 DQ 7 DQ 8 DQ 7 DQ 8 DQ 15 DQ 15 CS1\ CK1 CK1\ LDQS1 LDQS1\ UDQS1 UDQS1\ CKE1 CAS1\ RAS1\ WE1\ LDM1 UDM1 A, BA RST\ VSS VSSQ VCC VCCQ DQ 0 DQ 16 D1 DQ 7 DQ 8 DQ 23 DQ 24 DQ 15 DQ 31 CS2\ CK2 CK2\ LDQS2 LDQS2\ UDQS2 UDQS2\ CKE2 CAS2\ RAS2\ WE2\ LDM2 UDM2 A, BA RST\ VSS VSSQ VCC VCCQ DQ 0 DQ 32 D2 DQ 7 DQ 8 DQ 39 DQ 40 DQ 15 DQ 47 CS3\ CK3 CK3\ LDQS3 LDQS3\ UDQS3 UDQS3\ CKE3 CAS3\ RAS3\ WE3\ LDM3 UDM3 A, BA RST\ VSS VSSQ VCC VCCQ DQ 0 DQ 48 D3 DQ 7 DQ 8 DQ 55 DQ 56 DQ 15 DQ 63 CS4\ CK4 CK4\ LDQS4 LDQS4\ UDQS4 UDQS4\ CKE4 CAS4\ RAS4\ WE4\ LDM4 UDM4 A, BA RST\ VSS VSSQ VCC VCCQ DQ 0 DQ 64 D4 DQ 7 DQ 8 NC NC NC NC NC NC NC NC DQ 71 DQ 15 LOGIC Devices Incorporated www.logicdevices.com 6 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A A DVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) BALL /SIGNAL LOCATION (PBGA) FIGURE 4 - SDRAM - DDR3 PINOUT TOP VIEW 1 A B C D E F G H J K L M N P R T DQ1 DQ3 DQ6 DQ7 CAS0\ CS0\ VSS VSS CLK3\ NC DQ56 DQ57 DQ60 DQ62 VSS 1 2 DQ0 DQ2 DQ4 DQ5 LDM0 WE0\ RAS0\ VSS VSS CKE3 CLK3 UDM3 DQ58 DQ59 DQ61 DQ63 2 3 DQ14 DQ12 DQ10 DQ8 VCC VCC VCC VCC VCC VCC VCC VCC DQ55 DQ53 DQ51 DQ49 3 4 DQ15 DQ13 DQ11 DQ9 UDM0 CLK0 CKE0 VCCQ VCCQ CS3\ CAS3\ WE3\ DQ54 DQ52 DQ50 DQ48 4 5 VSS VSS VCC VCCQ 6 VSS VSS VCC VCCQ 7 A9 A0 A2 A12 8 A10 A7 A5 RFU BA0 9 A11 A6 A4 BA2 BA1 DNU VSSQ VSSQ VSSQ VSSQ 10 A8 A1 A3 RFU 11 VCCQ VCC VSS VSS 12 VCCQ VCC VSS VSS 13 DQ16 DQ18 DQ20 DQ22 LDM1 WE1\ CS1\ VSS VSS CKE2 CLK2 UDM2 DQ41 DQ43 DQ45 DQ47 13 14 DQ17 DQ19 DQ21 DQ23 VSS VSS VSS VSS VSS VSS VSS VSS DQ40 DQ42 DQ44 DQ46 14 15 DQ31 DQ29 DQ27 DQ26 NC UDM1 CLK1\ VCCQ VCCQ RAS2\ WE2\ LDM2 DQ37 DQ36 DQ34 DQ32 15 16 VSS DQ30 DQ28 DQ25 DQ24 CLK1 CKE1 VCC VCC CS2\ CAS2\ DQ39 DQ38 DQ35 DQ33 VCC 16 A B C D E F G H J K L M N P R T UDQS3 LDQS0 UDQS0 LDQS1 UDQS1 VrefDA UDQS1\ LDQS1\ VSSQ VSSQ VSSQ VSSQ RESET\ ZQ1 ZQ2 DNU RAS1\ CAS1\ VCC VCC CLK2\ LDQS3 UDQS3\ LDQS0\ UDQS0\ CLK0\ VSS VSS LDQS3\ ZQ0 VrefCA VSSQ VSSQ VSSQ VSSQ LDQS4\ NC NC NC NC NC 7 VSSQ VSSQ VSSQ VSSQ ZQ3 CLK4 NC NC NC NC 8 LDQS4 UDQS4\ RAS3\ LDM3 UDQS4 VSS VCC VCCQ 5 ODT CKE4 CLK4\ VSS VCC VCCQ 6 NC/ZQ4 LDQS2\ UDQS2\ LDQS2 CAS4\ DQ71 DQ69 DQ67 DQ65 9 WE4\ DQ70 DQ68 DQ66 DQ64 10 RAS4\ LDM4 VCC VSS VSS 11 CS4\ UDQS2 VCC VSS VSS 12 GND (Core) GND (I/O) Data IO A V+ (Core Power) V+ (I/O Power) CNTRL UNPOPULATED NC Address DNU Level REF L9D345G72BG5 ADVANCE INFORMATION LOGIC Devices Incorporated www.logicdevices.com 7 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A A DVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) TABLE 3 - BALL/SIGNAL LOCATION AND DESCRIPTION Ball Assignments B7, B10, C7, C10, C9, C8, B9, B8, A10, A7, A8, A9, D7 Symbol Type Description Input Address Inputs: Provide the ROW address for ACTIVATE commands, and the column A0, A1, A2, A3, A4, A5, A6, A7, address and auto precharge bit (A10) for READY/WRITE commands, to select one location A8, A9, A10 /AP, A11, out of the memory array in the respective bank. A10 sampled during a PRECHARGE comA12 /BC mand determines whether the PRECHARGE applies to one bank (A10 LOW), bank selected by BA[2:0] or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VrefCA. A12/BC#: when enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop, LOW = BC4 burst chop). BA0, BA1, BA2 Input Bank Address Inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MRE, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VrefCA. Input Future Address: A13, A14 Input Clock: CKx and CKx\ are differential clock inputs, one differential pair per WORD, five WORDs contained in the L9D3xxG72 product. All control and address input signals are sampled on the crossing of the positive edge of CKx and the negative edge of CKx\. Output data strobes (UDQSx/UDQSx\ and LDQSx/LDQSx\) is referenced to the crossing of CKx and CKx\. Input Clock Enable: CKE enables and disables internal circuitry and clocks on the SDRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CKx, CKx\, CKE, RESET#, and ODT) are disabled during SELF REFRESH. CKE is referenced to VrefCA. Input Chip Select: CS\ enables (registered LOW) and disables the command decoder. All commands are masked when CS\ is registered HIGH. CS\ provides for external rank selection on systems with multiple ranks. CS\ is considered part of the command code. CS\ is referenced to VrefCA. E8, E9, D9 D10, D8 F4, G5, F16, G15, L13, K12, L2, K1, M8, N6 G4, G16, K13, K2, M6 RFU CLK0, CLK0\, CLK1, CLK1\, CLK2, CLK2\, CLK3, CLK3\, CLK4, CLK4\ CKE0, CKE1, CKE2, CKE3, CKE4 G1, G13, K16, K4, M12 CS0\, CS1\, CS2\, CS3\, CS4\ E2, E4, E13, F15, M15, M13, M5, M2, N11 G2, F12, K15, L5, M11 F1, G12, L16, L4, M9 F2, F13, L15, M4, M10 LDMx, UDMx, LDMx, UDMx, LDMx, UDMx, LDMx, UDMx LDMx Input Input Data Mask: LDMx is the Lower-byte of a WORD, UDMx is the Upperbyte of a WORD, the L9D3xxG72 contains five WORDS. The data mask input, masks WRITE data. Lower byte data masked when LDMx is sampled HIGH, upper byte data masked when UDMx is sampled HIGH. The UDMx and LDMx pins are structured as inputs only, the pins electrical loading is designed to match that of the DQ and LDQSx, LDQSx\, UDQSx, and UDQSx\ pins. RAS0\, RAS1\, RAS2\, Input ROW Address Strobe/Select: Defines the command being entered along CAS\, WE\, and RAS3\, RAS4\ CS\. This input pin is referenced to VrefCA. CAS0\, CAS1\, CAS2\, Input COLUMN Address Strobe/Select: Defines the command being entered along with RAS\, CAS3\, CAS4\ WE\, and CS\. This input pin is referenced to VrefCA. WE0\, WE1\, WE2\, Input WRITE Enable Input: Defines the command being entered along with CAS\, RAS\,, and CS\. WE3\, WE4\ This input pin is referenced to VrefCA. LOGIC Devices Incorporated www.logicdevices.com 8 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) TABLE 3 - BALL/SIGNAL LOCATION AND DESCRIPTION CONTINUED Ball Assignments L6 Symbol ODT Type Description Input On-Die Termination: ODT enables (when registered HIGH) and disables termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following signals: DQ[63:0], LDQSx, LDQSx\, UDQSx, UDQSx\, UDMx and LDMx. The ODT input is ignored if disabled via the LOAD MODE register command. ODT is referenced to VrefCA. Input RESET: An input control pin, active LOW referenced to Vss. The RESET\ input receiver is a CMOS input defined as a rail to rail signal with DC HIGH ≥ 0.8 x Vcc and DC LOW ≤ 0.2 x VccQ. RESET\ assertion and de-assertion are asynchronous. Input Data Strobe, LOW Byte (per WORD): Output, edge-aligned with READ data. Input, centeraligned with WRITE data. Input Data Strobe, HIGH Byte (per WORD): Output, edge-aligned with READ data. Input, centeraligned with WRITE data. I/O Data Input/Output: LOW Byte, LOW WORD (WORD 1). Pin referenced to VrefDQ. G11 RESET\ E6, E10, L12, F5, K5, F7, F11, L10, G6, L7 E7, E11, N12, E5, N5, F8, F10, L11, F6, K6 A2, B1, B2, C1, C2, D2, D1, E1 D3, D4, C3, C4, B3, B4, A3, A4 A13, A14, B13, B14, C13, C14, D13, D14 E16, D16, D15, C15, C16, B15, B16, A15 T15, R16, R15, P16, P15, N15, N16, M16 N14, N13, P14, P13, R14, R13, T14, T13 T4, T3, R4, R3, P4, P3, N4, N3 LDQSx, LDQSx\ UDQSx, UDQSx\ DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7 DQ8, DQ9, DQ10, I/O DQ11, DQ12, DQ13, DQ14, DQ15 DQ16, DQ17, DQ18, I/O DQ19, DQ20, DQ21, DQ22, DQ23 DQ24, DQ25, DQ26, I/O DQ27, DQ28, DQ29, DQ30, DQ31 DQ32, DQ33, DQ34, I/O DQ35, DQ36, DQ37, DQ38, DQ39 DQ40, DQ41, DQ42, I/O DQ43, DQ44, DQ45, DQ46, DQ47 DQ48, DQ49, DQ50, I/O DQ51, DQ52, DQ53, DQ54, DQ55 Data Input/Output: HIGH Byte, LOW WORD (WORD 1). Pin referenced to VrefDQ. Data Input/Output: LOW Byte, WORD 2. Pin referenced to VrefDQ. Data Input/Output: HIGH Byte, WORD 2. Pin referenced to VrefDQ. Data Input/Output: LOW Byte, WORD 3. Pin referenced to VrefDQ. Data Input/Output: HIGH Byte, WORD 3. Pin referenced to VrefDQ. Data Input/Output: LOW Byte, HIGH WORD (WORD 4). Pin referenced to VrefDQ. LOGIC Devices Incorporated www.logicdevices.com 9 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) TABLE 3 - BALL/SIGNAL LOCATION AND DESCRIPTION CONTINUED Ball Assignments M1, N1, N2, P2, P1, R2, R1, T2 T10, T9, R10, R9, P10, P9, N10, N9 B11, B12, C5, C6, E3, F3, G3, H3, H12, H16, J3, J12, J16, K3, L3, M3, P11, P12, R5, R6, T16 A11, A12, D5, D6, H4, H15, J4, J15, T5, T6 A5, A6, A16, B5, B6, C11, C12, D11, D12, E14, F14, G14, H1, H2, H5, H13, H14, J1, J2, J5, J13, J14, K14, L14, M14, P5, P6, R11, R12, T1, T11, T12 G7, G8, G9, G10, H7, H8, H9, H10, J7, J8, J9, J10, K7, K8, K9, K10 J6 E12 H6, H11, J11, L8, L9 A1 E15, L1 Symbol DQ56, DQ57, DQ58, DQ59, DQ60, DQ61, DQ62, DQ63 DQ64, DQ65, DQ66, DQ67, DQ68, DQ69, DQ70, DQ71 Vcc Type I/O Description Data Input/Output: HIGH Byte, HIGH WORD (WORD 4). Pin referenced to VrefDQ. I/O Data Input/Output: HIGH Byte, HIGH WORD (WORD 5). Pin referenced to VrefDQ. Supply Power Supply: 1.5V ± 0.075V VccQ Supply Data I/O Supply: 1.5V ± 0.075V Vss Supply Ground VssQ Supply Data I/O Ground: Isolated from Core for improved noise immunity VrefCA VrefDQ ZQx Supply Voltage Reference CORE: VrefCA must be maintained at all times Supply Voltage Reference I/O: VrefDQ must be maintained at all times. REF External Reference for output drive calibration Unpopulated, un-plated matrix location(s) No Connect: These ball locations have no electrical connection internally. Locations other than those indicating an upgrade or alternative function should be left isolated (non-connected) UNPOPULATED NC LOGIC Devices Incorporated www.logicdevices.com 10 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) FIGURE 5 - MECHANICAL DRAWING 24.90 25.10 2.00 MAX 0.61 NOM A B C D E F G H J K L M N P R T 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1.27 NOM 19.05 NOM 1.27 NOM 24.90 25.10 0.50 MAX 255 x 0.762 NOM 1.27 NOM Note: All dimensions in mm LOGIC Devices Incorporated www.logicdevices.com 11 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) TABLE 5: ABSOLUTE MAXIMUM RATINGS Symbol Vcc VccQ VIN, VOUT TcIndustrial TcExtended TcMiltemp TSTG NOTES: 1. Vcc and VccQ must be within 300mV of each other at all times and VREF must not be greater than 0.6 x VccQ. When Vcc and VccQ are less than 500MV, VREF may be ≤300mV. 2. Max operating case temperature. Tc is measured in the center of the package. 3. Device Functionality is not guaranteed if the DRAM device exceeds the Maximum Tc during operation. Parameter Vcc Supply Voltage relative to Vss Vcc Supply Voltage relative to VssQ Voltage on any pin relative to Vss Operating Case Temperature Operating Case Temperature Operating Case Temperature Storage Temperature MIN -0.4 -0.4 -0.4 0 -40 -55 -55 MAX 1.975 1.975 1.975 85 105 125 120 UNITS V V V °C °C °C °C NOTES 1 1 1 2,3 2,3 2,3 2,3 TABLE 6: INPUT/OUTPUT CAPACITANCE Capacitance Parameter CK and CK\ ∆C: CK to CK\ Single-end I/O: DQ, DM Differential I/O: DQS, DQS\ ∆C: DQS to DQS\ ∆C: DQ to DQS ∆C: CNTL to CK ∆C: cmd_ADDR to CK Inputs (RAS\, CAS\, WE\, CS\, CKE, ADDR) NOTES: PACKAGE OUTLINE DIMENSIONS DDR3-800 Symbol CCK CDCK C10 C10 CCCQS CDI0 CDI_CNTL CDI_CMD_ADDR CI_Shared DDR3-1066 MIN 3.1 0 1.5 1.5 0 -0.5 -0.5 -0.5 2.9 DDR3-1333 MIN 3.0 0 1.5 1.5 0 -0.5 -0.5 -0.5 2.9 MIN 3.1 0 1.5 1.5 0 -0.5 -0.5 -0.5 2.9 MAX 6.2 0.2 3.0 3.0 0.2 0.3 0.3 0.3 5.5 MAX 6.2 0.2 3.0 3.0 0.2 0.3 0.3 0.3 5.3 MAX UNITS NOTES 6.1 0.2 2.5 2.5 0.2 0.3 0.3 0.3 5.1 pF pF pF pF pF pF pF pF pF 2 3 3 4 6 7 5 1. Vcc = +1.5V± 0.075mV, VccQ = Vcc, VREF = Vss, f= 100MHz, Tc = 25°C, VOUT (DC) = 0.5 x VccQ, VOUT (peak to peak) = 0.1V 2. DM input is grouped with I/O pins, reflecting the signal is grouped with DQ and therefore matched in loading. 3. CCCQS is for DQS vs. DQS\ 4. CDIO = CIO (DQ) - 0.5 x (CIO [DQS] + CIO [DQS\]) 5. Excludes CK, CK\ 6. CDI_CNTL = CI(CNTL) - 0.5 x (CCK[CK] + CCK [CK\]); CNTL = ODT, CS\ and CKE 7. CDI_CMD_ADDR = CI (CMD_ADDR) - 0.5 x (CCK [CK] + CCK [CK\]); CMD = RAS\, CAS\, and WE\ ADDR = [n:0] LOGIC Devices Incorporated www.logicdevices.com 12 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) TABLE 8: TIMING PARAMETERS FOR ICC MEASUREMENTS - CLOCK UNITS DDR3-800 -25 ICC Parameter tCK DDR3-1066 -19 8-8-8 1.875 8 8 28 20 8 27 6 59 DDR3-1333 -15 10-10-10 1.5 10 10 34 24 10 30 5 74 6-6-6 2.5 6 6 21 15 6 x72 x72 20 4 44 UNITS ns CK CK CK CK CK CK CK CK (MIN) ICC CL ICC tRCD (MIN) ICC tRC (MIN) ICC tRAS (MIN) ICC tRP (MIN) ICC tFAW tRRD ICC tRFC 64M x 16 (4.5X) LOGIC Devices Incorporated www.logicdevices.com 13 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) High Performance, Integrated Memory Module Product A [15:11] BA [2:0] A [9:7] A [10] RAS\ CAS\ ODT WE\ ADVANCE INFORMATION Sub-Loop CK, CK\ Command Cycle Number A [6:3] A [2:0] CKE CS\ 0 TABLE 9: ICC0 MEASUREMENT LOOP LOGIC Devices Incorporated www.logicdevices.com 1 2 3 4 5 6 7 0 1 2 3 4 n RAS n RC n RC + 1 n RC + 2 n RC + 3 n RC + 4 n RC + n RAS 2 x nRC 4 x n RC 6 x n RC 8 x n RC 10 x n RC 12 x n RC 14 x n RC ACT D D D\ D\ 0 1 1 1 1 0 0 1 1 1 1 PRE 0 PRE ACT D D D\ D\ 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 Repeat cycles 1 through 4 until n RAS - 1, truncate if needed 0 1 0 0 0 0 0 0 0 Repeat cycles 1 through 4 until n RC - 1, truncate if needed 0 1 1 0 0 0 0 0 F 0 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 0 F 1 1 1 0 0 0 0 0 F 1 1 1 0 0 0 0 0 F Repeat cycles n RC +1 through n RC +4 until n RC - 1 + n RAS - 1, truncate if needed 0 1 0 0 0 0 0 0 F Repeat cycles n RC +1 through n RC +4 until 2 x RC - 1, truncate if needed Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 0 0 0 0 0 0 Static HIGH Toggling 0 0 0 0 0 Data - - - 0 - 14 Jul 06, 2009 LDS-L9D345G72BG5-A L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) High Performance, Integrated Memory Module Product A [15:11] BA [2:0] A [9:7] A [10] RAS\ CAS\ ODT WE\ 0 0 0 1 1 1 0 0 0 0 1 1 1 0 ADVANCE INFORMATION Sub-Loop CK, CK\ Command Cycle Number A [6:3] A [2:0] CKE 0 0 1 2 3 4 n RCD n RAS n RC n RC +1 nRC +2 n RC +3 n RC +4 n RC + nRCD n RC + nRAS ACT D D D\ D\ 0 1 1 1 1 0 0 0 1 1 1 1 RD PRE 2 x n RC 2 x n RC 2 x n RC 2 x n RC 2 x n RC 2 x n RC 2 x n RC 0 0 RD PRE ACT D D D\ D\ CS\ TABLE 10: ICC1 MEASUREMENT LOOP LOGIC Devices Incorporated www.logicdevices.com 1 2 3 4 5 6 7 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 Repeat cycles 1 through 4 until nRCD - 1, truncate if needed 0 1 0 0 0 0 0 0 Repeat cycles 1 through 4 until nRAS - 1, truncate if needed 1 0 0 0 0 0 0 0 Repeat cycles 1 through 4 until nRC - 1, truncate if needed 1 1 0 0 0 0 0 F 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 F 1 1 0 0 0 0 0 F 1 1 0 0 0 0 0 F Repeat cycles nRC + 1 through nRC + 4 until nRC + nRCD - 1, truncate if needed 0 1 0 0 0 0 0 F Repeat cycles nRC + 1 through nRC + 4 until nRC + nRAS - 1, truncate if needed 1 0 0 0 0 0 0 F Repeat cycle nRC + 1 through nRC + 4 until 2 x nRC - 1, truncate if needed Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 0 0 0 0 0 0 00000000 0 Static HIGH Toggling 0 0 0 0 0 Data - - - 0 00110011 0 - 15 Jul 06, 2009 LDS-L9D345G72BG5-A L 9D345G72BG5 ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) TABLE 11: ICC MEASUREMENT CONDITIONS FOR POWER-DOWN CURRENTS Icc2P0 Icc2P1 Icc2Q Precharge Power- Precharge PowerPrecharge Quiet Down Current Down Current Standby Current (Slow Exit) (Fast Exit) n/a LOW Toggling tCK (MIN) ICC n\a n\a n\a n\a n\a n\a n\a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, OFF 8 None All n\a n/a LOW Toggling tCK (MIN) ICC n\a n\a n\a n\a n\a n\a n\a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, OFF 8 None All n\a n/a HIGH Toggling tCK (MIN) ICC n\a n\a n\a n\a n\a n\a n\a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, OFF 8 None All n\a Name Timing Pattern CKE External Clock tCK tRC tRAS tRCD tRRD tRC CL AL CS\ Command Inputs ROW/COLUMN Addr Bank Address DM Data I/O Output Buffer DQ, DQS ODT Burst Length ACTIVE Bank(s) IDLE Bank(s) Special Notes Icc3P Active PowerDown Current n/a LOW Toggling tCK (MIN) ICC n\a n\a n\a n\a n\a n\a n\a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, OFF 8 None All n\a LOGIC Devices Incorporated www.logicdevices.com 16 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) TABLE 12: ICC2N / ICC3N MEASUREMENT LOOP Toggling Static HIGH 0 D D D\ D\ 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 0 0 0 0 0 0 F F 0 0 0 0 1 2 3 4 5 6 7 CK, CK\ CKE Sub-Loop 0 1 2 3 4-7 8-11 12-15 16-19 20-23 24-27 28-31 Cycle Number Command CS\ RAS\ CAS\ WE\ ODT BA [2:0] A [15:11] A [10] A [9:7] A [6:3] A [2:0] Data LOGIC Devices Incorporated www.logicdevices.com 17 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) High Performance, Integrated Memory Module Product A [15:11] BA [2:0] A [9:7] A [10] RAS\ CAS\ ODT WE\ 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Repeat sub-loop 0, use BA [2:0] = 1; ODT = 0 Repeat sub-loop 0, use BA [2:0] = 2; ODT = 1 Repeat sub-loop 0, use BA [2:0] = 3; ODT = 1 Repeat sub-loop 0, use BA [2:0] = 4; ODT = 0 Repeat sub-loop 0, use BA [2:0] = 5; ODT = 0 Repeat sub-loop 0, use BA [2:0] = 6; ODT = 1 Repeat sub-loop 0, use BA [2:0] = 7; ODT = 1 0 0 0 0 ADVANCE INFORMATION Sub-Loop Command CK, CK\ Cycle Number A [6:3] A [2:0] CKE 0 1 2 3 4 5 6 7 0 1 2 3 4-7 8-11 12-15 16-19 20-23 24-27 28-31 Static HIGH Toggling TABLE 13: ICC2NT MEASUREMENT LOOP LOGIC Devices Incorporated www.logicdevices.com 18 D D D\ D\ CS\ 1 1 1 1 0 0 F F 0 0 0 0 Data - Jul 06, 2009 LDS-L9D345G72BG5-A L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) High Performance, Integrated Memory Module Product A [15:11] BA [2:0] A [9:7] A [10] RAS\ CAS\ ODT WE\ 1 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 0 0 0 0 0 0 0 0 ADVANCE INFORMATION Sub-Loop CK, CK\ Command Cycle Number A [6:3] A [2:0] CKE 0 TABLE 14: ICC4R MEASUREMENT LOOP 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 RD D D\ D\ RD D D\ D\ CS\ Static HIGH Toggling 0 1 1 1 0 1 1 1 0 0 0 0 F F F F 0 0 0 0 0 0 0 0 00000000 00110011 - Data LOGIC Devices Incorporated www.logicdevices.com 19 Jul 06, 2009 LDS-L9D345G72BG5-A L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) High Performance, Integrated Memory Module Product A [15:11] BA [2:0] A [9:7] A [10] RAS\ CAS\ WE\ ODT 1 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADVANCE INFORMATION Sub-Loop CK, CK\ Command Cycle Number A [6:3] A [2:0] CKE Sta c HIGH Toggling TABLE 15: ICC4W MEASUREMENT LOOP 1 2 3 4 5 6 7 LOGIC Devices Incorporated www.logicdevices.com 20 0 0 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 WR D D\ D\ WR D D\ D\ CS\ 0 1 1 1 0 1 1 1 0 0 0 0 F F F F 0 0 0 0 0 0 0 0 00000000 00110011 - Data Jul 06, 2009 LDS-L9D345G72BG5-A L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) High Performance, Integrated Memory Module Product A [15:11] BA [2:0] A [9:7] A [10] RAS\ CAS\ ODT WE\ Repeat sub-loop 1a, use BA [2:0] = 1 Repeat sub-loop 1a, use BA [2:0] = 2 Repeat sub-loop 1a, use BA [2:0] = 3 Repeat sub-loop 1a, use BA [2:0] = 4 Repeat sub-loop 1a, use BA [2:0] = 5 Repeat sub-loop 1a, use BA [2:0] = 6 Repeat sub-loop 1a, use BA [2:0] = 7 Repeat sub-loop 1a through 1h until n RFC - 1, truncate if needed ADVANCE INFORMATION Sub-Loop CK, CK\ Command Cycle Number A [6:3] A [2:0] CKE 0 1a 1b 1c 1d 1e 1f 1g 1h 2 0 1 2 3 4 5-8 9-12 13-16 17-20 21-24 25-28 29-32 33-n RFC-1 TABLE 16: ICC5B MEASUREMENT LOOP Static HIGH Toggling REF D D D\ D\ CS\ Data LOGIC Devices Incorporated www.logicdevices.com 21 Jul 06, 2009 LDS-L9D345G72BG5-A L 9D345G72BG5 ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) TABLE 17: ICC MEASUREMENT LOOP Industrial Range Tc =-40°C to 85°C PACKAGE OUTLINE DIMENSIONS Extended or Mil Temperature Range, Tc = -40°C to 85°C or -55°C to 125°C ICC Test CKE External Clock tCK tRC tRAS tRCD tRRD Icc6: Self Refresh Current LOW Off, CK and CK\ = LOW n\a n\a n\a n\a n\a n\a n\a n\a Mid-level Mid-level Mid-level Mid-level Mid-level Enabled Enabled, Mid-level n\a n\a n\a Disabled (normal) Disabled Icc6E/M: Self Refresh Current LOW Off, CK and CK\ = LOW n\a n\a n\a n\a n\a n\a n\a n\a Mid-level Mid-level Mid-level Mid-level Mid-level Enabled Enabled, Mid-level n\a n\a n\a Enabled (extended) Disabled Icc8: Reset Mid-level Mid-level n\a n\a n\a n\a n\a n\a n\a n\a Mid-level Mid-level Mid-level Mid-level Mid-level Mid-level Mid-level n\a None All n\a n\a tRC CL AL CS\ Command Inputs ROW/COLMUN addresses BANK addresses Data I/O Output buffer DQ, DQS ODT Burst Length Active BANKS IDLE BANKS SRT ASR LOGIC Devices Incorporated www.logicdevices.com 22 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) High Performance, Integrated Memory Module Product A [15:11] BA [2:0] A [9:7] A [10] RAS\ CAS\ ODT WE\ CS\ 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 Repeat cycle 2 until n RRD - 1 1 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 Repeat cycle n RRD + 2 until 2 x n RRD - 1 Repeat sub-loop 0, use BA[2:0] = 2 Repeat sub-loop 0, use BA[2:0] = 3 0 0 0 3 0 0 0 Repeat cycle 4 x n RRD until n FAW - 1, if needed Repeat sub-loop 0, use BA[2:0] = 4 Repeat sub-loop 1, use BA[2:0] = 5 Repeat sub-loop 0, use BA[2:0] = 6 Repeat sub-loop 1, use BA[2:0] = 7 0 0 0 7 0 0 0 Repeat cycle n FAW + 4 x n RRD until 2 x n FAW - 1, if needed 1 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 Repeat cycle 2 x n FAW + 2 until 2 x n FAW + n RRD - 1 1 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 Repeat cycle 2 x n FAW + n RRD + 2 until 2 x n FAW + 2 x n RRD - 1 Repeat sub-loop 10, use BA[2:0] = 2 Repeat sub-loop 11, use BA[2:0] = 3 0 0 0 3 0 0 0 Repeat cycle 2 x n FAW + 4 x n RRD until 3 x n FAW - 1, if needed Repeat sub-loop 10, use BA[2:0] = 4 Repeat sub-loop 11, use BA[2:0] = 5 Repeat sub-loop 10, use BA[2:0] = 6 Repeat sub-loop 11, use BA[2:0] = 7 0 0 0 7 0 0 0 Repeat cycle 3 x n FAW + 4 x n RRD until 4 x n FAW - 1, if needed ADVANCE INFORMATION Sub-Loop CK, CK\ Command Cycle Number A [6:3] A [2:0] CKE 0 ACT RDA D 1 2 3 4 5 6 7 8 9 D ACT RDA D ACT RDA D D 10 11 12 13 14 15 16 17 18 19 TABLE 18: ICC7 MEASUREMENT LOOP 0 1 2 3 n RRD n RRD + 1 n RRD + 2 n RRD + 3 2 x n RRD 3x n RRD 4 x n RRD 4 x n RRD + 1 n FAW n FAW + n RRD n FAW + 2xn RRD n FAW + 3xn RRD n FAW + 4xn RRD n FAW + 4xn RRD+1 2 x n FAW 2 x n FAW + 1 2 x n FAW + 2 2 x n FAW + 3 2 x n FAW + n RRD 2 x n FAW + n RRD+1 2 x n FAW + n RRD+2 2 x n FAW + n RRD+3 2 x nFAW + 2x n RRD 2 x n FAW + 3x n RRD 2 x n FAW + 4x n RRD 2 x n FAW+4x n RRD+1 3 x nFAW 3 x nFAW + nRRD 3 x nFAW + 2x nRRD 3 x nFAW + 3x nRRD 3 x nFAW + 4x nRRD 3 x nFAW + 4x nRRD +1 ACT RDA D 0 0 0 0 0 0 00000000 - F F F 0 0 0 00110011 - F 0 Data - Static HIGH Toggling F 0 - F F F 0 0 0 00110011 - 0 0 0 0 0 0 00000000 - D 0 0 - D 0 0 LOGIC Devices Incorporated www.logicdevices.com 23 Jul 06, 2009 LDS-L9D345G72BG5-A L 9D345G72BG5 ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) TABLE 19: ICC MAXIMUM LIMITS Speed Bin ICC Icc0 IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP DDR3-800 437 456 475 544 578 603 59 76 220 148 191 220 230 299 343 244 316 362 393 506 581 148 154 163 245 250 269 1128 1150 1175 1176 1200 1125 980 1000 1020 30 54 95 1700 1844 1988 ICC2P + 2mA ICC2P + 2.1mA ICC2P + 2.4mA 3. DDR3-1066 488 508 637 663 59 76 171 223 265 344 268 349 465 605 173 181 268 273 1275 1300 1421 1450 1077 1100 30 54 1860 2000 ICC2P + 2mA ICC2P + 2.1mA DDR3-1333 544 UNITS mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Notes 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 Icc1 731 Icc2P0 59 Icc2P1 196 Icc2Q 300 Icc2N 318 Icc2NT 515 Icc3P 196 Icc3N 294 Icc4R 1421 Icc4W 1740 Icc5B 1176 Icc6 30 Icc7 2055 Icc8 ICC2P + 2mA NOTES: 1. 2. Tc = 0°C to ≤ 85°C; SRT and ASR are disabled, enabling ASR could increase ICCx by up to an additional 2mA. Tc = -40°C to ≤ 105°C; SRT and ASR are disabled, enabling ASR could increase ICCx by up to an additional 2mA. Tc = -55°C to ≤ 125°C; SRT and ASR are disabled, enabling ASR could increase ICCx by up to an additional 2mA. LOGIC Devices Incorporated www.logicdevices.com 24 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) TABLE 20: DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS PACKAGE OUTLINE DIMENSIONS All Voltages are referenced to Vss Parameter/Condition Supply Voltage I/O Supply Voltage Input Leakage Current: Any input 0V≤VIN≤Vcc, VREF pin 0V≤VIN≤1.1V All other pins not under test = 0V VREF Supply Leakage Current: VREFDQ = Vcc/2 or VREFCA = Vcc/2 All other pins not under test = 0V NOTES: 1. Symbol Vcc VccQ II MIN 1.425 1.425 -2 TYP 1.5 1.5 - MAX 1.575 1.575 2 UNITS V V μA NOTES 1,2 1,2 IVREF -1 - 1 μA 3,4 Vcc and VccQ must track one another, VccQ must be less than or equal to Vcc, Vss = VssQ. 3. 4. VREF (see Table 22). The minimum limit requirement is for testing purposes. The leakage current on the VREF pin should be minimal. 2. Vcc and VccQ may include AC noise of ± 50mV (250 kHz to 20MHz) in addition to the DC (0Hz to 250kHz) specifications, Vcc and VccQ must be at the same level for valid AC timing parameters. TABLE 21: DC ELECTRICAL CHARACTERISTICS AND INPUT CONDITIONS OUTLINE DIMENSIONS PACKAGE All Voltages are referenced to Vss Parameter/Condition VIN low; DC/commands/address busses VIN high; DC/commands/address busses Input reference voltage command/address bus I/O reference voltage DQ bus I/O reference voltage DQ bus in SELF REFRESH Command/address termination voltage (system level, not direct DRAM input) NOTES: 1. Symbol VIL VIH VREFCA(DC) VREFDQ(DC) VREFDQ(SR) VTT MIN Vss See Table 20 TYP n/a n/a 0.5 x Vcc 0.5 x Vcc 0.5 x Vcc 0.5 x VccQ MAX See Table 20 UNITS V V V V V V NOTES Vcc 0.51 x Vcc 0.51 x Vcc Vcc - 0.49 x Vcc 0.49 x Vcc Vss - 1,2 2,3 4 5 VREFCA(DC) is expected to be approximately 0.5 x Vcc and to track variations in the DC level. Externally generated peak noise (noncommon mode) on VREFCA may not exceed ± 1% x Vcc around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not exceed ± 2% of VREFCA(DC). 4. mon mode) on VREFDQ may not exceed ± 1% x Vcc around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not exceed ± 2% of VREFDQ(DC). VREFDQ(DC) may transition to VREFDQ(SR) and back to VREFDQ(DC) when in SELF zREFRESH, within restrictions outlined in the SELF REFRESH section. 5. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors. MIN and MAX values are system-dependent. 2. DC values are determined to be less than 20MHz in frequency. DRAM must meet specifications if the DRAM induces additional AC noise greater than 20MHz in frequency. 3. VREFDQ(DC) is expected to be approximately 0.5 x Vcc and to track variations in the DC level. Externally generated peak noise (noncom- LOGIC Devices Incorporated www.logicdevices.com 25 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) TABLE 22: INPUT SWITCHING CONDITIONS Parameter/Condition Command and Address Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input high DC voltage: Logic 1 Input high DC voltage: Logic 0 Input high AC voltage: Logic 0 Input high AC voltage: Logic 0 VIH (AC175) MIN VIH (AC150) MIN VIH (DC100) MIN VIL (DC100) MAX VIL (AC150) MAX VIL (AC175) MAX +175 +150 +100 -100 -150 -175 +175 +150 +100 -100 -150 -175 mV mV mV mV mV mV PACKAGE OUTLINE DIMENSIONS Symbol DDR3-1066 DDR3-900 DDR1333 UNITS DQ and DM Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input high DC voltage: Logic 1 Input high DC voltage: Logic 0 Input high AC voltage: Logic 0 Input high AC voltage: Logic 0 NOTES: 1. All voltages are referenced to VREF, VREF is VREFCA for control, command, and address. All slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ and DM inputs. 4. 2. Input setup timing parameters (tIS and tDS) are referenced at VIL(AC)/ VIH(AC), not VREF(DC). Single-ended input slew rate = 1V/ns; maximum input voltage swing under test is 900mV (peak-to-peak). 3. Input hold timing parameters (tIH and tDH) are referenced at VIL(DC)/ VIH(DC), not VREF(AC). VIH (AC175) MIN VIH (AC150) MIN VIH (DC100) MIN VIL (DC100) MAX VIL (AC150) MAX VIL (AC175) MAX +175 +150 +100 -100 -150 -175 +150 +100 -100 -150 mV mV mV mV mV mV LOGIC Devices Incorporated www.logicdevices.com 26 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) OPERATING CONDITIONS FIGURE 6 - INPUT SIGNAL VIL and VIH levels with ringback 1.90V VDDQ + 0.4V narrow pulse width 1.50V Minimum VIL and VIH levels VIH (AC) 0.925V VDDQ 0.925V VIH (AC) VIH (DC) 0.850V 0.850V VIH (DC) 0.780V 0.765V 0.750V 0.735V 0.720V 0.780V 0.765V 0.750V 0.735V 0.720V VREF + AC noise VREF + DC error VREF + DC error VREF + AC noise 0.650V VIL (DC) 0.650V VIL (DQ) 0.575V VIL (AC) 0.575V VIL (AC) 0.0V VSS -0.40V VSS 0.4V narrow pulse width Notes: 1. Numbers in diagrams reflect nominal values. LOGIC Devices Incorporated www.logicdevices.com 27 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) AC OVERSHOOT/UNDERSHOOT SPECIFICATION TABLE 23: CONTROL AND ADDRESS PINS Parameter Maximum peak amplitude allowed for overshoot area (see Figure 16 on page 38) Maximum peak amplitude allowed for overshoot area (see Figure 17 on page 39) Maximum overshoot area above Vcc (see Figure 16 on page 38) Maximum undershoot area below Vss (see Figure 17 on page 39) 0.67Vns 0.67Vns 0.5Vns 0.5Vns 0.4Vns 0.4Vns 0.4V 0.4V 0.4V PACKAGE OUTLINE DIMENSIONS DDR3-800 0.4V DDR3-1066 0.4V DDR3-1333 0.4V TABLE 24: CLOCK, DATA, STROBE, AND MASK PINS Parameter Maximum peak amplitude allowed for overshoot area (see Figure 16 on page 38) Maximum peak amplitude allowed for overshoot area (see Figure 17 on page 39) Maximum overshoot area above Vcc/ VccQ (see Figure 16 on page 38) Maximum undershoot area below Vss/ VssQ (see Figure 17 on page 39) PACKAGE OUTLINE DIMENSIONS DDR3-800 0.4V DDR3-1066 0.4V DDR3-1333 0.4V 0.4V 0.4V 0.4V 0.25Vns 0.19Vns 0.15Vns 0.25Vns 0.19Vns 0.15Vns FIGURE 7 & 8: OVERSHOOT/UNDERSHOOT SPECIFICATIONS Volts (V) Maximum amplitude Overshoot area Figure 7: Overshoot VCC/VCCQ Time (ns) Time (ns) Figure 8: Undershoot VSS/VSSQ Volts (V) Maximum amplitude Undershoot area LOGIC Devices Incorporated www.logicdevices.com 28 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) TABLE 25: DIFFERENTIAL INPUT OPERATING CONDITIONS (CKXPACKAGE OUTLINEND IMENSIONS , CKX\, DQSX, A D DQSX\) Parameter/Condition Differential input voltage, logic high - slew Differential input voltage, logic low - slew Differential input voltage, logic high Differential input voltage, logic low Differential input crossing voltage relative to Vcc/2 for DQS, DQS\, CK, CK\ Differential input crossing voltage relative to Vcc/2 for CK, CK\ Single-ended high level for strobes Single-ended high level for CK, CK\ Single-ended low level for strobes Single-ended low level for CK, CK\ NOTES: 1. Clock is referenced to VccD and Vss. Data strobe is referenced to VccQ and VssQ. 2. 3. 4. 5. Reference is VREFCA(DC) for clock and for VREFDQ(DC) for strobe. Differential input slew rate = 2V/ms. Defines slew rate reference points relative to input crossing voltages. 8. MAX limit is relative to single-ended signals, the overshoot specifications are applicable. The VIX extended range (±175mV) is allowed only for the clock and this VIX extended range is only allowed when the following conditions are met: The single-ended input signals are monotonic, have the singleended swing VSEL, VSEH of at least Vcc/2 ±250mV, and the differential slew rate of CK, CK\ is greater than 3V/ns. 7. 6. MIN limit is relative to single-ended signals, the undershoot specifications are applicable. The typical value of VIX(AC) is expected to be about 0.5 x Vcc of the transmitting device and VIX(AC) is expected to track variations in Vcc. VIX(AC) indicates the voltage at which differential input signals must cross. VSEL VSHE VccQ/2 + VIH(AC) Vcc/2 + VIH(AC VssQ Vss VccQ Vcc VccQ/2-VIL(AC) Vcc/2-VIL(AC) mV 6 mV 5 VIX(175) VREF(DC) - 175 VREF(DC) + 175 mV 7,8 Symbol VIH DIFF(AC)slew VIL DIFF(AC)slew VIH DIFF(AC) VIL DIFF(AC) VIX MIN +200 n/a 2x(VIH(AC)-VREF) Vss/VssQ VREF(DC) - 150 MAX n/a -200 Vcc/VccQ 2x(VREF-VIL(AC)) VREF(DC) + 150 UNITS mV mV mV mV mV NOTES 4 4 5 6 7 LOGIC Devices Incorporated www.logicdevices.com 29 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) OVERSHOOT/UNDERSHOOT SPECIFICATIONS FIGURE 9 - VIX FOR DIFFERENTIAL SIGNALS VCC, VCCQ CK#, DQS# X VIX VCC/2, VCCQ/2 X VCC/2, VCCQ/2 VIX X CK, DQS VSS, VSSQ VIX CK, DQS VSS, VSSQ VCC, VCCQ CK#, DQS# VIX X FIGURE 10 - SINGLE-ENDED REQUIREMENTS FOR DIFFERENTIAL SIGNALS V CC or VCC Q VSEH (MIN) V CC /2 or VCC Q/2 VSEH VSEL (MAX) CK or DQS VSEL VSS or VSS Q LOGIC Devices Incorporated www.logicdevices.com 30 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) OVERSHOOT/UNDERSHOOT SPECIFICATIONS FIGURE 11 - DEFINITION OF DIFFERENTIAL AC-SWING AND tDVAC t DVAC V IHDIFF ( A C) MIN V IHDIFF (MIN) V IHDIFF ( DC) MIN CK - CK# DQ S - DQS # 0.0 V ILDIFF ( DC) MAX V ILDIFF (MAX) V ILDIFF ( A C) MAX half cycle t DVAC TABLE 26: DIFFERENTIAL INPUT OPERATING CONDITIONS (tDVAC) FOR CKX, CKD\, DQSX, AND DQSX\ PACKAGE OUTLINE X IMENSIONS Below VIL (AC) tDVAC (ps) at [VIHDIFF(AC) to VILDiff(AC)] Slew Rate (V/ns) -4.0 4.0 3.0 2.0 1.9 1.6 1.4 1.2 1.0 105˚C ≤ 125˚C t REFI ms ms ms μs μs μs SELF REFRESH Timing t 36 36 36 36 36 36 XS t Exit SELF REFRESH TO commands not requiring a locked DLL EXIT SELF REFRESH TO commands requiring a locked DLL MINIMUM CKE LOW pulse width for SELF REFRESH entry to SELF REFRESH exit ming Valid clocks a er SELF REFRESH entry or POWER-DOWN entry Valid clocks before SELF REFRESH exit, POWER-DOWN exit, or RESET exit MIN = greater of 5CK or tRFC + 10ns; MAX = n/a XSDLL t CK MIN = tDLLK (MIN); MAX = n/a CKESR t CK MIN = tCKE (MIN) + CK; MAX = n/a CKSRE t 28 CK MIN = greater of 5CK or 10ns; MAX = n/a CKSRX CK MIN = greater of 5CK or 10ns; MAX = n/a CK LOGIC Devices Incorporated www.logicdevices.com 53 REFRESH-to-ACTIVATE or REFRESH command period ns Jul 06, 2009 LDS-L9D345G72BG5-A L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) High Performance, Integrated Memory Module Product t CPDED t PD t ADVANCE INFORMATION TABLE 50 (SHEET 5 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS Parameter CKE MIN pulse width Command pass disable delay POWER-DOWN entry to POWER-DOWN exit ming Begin POWER-DOWN period prior to CKE registered HIGH POWER-DOWN entry period: ODT e her synchronous or asynchronous POWER-DOWN exit period: ODT either synchronous or asynchronous ACTIVATE command to POWER-DOWN entry PRECHARGE/PRECHARGE ALL command to POWER-DOWN entry REFRESH command to POWER-DOWN entry MRS command to POWER-DOWN entry READ/READ with AUTO PRECHARGE commant to POWER-DOWN entry WRITE Command to POWERDOWN entry WRITE with AUTO PRECHARGE command to POWER-DOWN entry BL8 (OTF, MRS) BC4OTF BC4MRS BL8 (OTF, MRS) BC4OTF BC4MRS t t -25 (DDR3-800) -19 (DDR3-1066) -15 (DDR3-1333) [CWL=2.5; 6-6-6] [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] Symbol MIN MAX MIN MAX MIN MAX POWER-DOWN Timing Greater of 3CK or Greater of 3CK or Greater of 3CK or t CKE (MIN) 7.5ns 5.625ns 5.625ns MIN = 1; MAX = n/a MIN = tCKE (MIN); MAX = 60ms ANPD PDE PDX POWER-DOWN Entry MINIMUM Timing ACTPDEN t Units Notes CK CK CK WL - 1CK CK Greater of tANPD or tRFC - REFRESH command to CKE LOW me t CK ANPD + tXPDLL MIN = 1 PRPDEN t REFPDEN t MRSPDEN t CK CK MIN = 1 MIN = 1 MIN = tMOD (MIN) RDPDEN t t CK CK CK MIN = RL + 4 + 1 WRPDEN WRPDEN WRAPDEN t WRAPDEN POWER-DOWN Exit Timing t 37 CK MIN = WL + 4 + tWR/tCK (AVG) MIN = WL + 2 + tWR/tCK (AVG) MIN = WL + 4 + WR + 1 MIN = WL + 2 + WR + 1 CK CK CK CK MIN = Greater of 3CK or 7.5ns; MAX = n/a XP t DLL on, any valid command, or DLL off to commands not requiring DLL locked PRECHARGE POWER-DOWN with DLL off to command requiring DLL locked MIN = Greater of 3CK or 6ns; MAX = n/a CK XPDLL MIN = Greater of 10CK or 24ns; MAX = n/a CK 28 LOGIC Devices Incorporated www.logicdevices.com 54 Jul 06, 2009 LDS-L9D345G72BG5-A L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) High Performance, Integrated Memory Module Product -25 (DDR3-800) [CWL=2.5; 6-6-6] Symbol MIN MAX ODT Timing ODTL on ODTL off t t t ADVANCE INFORMATION TABLE 50 (SHEET 6 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS Parameter RTT synchronous TURN-ON delay RTT synchronous TURN-OFF delay RTT TURN-ON from ODTL ON reference RTT TURN-OFF from ODTL OFF reference Asynchronous RTT TURN-ON delay (POWER-DOWN with DLL OFF) Asynchronous RTT TURN-OFF delay (POWER-DOWN with DLL OFF) ODT HIGH me without WRITE command or with WRITE command and BC8 ODT HIGH me without WRITE command or with WRITE command and BC4 RTT_NOM-to=RTT_WR change skew RTT_WR-to-RTT_NOM change skew - BC4 RTT_WR-to-RTT_NOM change skew - BC8 RTT dynamic change skew First DQS, DQS\ RISING edge DQS; DQS\ delay WRITE Leveling SETUP from rising CK, CK\ crossing to rising DQS, DQS\ crossing WRITE Leveling HOLD from rising DQS, DQS\ crossing to rising CK, CK\ crossing WRITE Leveling output delay WRITE Leveling output error -19 (DDR3-1066) -15 (DDR3-1333) [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] MIN MAX MIN MAX Units Notes AON AOF AONPD t -400 0.3 400 0.7 -300 0.3 300 0.7 MIN = 2; MAX = 8.5 AOFPD ODTH8 ODTH4 Dynamic ODT Timing ODTLCNW ODTLCNW4 ODTLCNW8 t 0.3 ADC WRITE Leveling Timing 40 25 t WLMRD t WLDQSEN t -250 0.3 250 0.7 CK CK ps CK 38 40 23,38 39,40 ns MIN = 2; MAX = 8.5 MIN = 6; MAX = n/a MIN = 4; MAX = n/a WL - 2CK 4CK + ODTL OFF 6CK + ODTL OFF 0.3 0.7 0.7 WLS t 38 ns 40 CK 0.3 40 25 325 WLH t t WLO WLOE 0.7 325 0 0 9 2 245 245 0 0 9 2 40 25 195 195 0 0 CK CK CK CK 39 - CK CK - ps - ps 9 2 ns ns LOGIC Devices Incorporated www.logicdevices.com 55 CK Jul 06, 2009 LDS-L9D345G72BG5-A L 9D345G72BG5 ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) NOTES 1. 2. 3. 4. Parameters are applicable with 0˚C ≤ Tc ≤ +95˚C and Vcc/VccQ = + 1.5V ± 0.075V. All voltages are referenced to Vss. Output timings are only valid for RON34 output buffer selection. Unit tCK (AVG) represents the actual tCK (AVG) of the input clock under operation. Unit CK represents one clock cycle of the input clock, counting the actual clock edges. AC timing and ICC tests may use a VIL-to-VIH swing of up to 900mV I the test environment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the AC/DC trip points and CK, CK\ and DQS, DQS\ use their crossing points). The minimum slew rate for the input signals used to test the device is 1V/ns for single-ended inputs and 2V/ ns for differential inputs in the range between VIL (AC) and VIH (AC). All timings that use time-based values (ns, μs, ms) should use tCK (AVG) to determine the correct number of clocks (Table 50 uses CK or CK (AVG) interchangeably). In the case of non-interger results, all minimum limits are to be rounded up to the nearest whole integer. The use of STROBE or DQSDIFF refers to the DQS and DQS\ differential crossing point when DQS is the rising edge. The use of CLOCK or CK refers to the CK and CK\ differential crossing point when CK is the rising edge. This output load is used for all AC timing (except ODT reference timing) and slew rates. The actual test load may be different. The output signal voltage reference point is VccQ/2 for single-ended signals and the crossing point for differential signals. When operating in DLL disable mode, LOGIC Devices, Inc. (LDI) does not warrant compliance with normal mode timings or functionality. 24. 10. The clock’s tCK (AVG) is the average clock over any 200 consecutive clocks and tCK (AVG) MIN is the smallest clock rate allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20-60kHz with and additional 1% of tCK (AVG) as a long-term jitter component; however, the spread-spectrum may not use a clock rate below tCK (AVG) MIN. The clock’s tCH (AVG) and tCL (AVG) are the average half clock period over any 200 consecutive clocks and is the smallest clock half period allowed, with the exception of values specified and must of a random Gaussian distribution in nature. The period jitter (tJITPER) is the maximum deviation in the clock period from the average or nominal clock. It is allowed in either the positive or negative direction. tCH (ABS) is the absolute instantaneous clock high pulse width as measured from one rising edge to the following falling edge. tCL (ABS) is the absolute instantaneous clock low pulse width as measured from one falling edge to the following rising edge. deviate from one cycle to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL locking time. 17. The cumulative jitter error (tERRnPER), where n is the number of clocks between 2 and 50, is the amount of clock time allowed to accumulate consecutively away from the average clock over n number of clock cycles. tDS (base) and tDH (base) values are for a single-ended 1V/ns DQ slew rate and 2V/ns for differential DQS, DQS\ slew rate. 18. 5. 19. These parameters are measured from a data signal (DM, DQ0, DQ1 … DQn and so forth) transition edge to its respective data strobe signal (DQS, DQS\) crossing. The setup and hold times are listed converting the base specification values (to which derating tables apply) to VREF when the slew rate is 1V/ns. These values, with a slew rate of 1V/ns are for reference only. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJITPER (larger of tJITPER (MIN) or tJITPER (MAX) of the input clock (output deratings are relative to the SDRAM input clock). Single-ended signal parameter. The SDRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by the actual jitter error when input clock jitter is present, even when within specification. This results in each parameter becoming larger. The following parameters are required to be derated by subtracting tERR10PER (MAX); tDQSCK (MIN), tLZ (DQS) MAX, tLZ (DQ) MAX, and tAON (MAX). The parameter tRPRE (MIN) is derated by subtracting tJITPER (MAX), while tRPRE (MAX) is derated by tJITPER (MIN). The maximum preamble is bound by tLZDQS (MAX). These parameters are measured from a data strobe signal (DQS, DQS\) crossing to its respective clock signal (CK, CK\) crossing. The specification values are not affected by the amount of clock jitter applied, as these are relative to the clock signal crossing. These parameters should be met whether clock jitter is present or not. The tDQSCK DLL_DIS parameter begins CL + AL - 1 cycles after the READ command. The maximum postamble is bound by tHZDQS (MAX). Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT commands. In addition, after any change of latency tXPDLL, timing must be met. tIS 20. 6. 21. 7. 22. 23. 8. 9. 25. 11. 26. 27. 28. 12. 29. 13. (base) and tIH (base) values are for a single-ended 1 V/ns control/command/ address slew rate and 2 V/ns CK, CK# differential slew rate. These parameters are measured from a command/address signal transition edge to its respective clock (CK, CK\) signal crossing. The specification values are not affected by the amount of clock jitter applied as the setup and hold times are relative to the clock signal crossing that latches the command/address. These parameters should be met whether clock jitter is present or not. For these parameters, the DDR3 SDRAM device supports tnPARAM (nCK) = RU (tPARAM [ns]/ tCK[AVG][ns]), assuming all input clock 30. 14. 15. 31. 16. The cycle-to-cycle jitter (tJITCC) is the amount the clock period can LOGIC Devices Incorporated www.logicdevices.com 56 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) NOTES CONTINUED jitter specifications are satisfied. For example, the device will support tnRP (nCK) = RU (tRP)/tCK[AVG]) if all input clock jitter specifications are met. This means for DDR2-800; 6-6-6, of which tRP = 15ns, the device will support tnRP = RU (tRP/tCK [AVG]) = 6 as long as the input clock jitter specifications are met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0+6 are valid even if six clocks are less than 15ns due to input clock jitter. 32. During READs and WRITEs with AUTO PRECHARGE, the DDR3 SDRAM will hold off the internal PRECHARGE command until tRAS (MIN) has been satisfied. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for tWR. The start of the write recovery time is defined as follows: • For BL8 (fixed by MRS and OTF): Rising clock edge four clock cycles after WL. • For BC4 (OTF): Rising clock edge four clock cycles after WL. • For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL. 35. RESET\ should be LOW as soon as power starts to ramp to ensure the outputs are in HIGH-Z Until RESET\ is LOW, the outputs are at risk of driving the bus and could result in excessive current, depending on the bus activity. The refresh period is 64ms when Tc is less than or equal to 85˚C. This equates to an average refresh rate of 7.8124μs. However, nine REFRESH commands should be asserted at least once every 70.3μs. When Tc is greater than 85˚C, the refresh period is 32ms and when Tc is greater than 105˚C, the refresh period is 24ms. 41. 42. 40. 37. Although CKE is allowed to be registered LOW after a REFRESH command when tREFPDEN (MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN) is required. ODT turn-on time MIN is when the device leaves HIGH-Z and ODT resistance begins to turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT reference load is shown in Figure 23. Half-clock output parameters must derated by the actual tERR10PER and tJITDTY when input clock jitter is present. This results in each parameter becoming larger. The parameters tADC (MIN) and tAOF(MIN) are each required to be derated by subtracting both tERR10PER (MAX) and tJITDTY (MAX). The parameters tADC (MAX) and tAOF (MAX) are required to be derated by subtracting both tERR10PER (MAX) and tJITDTY (MAX). ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT turn-off time maximum is when the SDRAM buffer is in HIGH-Z. The ODT reference load is shown in Figure 24. This output load is used for ODT timings (see Figure 31). Pulse width of an input signal is defined as the width between the first crossing of VREF (DC) and the consecutive crossing of VREF(DC). Should the clock rate be larger than tRFC(MIN), an AUTO REFRESH command should have at least one NOP command between it and another AUTO REFRESH command. Additionally, if the clock rate is slower than 40ns (25MHz) all REFRESH commands should be followed by a PRECHARGE ALL command. 38. 39. 33. 34. 36. LOGIC Devices Incorporated www.logicdevices.com 57 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) COMMAND AND ADDRESS SETUP, HOLD, AND DERATING The total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH (base) values (Tables 51) to the ∆tIS and ∆tIH derating values (Table 52), respectively. Although the total setup time for slow slew rates might be negative, a valid input signal is still required to complete the transition and to reach VIH(AC)/VIL(AC) (see Figure 14 for input signal requirements). For slew rates which fall between the values listed in Table 52 and Table 53, the derating values may be obtained by linear interpolation. Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC) MIN. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between the shaded “VREF(DC)-to-AC region”, use the nominal slew rate for derating value (see Figure 25). If the actual signal is later than the nominal slew rate line anywhere between the shaded “VREF(DC)-to-AC region”, the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for the derating value (see Figure 27). Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC) MAX and the first crossing of VREF(DC). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between the shaded “DC-to-VREF(DC) region”, use the nominal slew rate for derating value (see Figure 26). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded ”DC-to-VREF(DC) region”, the slew rate of a tangent line to the actual signal from the DC level to the VREF(DC) level is used for the derating value (see Figure 28). TABLE 51: COMMAND AND ADDRESS SETUP AND HOLD VALUES REFERENCED AT 1V/NS – AC/DC BASED Symbol tIS(base)AC175 tIS(base)AC150 tIH(base)DC100 DDR3-800 200 350 275 DDR3-1066 125 275 200 DDR3-1333 65 190 140 UNITS ps ps ps REFERENCE VIH(AC)/VIL(AC) VIH(AC)/VIL(AC) VIH(AC)/VIL(AC) TABLE 52: DERATING VALUES FOR tIS/tIH – AC175/DC100-BASED Shaded cells indicate slew-rate combinations not supported ∆tIS, ∆tIH Derating (ps) - AC/DC-Based, AC175 Threshold; VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV CMD/ADDR Slew Rate V/ns 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 CK, CK\ Differential Slew Rate 4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 1.6V/ns 1.4V/ns 1.2V/ns 1.0V/ns ∆tIS 88 59 0 -2 -6 -11 -17 -35 -62 ∆tIH 50 34 0 -4 -10 -16 -26 -40 -60 ∆tIS 88 50 0 -2 -6 -11 -17 -35 -62 ∆tIH 50 34 0 -4 -10 -16 -26 -40 -60 ∆tIS 88 59 0 -2 -6 -11 -17 -35 -62 ∆tIH 50 34 0 -4 -10 -16 -26 -40 -60 ∆tIS 96 67 8 6 2 -3 -9 -27 -54 ∆tIH 58 42 8 4 -2 -8 -18 -32 -52 ∆tIS 96 67 8 6 2 -3 -9 -27 -54 ∆tIH 66 50 16 12 6 0 -10 -24 -44 ∆tIS 112 83 24 22 18 13 7 -11 -38 ∆tIH 74 58 24 20 14 8 -2 -16 -36 ∆tIS 120 91 32 30 26 21 15 -2 -30 ∆tIH 84 68 34 30 24 18 8 -6 -26 ∆tIS 128 99 40 38 34 29 23 5 -22 ∆tIH 100 84 50 46 40 34 24 10 -10 LOGIC Devices Incorporated www.logicdevices.com 58 High Performance, Integrated Memory Module Product Jul 06, 2009 LDS-L9D345G72BG5-A ADVANCE INFORMATION L 9D345G72BG5 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD) TABLE 53: DERATING VALUES FOR tIS/tIH – AC150/DC100-BASED Shaded cells indicate slew-rate combinations not supported ∆tIS, ∆tIH Derating (ps) - AC/DC-Based, AC150 Threshold; VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV CMD/ADDR Slew Rate V/ns 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 CK, CK\ Differential Slew Rate 4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 1.6V/ns 1.4V/ns 1.2V/ns 1.0V/ns ∆tIS 75 50 0 0 0 0 -1 -10 -25 ∆tIH 50 34 0 -4 -10 -16 -26 -40 -60 ∆tIS 75 50 0 0 0 0 -1 -10 -25 ∆tIH 50 34 0 -4 -10 -16 -26 -40 -60 ∆tIS 75 50 0 0 0 0 -1 -10 -25 ∆tIH 50 34 0 -4 -10 -16 -26 -40 -60 ∆tIS 83 58 8 8 8 8 7 -2 -17 ∆tIH 58 42 8 4 -2 -8 -18 -32 -52 ∆tIS 91 66 16 16 16 16 15 6 -9 ∆tIH 66 50 16 12 6 0 -10 -24 -44 ∆tIS 99 74 24 24 24 24 23 14 -1 ∆tIH 74 58 24 20 14 8 -2 -16 -36 ∆tIS 107 82 32 32 32 32 31 22 7 ∆tIH 84 68 34 30 24 18 8 -6 -26 ∆tIS 115 90 40 40 40 40 39 30 15 ∆tIH 100 84 50 46 40 34 24 10 -10 TABLE 54: MINIMUM REQUIRED TIME tVAC ABOVE VIH(AC) FOR A VALID TRANSITION Below VIL(AC) Slew Rate (V/ns) >2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5