LF2247

LF2247 DEVICES INCORPORATED Image Filter with Coefficient RAM LF2247 DEVICES INCORPORATED Image Filter with Coefficient RAM DESCRIPTION The LF2247 consists of an array of four 11 x 10-bit registered multipliers followed by a summer and a 25-bit accumulator. The LF2247 provides a coefficient register file containing four 32 x 11-bit registers which are capable of storing 32 different sets of filter coefficients for the multiplier array. All multiplier data inputs are user accessible and can be updated every clock cycle with either fractional or integer two’s complement data. The pipelined architecture has fully registered input and output ports and an asynchronous three-state output enable control to simplify the design of complex systems. The pipeline latency for all inputs is five clock cycles. A 25-bit accumulator path allows cumulative word growth which may be internally rounded to 16 bits. Output data is updated every clock cycle and may be held under user control. The data inputs/outputs and control inputs are registered on the rising edge of CLK. The Serial Data In signal, SDIN, is registered on the FEATURES u 66 MHz Data Input and Computation Rate u Four 11 x 10-bit Multipliers with Individual Data and Coefficient Inputs and a 25-bit Accumulator u Four 32 x 11-bit Serially Loadable Coefficient Registers u Fractional or Integer Two’s Complement Operands u Package Styles Available: • 84-pin PLCC, J-Lead • 100-pin PQFP 1 2 3 4 5 6 LF2247 BLOCK DIAGRAM ENBA 5 A4-0 COEFFICIENT REGISTER FILE SDIN SEN SCLK D19-0 10 ENB1 Coefficient Register 1 (32 x 11-bit) SEN SCLK D29-0 ENB2 Coefficient Register 2 (32 x 11-bit) SEN SCLK D39-0 ENB3 Coefficient Register 3 (32 x 11-bit) SEN SCLK D49-0 ENB4 Coefficient Register 4 (32 x 11-bit) 7 8 11 10 11 10 11 10 11 9 10 22 ACC 22 11 25 OCEN FSEL MS LS OEN 16 CLK TO ALL REGISTERS (EXCEPT COEFFICIENT REGISTERS) S15-0 Video Imaging Products 1 08/16/2000–LDS.2247-H LF2247 DEVICES INCORPORATED Image Filter with Coefficient RAM Inputs D19-0 – D49-0 — Data Input FIGURE 1A. INPUT FORMATS Data Coefficient Fractional Two's Complement (FSEL = 0) 987 –20 2–1 2–2 (Sign) 210 2–7 2–8 2–9 10 9 8 –21 20 2–1 (Sign) 210 2–7 2–8 2–9 D1–D4 are the 10-bit registered data input ports. Data is latched on the rising edge of CLK. A4-0 — Row Address A4-0 determines which row of data in the coefficient register file is used to feed data to the multiplier array. A4-0 is latched on the rising edge of CLK. When a new row address is loaded into the row address register, data from the register file will be latched into the multiplier input registers on the next rising edge of CLK. SDIN — Serial Data Input SDIN is used to serially load data into the coefficient registers. Data present on SDIN is shifted into the coefficient register file on the rising edge of SCLK when SEN is LOW. The 11-bit coefficients are loaded into the coefficient register file in 16-bit words as shown in Figure 2. The five most significant bits of the first 16-bit word determine which row the data is written to in the coefficient registers. Note that the five most significant bits of the remaining three 16-bit words are ignored. After all four 16-bit words are shifted into the register file, the lower eleven bits of each word (the coefficient data) are stored into the coefficient registers. Outputs S15-0 — Data Output S15-0 is the 16-bit registered data output port. Controls ENB1–ENB4 — Data Input Enables The ENBN (N = 1, 2, 3, or 4) inputs allow the DN registers to be updated on each clock cycle. When ENBN is LOW, data on DN9-0 is latched into Integer Two's Complement (FSEL = 1) 987 –29 28 27 (Sign) 210 22 21 20 10 9 8 –210 29 28 (Sign) 210 22 21 20 FIGURE 1B. OUTPUT FORMATS Fractional Two's Complement (FSEL = 0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 –26 25 24 23 22 21 20 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 (Sign) Integer Two's Complement (FSEL = 1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 –215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 (Sign) rising edge of SCLK. The LF2247 operates at a clock rate of 66 MHz over the full temperature and supply voltage ranges. The LF2247 is applicable for performing pixel interpolation in image manipulation and filtering applications. The LF2247 can perform a bilinear interpolation of an image (4pixel kernels) at real-time video rates when used with an image resampling sequencer. Larger kernels or more complex functions can be realized by utilizing multiple devices. Unrestricted access to all data ports and an addressable coefficient register file provides the LF2247 with considerable flexibility in applications such as digital filters, adaptive FIR filters, mixers, and other similar systems requiring high-speed processing. SIGNAL DEFINITIONS Power VCC and GND +5 V power supply. All pins must be connected. Clocks CLK — Master Clock The rising edge of CLK strobes all enabled registers except for the coefficient registers. SCLK — Serial Clock The rising edge of SCLK shifts data into and through the coefficient register file when it is enabled for serial data shifting. Video Imaging Products -2 08/16/2000–LDS.2247-H LF2247 DEVICES INCORPORATED Image Filter with Coefficient RAM FIGURE 2. SERIAL DATA FORMAT FIRST 16-BIT WORD SECOND 16-BIT WORD the DN register on the rising edge of CLK. When ENBN is HIGH, data on DN9-0 is not latched into the DN register and the register contents will not be changed. ENBA — Row Address Input Enable The ENBA input allows the row address register to be updated on each clock cycle. When ENBA is LOW, data on A4-0 is latched into the row address register on the rising edge of CLK. When ENBA is HIGH, data on A4-0 is not latched into the row address register and the register contents will not be changed. OEN — Output Enable When OEN is LOW, S15-0 is enabled for output. When OEN is HIGH, S15-0 is placed in a high-impedance state. OCEN — Clock Enable When OCEN is LOW, data in the premux register (accumulator output) is loaded into the output register on the next rising edge of CLK. When OCEN is HIGH, data in the pre-mux register is held preventing the output register’s contents from changing (if FSEL does not change). Accumulation continues internally as long as ACC is HIGH, despite the state of OCEN. FSEL — Format Select When FSEL is LOW, the data input during the current clock cycle is assumed to be in fractional two’s complement format, and the upper 16 bits of the accumulator are presented at the output. Rounding of the accumulator result to 16 bits is per- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 0001011111101100XXXXX00010001100 ROW ADDRESS DATA FOR COEFFICIENT REGISTER 4 DON'T CARES DATA FOR COEFFICIENT REGISTER 3 1 2 3 4 THIRD 16-BIT WORD FOURTH 16-BIT WORD 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 XXXXX00110100100XXXXX11111100100 DON'T CARES DATA FOR COEFFICIENT REGISTER 2 DON'T CARES DATA FOR COEFFICIENT REGISTER 1 SHOWN IS SERIAL DATA STREAM TO LOAD ROW ADDRESS 2 WITH: COEFFICIENT REGISTER 1 = 7E4 COEFFICIENT REGISTER 2 = 1A4 COEFFICIENT REGISTER 3 = 08C COEFFICIENT REGISTER 4 = 7EC 5 6 7 8 9 10 11 formed if the accumulator control input ACC is LOW. When FSEL is HIGH, the data input is assumed to be in integer two’s complement format, and the lower 16 bits of the accumulator are presented at the output. No rounding is performed when FSEL is HIGH. ACC — Accumulator Control The ACC input determines whether internal accumulation is performed on the data input during the current clock cycle. If ACC is LOW, no accumulation is performed, the prior accumulated sum is cleared, and the current sum of products is output. If FSEL is also LOW, one-half LSB rounding to 16 bits is performed on the result. When ACC is HIGH, the emerging product is added to the sum of the previous products, without additional rounding. SEN — Serial Input Enable The SEN input enables the shifting of serial data through the registers in the coefficient register file. When SEN is LOW, serial data on SDIN is shifted into the coefficient register file on the rising edge of SCLK. SEN must remain LOW until all four coefficients have been clocked in. SEN does not need to be pulsed between consecutive data sets. It can remain LOW while the entire register file is loaded by a constant bit stream. When SEN is HIGH, data can not be shifted into the register file and the register file’s contents will not be changed. When enabling the coefficient register file for serial data input, the LF2247 requires a HIGH to LOW transition of SEN in order to function properly. Therefore, SEN needs to be set HIGH immediately after power up to ensure proper operation of the serial input circuitry. Video Imaging Products 3 08/16/2000–LDS.2247-H LF2247 DEVICES INCORPORATED Image Filter with Coefficient RAM MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ............................................................................... –0.5 V to V CC + 0.5 V Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0°C to +70°C –55°C to +125°C Supply Voltage 4.75 V ≤ VCC ≤ 5.25 V 4.50 V ≤ VCC ≤ 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol VOH VOL VIH VIL IIX IOZ ICC1 ICC2 CIN COUT Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent Input Capacitance Output Capacitance (Note 3) Test Condition VCC = Min., IOH = –2.0 mA VCC = Min., IOL = 4.0 mA Min 2.4 Typ Max Unit V 0.4 2.0 0.0 VCC 0.8 ±10 ±40 100 6.0 10 10 V V V µA µA mA mA pF pF Ground ≤ VIN ≤ VCC (Note 12) Ground ≤ VOUT ≤ VCC (Note 12) (Notes 5, 6) (Note 7) TA = 25°C, f = 1 MHz TA = 25°C, f = 1 MHz Video Imaging Products -4 08/16/2000–LDS.2247-H 432109876543210987654321 432109876543210987654321 432109876543210987654321 *DISCONTINUED SPEED GRADE Symbol Symbol S15-0 HIGH IMPEDANCE 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 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OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) SWITCHING WAVEFORMS: SWITCHING CHARACTERISTICS tENA tDIS tD tH tS tPWH tPWL tCYC tENA tDIS tD tH tS tPWH tPWL tCYC CONTROLS (Except OEN) D19-0 – D49-0 OEN Three-State Output Enable Delay (Note 11) Three-State Output Disable Delay (Note 11) Output Delay Input Hold Time Input Setup Time Clock Pulse Width High Clock Pulse Width Low Cycle Time Parameter Parameter Three-State Output Enable Delay (Note 11) Three-State Output Disable Delay (Note 11) Output Delay Input Hold Time Input Setup Time Clock Pulse Width High Clock Pulse Width Low Cycle Time CLK A4-0 tS AN+1 DN tH 1 DATA I/O DN+1 AN+2 2 tDIS 5 tPWH 3 tCYC tENA tPWL 10 15 33 10 Image Filter with Coefficient RAM 0 33* 4 Max 15 15 15 SN–1 Video Imaging Products Min 10 15 33 10 10 10 25 0 0 8 LF2247– 25 tD 33* 5 Max Max 15 15 15 15 15 13 LF2247– SN Min Min 08/16/2000–LDS.2247-H 10 10 25 15 0 8 7 0 7 5 6 LF2247 25* 15 SN+1 Max Max 15 15 13 11 15 15 11 10 9 8 7 6 5 4 3 2 1 432109876543210987654321 432109876543210987654321 432109876543210987654321 *DISCONTINUED SPEED GRADE Symbol Symbol 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 Min 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 543210987654321 6543210987654321 6543210987654321 6 Min DEVICES INCORPORATED MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) SWITCHING WAVEFORMS: tSH tSS tSENH tSENS tSWH tSWL tSCYC SWITCHING CHARACTERISTICS tSH tSS tSENH tSENS tSWH tSWL tSCYC SCLK SDIN SEN Serial Data Input Hold Time Serial Data Input Setup Time Serial Enable Hold Time Serial Enable Setup Time Serial Clock Pulse Width High Serial Clock Pulse Width Low Serial Interface Cycle Time Parameter Parameter Serial Data Input Hold Time Serial Data Input Setup Time Serial Enable Hold Time Serial Enable Setup Time Serial Clock Pulse Width High Serial Clock Pulse Width Low Serial Interface Cycle Time tSENS tSS A4 tSH SERIAL DATA INPUT 1 tSWL tSCYC A3 tSWH 2 -6 62 20 20 30 30 Image Filter with Coefficient RAM 0 0 33* C11 Max 63 Video Imaging Products Min 62 20 20 30 30 62 20 20 30 30 0 0 0 0 LF2247– 25 33* Max Max LF2247– C10 tSENH Min 64 Min 62 20 20 30 30 08/16/2000–LDS.2247-H 62 20 20 30 30 0 0 0 0 LF2247 25* 15 Max Max LF2247 DEVICES INCORPORATED Image Filter with Coefficient RAM NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of I OH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter6. Tested with all outputs changing ev- nal system must supply at least that ery cycle and no load, at a 30 MHz clock much time to meet the worst-case requirements of all parts. Responses from rate. the internal circuitry are specified from 7. Tested with all inputs within 0.1 V of the point of view of the device. Output VCC or Ground, no load. delay, for example, is specified as a 8. These parameters are guaranteed maximum since worst-case operation of any device always provides data within but not 100% tested. that time. N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. 1 2 3 4 5 FIGURE A. OUTPUT LOADING CIRCUIT DUT S1 IOL CL IOH VTH 6 7 8 9 10 11 FIGURE B. THRESHOLD LEVELS tENA OE Z 0 1.5 V 1.5 V 1.5 V tDIS 3.5V Vth VOL* 0.2 V 0 1 Z Z 1.5 V VOH* 0.2 V Z 1 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA Video Imaging Products 7 08/16/2000–LDS.2247-H LF2247 DEVICES INCORPORATED Image Filter with Coefficient RAM ORDERING INFORMATION 84-pin S0 S1 GND S2 S3 S4 VCC S5 S6 S7 GND S8 S9 S10 VCC S11 S12 S13 GND S14 S15 D15 D14 D13 D12 D11 D10 D19 D18 D17 D16 GND SDIN VCC SCLK SEN A0 A1 A2 A3 A4 ENBA 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 74 13 73 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 72 71 70 69 68 67 66 Top View 65 64 63 62 61 60 59 58 57 56 55 32 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 CLK ENB1 ENB2 ENB3 D49 D48 D47 D46 D45 D44 D43 D42 D41 GND D40 ENB4 GND OEN OCEN ACC FSEL Speed 0°C to +70°C — COMMERCIAL SCREENING 15 ns LF2247JC15 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D39 GND D38 D37 D36 D35 D34 D33 D32 D31 D30 Plastic J-Lead Chip Carrier (J3) Video Imaging Products -8 08/16/2000–LDS.2247-H LF2247 DEVICES INCORPORATED Image Filter with Coefficient RAM ORDERING INFORMATION S1 GND GND S2 S3 S4 VCC S5 S6 S7 GND S8 S9 S10 VCC S11 S12 S13 GND S14 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100-pin S0 NC D15 D14 D13 D12 D11 D10 D19 D18 D17 D16 GND GND NC SDIN NC VCC VCC SCLK SEN A0 A1 A2 A3 A4 ENBA NC NC D20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Top View 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 S15 CLK NC ENB1 ENB2 ENB3 D49 D48 D47 D46 D45 D44 D43 D42 D41 GND GND D40 ENB4 NC GND GND OEN OCEN ACC FSEL NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 Speed 0°C to +70°C — COMMERCIAL SCREENING 25 ns 15 ns LF2247QC25 LF2247QC15 D21 D22 D23 D24 D25 D26 D27 D28 D29 D39 GND D38 D37 D36 D35 D34 D33 D32 D31 D30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Plastic Quad Flatpack (Q2) Video Imaging Products 9 08/16/2000–LDS.2247-H 121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 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INCORPORATED Speed –55°C to +125°C — MIL-STD-883 COMPLIANT –55°C to +125°C — COMMERCIAL SCREENING 0°C to +70°C — COMMERCIAL SCREENING ORDERING INFORMATION 84-pin G H D C K E B A F L J ENB2 D49 GND D15 GND VCC S13 S14 S15 ENB1 ENB3 D47 S5 S3 S4 S6 1 GND CLK VCC S10 S11 S1 S2 S7 2 D14 D48 S12 S0 S8 S9 3 Ceramic Pin Grid Array (G3) Discontinued Package D12 D13 D46 4 (i.e., Component Side Pinout) -10 D19 D10 D11 D45 D44 GND ENB4 OCEN D30 D43 5 Through Package Top View VCC GND SCLK D18 SDIN SEN D17 D42 D41 GND 6 D40 OEN ACC FSEL D32 D16 7 Image Filter with Coefficient RAM 8 D27 D28 D38 GND D39 A0 A2 9 ENBA D21 D31 D22 D25 D36 D33 D24 10 Video Imaging Products A1 A4 D20 D23 D26 D29 D37 D35 D34 11 A3 08/16/2000–LDS.2247-H LF2247