LF3347

LF3347 DEVICES INCORPORATED High-Speed Image Filter with Coefficient RAM LF3347 DEVICES INCORPORATED High-Speed Image Filter with Coefficient RAM DESCRIPTION The LF3347 consists of an array of four 12 x 12-bit registered multipliers followed by two summers and a 32-bit accumulator. The LF3347 provides four 256 x 12-bit coefficient banks which are capable of storing 256 different sets of filter coefficients for the multiplier array. All multiplier data inputs are user accessible and can be updated every clock cycle with two’s complement data. The pipelined architecture has fully registered input and output ports and an asynchronous three-state output enable control to simplify the design of complex systems. A 32-bit accumulator allows cumulative word growth which may be internally rounded to 16-bits. Output data is updated every clock cycle and may be held under user control. The data inputs/outputs and control inputs are registered on the rising edge of CLK. The Control/Coefficient Data Input, CC11-0, is registered on the rising edge of CCCLK. The LF3347 is ideal for performing pixel interpolation in image manipulation and filtering applications. The LF3347 can perform a bilinear interpolation of an image (4-pixel kernels) at real-time video rates when used FEATURES u 83 MHz Data Input and Computation Rate u Four 12 x 12-bit Multipliers with Individual Data and Coefficient Inputs u Four 256 x 12-bit Coefficient Banks u 32-bit Accumulator u Selectable 16-bit Data Output with User-Defined Rounding and Limiting u u u u Two’s Complement Operands 3.3 Volt Power Supply 5 Volt Tolerant I/O 120-pin PQFP LF3347 BLOCK DIAGRAM 12 CC11-0 LD CCCLK ENBA 8 A7-0 Coefficient Bank 1 (256 x 12-bit) ENB1 12 2 D211-0 12 2 ENB2 12 Coefficient Bank 2 (256 x 12-bit) D311-0 12 2 ENB3 12 Coefficient Bank 3 (256 x 12-bit) D411-0 12 2 ENB4 12 Coefficient Bank 4 (256 x 12-bit) LF INTERFACE D111-0 12 25 25 ACC 3 32 SELRND3-0 4 4 4 Rounding Selecting Limiting Circuit Rounding/ Limiting Registers SELLMT3-0 4 6 4 LMTEN 6 SHIFT4-0 5 5 5 16 OCEN OE 16 CLK TO ALL REGISTERS S15-0 NOTE: NUMBERS IN REGISTERS INDICATE NUMBER OF PIPELINE DELAYS Video Imaging Products 1 08/16/2000–LDS.3347-G LF3347 DEVICES INCORPORATED High-Speed Image Filter with Coefficient RAM FIGURE 1. INPUT FORMATS Data Coefficient Fractional Two's Complement 11 10 9 –20 2–1 2–2 (Sign) with an image resampling sequencer. Larger kernels or more complex functions can be realized by utilizing multiple devices. Unrestricted access to all data ports and addressable coefficient banks provides the LF3347 with considerable flexibility in applications such as digital filters, adaptive FIR filters, mixers, and other similar systems requiring highspeed processing. SIGNAL DEFINITIONS Power VCC and GND +3.3 V power supply. All pins must be connected. Clocks CLK — Master Clock The rising edge of CLK strobes all enabled registers. CCCLK — Coefficient/Control Clock When LD is LOW, the rising edge of CCCLK latches data on CC11-0 into the device. Inputs D111-0 – D411-0 — Data Input D1–D4 are the 12-bit registered data input ports. Data is latched on the rising edge of CLK. A7-0 — Row Address A7-0 determines which row in the coefficient banks feed data to the multipliers. A 7-0 is latched on the rising edge of CLK. When a new row address is loaded into the row address register, data from the coefficient banks will be latched into the multiplier input registers on the next rising edge of CLK. 210 2–9 2–10 2–11 11 10 9 –20 2–1 2–2 (Sign) 210 2–9 2–10 2–11 Integer Two's Complement 11 10 9 –211 210 29 (Sign) 210 22 21 20 11 10 9 –211 210 29 (Sign) 210 22 21 20 TABLE 1. OUTPUT FORMATS SHIFT4-0 00000 00001 00010 S15 S14 S13 F15 F14 F13 F16 F15 F14 F17 F16 F15 ··· ··· ··· ··· S8 F8 F9 F10 S7 F7 F8 F9 ··· ··· ··· ··· S2 F2 F3 F4 S1 F1 F2 F3 S0 F0 F1 F2 · · · 01110 01111 10000 · · · · · · · · · ··· ··· ··· · · · · · · ··· ··· ··· · · · · · · · · · F29 F28 F27 F30 F29 F28 F31 F30 F29 F22 F21 F23 F22 F24 F23 F16 F15 F14 F17 F16 F15 F18 F17 F16 CC11-0 — Control/Coefficient Data Input CC11-0 is used to load data into the coefficient banks and control registers. Data present on CC11-0 is latched on the rising edge of CCCLK when LD is LOW. Outputs S15-0 — Data Output S15-0 is the 16-bit registered data output port. Controls ENB1–ENB4 — Data Input Enables The ENBN (N = 1, 2, 3, or 4) inputs allow the DN registers to be updated on each clock cycle. When ENBN is LOW, data on DN11-0 is latched into the DN register on the rising edge of CLK. When ENBN is HIGH, data on D N11-0 is not latched into the DN register and the register contents will not be changed. ENBA — Row Address Input Enable The ENBA input allows the row address register to be updated on each clock cycle. When ENBA is LOW, data on A 7-0 is latched into the row address register on the rising edge of CLK. When ENBA is HIGH, data on A 7-0 is not latched into the row address register and the register contents will not be changed. OE — Output Enable When OE is LOW, S15-0 is enabled for output. When OE is HIGH, S15-0 is placed in a high-impedance state. Video Imaging Products 2 08/16/2000–LDS.3347-G LF3347 DEVICES INCORPORATED High-Speed Image Filter with Coefficient RAM TABLE 2. Register CS0 CS1 CS255 RND0 RND1 RND15 LMT0 LMT1 LMT15 REGISTER FORMATS Load Address 000H 001H 0FFH 800H 801H 80FH C00H C01H C0FH Bits 11-0 11-0 11-0 31-0 31-0 31-0 31-16/15-0 31-16/15-0 Register Description Coefficient Set 0 Coefficient Set 1 Coefficient Set 255 Rounding Register 0 Rounding Register 1 Rounding Register 15 Upper / Lower Limit Register 0 Upper / Lower Limit Register 0 A7-0 00H 01H FFH 0000 0001 1111 0000 0001 1111 SELRND3-0 SELLMT3-0 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 31-16/15-0 Upper / Lower Limit Register 15 power up to ensure proper operation of the input circuitry. It takes five CCCLK clock cycles to load one coefficient set into the four coefficient banks or to load one control register. When the input circuitry is enabled (LD goes LOW), the first value loaded into the device on CC11-0 is an address which determines what will be loaded (see Table 2). The next four values loaded on CC11-0 is the data to be loaded into the coefficient banks or control register (see Tables 3-5). After the last data value is loaded, another coefficient bank address or control register may be loaded by feeding another address into CC11-0. When all desired coefficient banks and control registers are loaded, the input circuitry must be disabled by setting LD HIGH. SELRND3-0 — Round Select SELRND3-0 allows the user to select which rounding register will be used in the rounding circuit to round/offset the data. SHIFT4-0 — Shift SHIFT4-0 determines which 16-bits of the 32-bits from the accumulator are passed to the output (see Table 1). · · · · · · · · · OCEN — Output Clock Enable When OCEN is LOW, the output register is enabled for data loading. When OCEN is HIGH, output register loading is disabled and the register’s contents will not change. ACC — Accumulator Control The ACC input determines whether internal accumulation is performed. If ACC is LOW, no accumulation is performed, the prior accumulated sum is cleared, and the current sum of products is output. When ACC is HIGH, the emerging product is added to the sum of the previous products. LD — Load Control LD enables the loading of data into the coefficient banks and control registers (control registers are the round and limit registers). When LD is LOW, data on CC11-0 is latched into the device on the rising edge of CCCLK. When LD is HIGH, data cannot be loaded into the coefficient banks and control registers. When enabling the input circuitry for data loading, the LF3347 requires a HIGH to LOW transition of LD in order to function properly. Therefore, LD needs to be set HIGH immediately after FIGURE 2. ROUNDING, SELECTING, LIMITING CIRCUITRY 32 RND31-0 RND 32 32 SHIFT4-0 SELECT 16 16 ULMT15-0 LLMT15-0 LIMIT 16 LMTEN SELLMT3-0 — Limit Select SELLMT3-0 allows the user to control which limiting register will be used in the limiting circuit to set the upper and lower limits on the data. LMTEN — Limit Enable When LMTEN is LOW, limiting is enabled and the selected limit register is used to determine the valid range of output values for the overall filter. When HIGH, limiting is disabled. Video Imaging Products 3 08/16/2000–LDS.3347-G LF3347 DEVICES INCORPORATED High-Speed Image Filter with Coefficient RAM registers. Each limit register contains both an upper and lower limit value. The lower limit is stored in bits 15-0 and the upper limit is stored in bits 31-16. If the value fed to the limiting circuitry is less than the lower limit, the lower limit is passed to the device output. If the value fed to the limiting circuitry is greater than the upper limit, the upper limit is passed to the device output. When loading limit values into the device, the upper limit must be greater than the lower limit. In the example shown in Table 4, limit register 15 is loaded with a lower limit of 0123H and an upper limit of 7FEDH. A limit register is not written to until all four data values have been loaded into the device. SELLMT3-0 determines which limit register is used for limiting. A value of 0 on SELLMT3-0 selects limit register 0. A value of 1 selects limit register 1 and so on. FUNCTIONAL DESCRIPTION Coefficient Banks The LF3347 has four coefficient banks which feed coefficient values to the multipliers. Each bank can store 256 12-bit coefficients. In the example shown in Table 3, address 10 in coefficient banks 1 through 4 is loaded with the following values: ABCH, 789H, 456H, 123H. The coefficient banks are not written to until all four coefficients have been loaded into the device. A7-0 determines which coefficient set is sent to the multipliers. A value of 0 on A7-0 selects set 0. A value of 1 selects set 1 and so on. Rounding/Offset The accumulator output may be rounded before being sent to the output select section. Rounding is user-selectable and is accomplished by adding the contents of a round register to the accumulator output (see Figure 2). There are sixteen 32-bit round registers. In the example in Table 4, round register 10 is loaded with 76543210H. A round register is not written to until all four data values have been loaded into the device. SELRND3-0 determines which round register is used for rounding. A value of 0 on SELRND3-0 selects round register 0. A value of 1 selects round register 1 and so on. If rounding is not desired, a round register should be loaded with 0 and selected as the register for rounding. Output Select The filter output word width is 32-bits. However, only 16-bits may be sent to the device output. SHIFT4-0 determines which 16 bits are passed to the device output (See Table 1). Output Limiting An output limiting function is provided for the output of the filter. When limiting is enabled (LMTEN LOW), the limit register selected with SELLMT3-0 determines the valid range of output values for the overall filter. There are sixteen 32-bit limit TABLE 3. 1st Word Address 2nd Word Bank 1 3rd Word Bank 2 4th Word Bank 3 5th Word Bank 4 COEFFICIENT BANK LOADING FORMAT CC11 CC10 CC9 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 0 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 1 1 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 1 0 1 TABLE 4. 1st Word Address 2nd Word 3rd Word 4th Word 5th Word ROUND REGISTER LOADING FORMAT CC11 CC10 CC9 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 1 R R R R 0 R R R R 0 R R R R 0 R R R R 0 0 0 0 **0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 *0 0 0 0 R = Reserved. Must be set to “0”. * This bit represents the LSB of the Round Register. ** This bit represents the MSB of the Round Register. TABLE 5. 1st Word Address 2nd Word 3rd Word 4th Word 5th Word LIMIT REGISTER LOADING FORMAT CC11 CC10 CC9 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 1 R R R R 1 R R R R 0 R R R R 0 R R R R 0 0 *0 1 **0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 1 1 0 0 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 1 1 R = Reserved. Must be set to “0”. * This bit represents the MSB of the Lower Limit Register. ** This bit represents the MSB of Upper Limit Register. Video Imaging Products 4 08/16/2000–LDS.3347-G LF3347 DEVICES INCORPORATED High-Speed Image Filter with Coefficient RAM MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +4.5 V Input signal with respect to ground .......................................................................................... –0.5 V to 5.5 V Signal applied to high impedance output ................................................................................. –0.5 V to 5.5 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA ESD Classification (MIL-STD-883E METHOD 3015.7) ...................................................................... Class 3 OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0°C to +70°C –55°C to +125°C Supply Voltage 3.00 V ≤ VCC ≤ 3.60 V 3.00 V ≤ VCC ≤ 3.60 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol VOH VOL VIH VIL IIX IOZ ICC1 ICC2 CIN COUT Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent Input Capacitance Output Capacitance (Note 3) Test Condition VCC = Min., IOH = –4 mA VCC = Min., IOL = 8.0 mA Min 2.4 Typ Max Unit V 0.4 2.0 0.0 VCC 0.8 ±10 ±10 150 2 10 10 V V V µA µA mA mA pF pF Ground ≤ VIN ≤ VCC (Note 12) Ground ≤ VOUT ≤ VCC (Note 12) (Notes 5, 6) (Note 7) TA = 25°C, f = 1 MHz TA = 25°C, f = 1 MHz Video Imaging Products 5 08/16/2000–LDS.3347-G 432109876543210987654321 432109876543210987654321 432109876543210987654321 *DISCONTINUED SPEED GRADE Symbol Symbol S15-0 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 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6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 Min DEVICES INCORPORATED SWITCHING WAVEFORMS: MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) SWITCHING CHARACTERISTICS tENA tDIS tD tH tS tPWH tPWL tCYC tENA tDIS tD tH tS tPWH tPWL tCYC D111-0 – D411-0 CONTROLS (Except OE) CLK Parameter Parameter Three-State Output Enable Delay (Note 11) Three-State Output Disable Delay (Note 11) Output Delay Input Hold Time Input Setup Time Clock Pulse Width High Clock Pulse Width Low Cycle Time Three-State Output Enable Delay (Note 11) Three-State Output Disable Delay (Note 11) Output Delay Input Hold Time Input Setup Time Clock Pulse Width High Clock Pulse Width Low Cycle Time A7-0 OE tS DN AN tH 1 DATA I/O DN+1 AN+1 2 tDIS HIGH IMPEDANCE High-Speed Image Filter with Coefficient RAM tPWH 3 tCYC tENA 6 tPWL 4 10 10 10 10 25 25 0 0 8 8 25* 25* Max Max 13 15 13 13 15 13 5 Video Imaging Products Min Min 15 15 7 7 0 0 7 7 5 5 LF3347– 15* LF3347– 15 6 Max Max 11 12 10 11 12 10 SN-1 08/16/2000–LDS.3347-G Min Min 12 12 tD 5 5 0 0 5 5 3 3 7 LF3347 12* 12 SN Max Max 10 10 8 8 8 8 432109876543210987654321 432109876543210987654321 432109876543210987654321 *DISCONTINUED SPEED GRADE Symbol Symbol 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4 Min 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 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Parameter Control Coefficient Data Input Hold Time Control Coefficient Data Input Setup Time Control Coefficient Clock Pulse Width High Control Coefficient Clock Pulse Width Low Parameter Control Coefficient Data Input Hold Time Control Coefficient Data Input Setup Time Control Coefficient Clock Pulse Width High Control Coefficient Clock Pulse Width Low tCCENS tCCS ADDRESS tCCH 1 tCCWL COEFFICIENT BANK AND CONTROL REGISTER INPUT tSCYC C0 tCCWH 2 C1 High-Speed Image Filter with Coefficient RAM 3 7 C2 25 10 10 25 10 10 0 8 0 8 0 8 0 8 4 25* 25* Max Max C3 Video Imaging Products Min Min tCCENH 15 15 0 5 0 5 7 7 0 LF3347– 15* 5 0 LF3347– 15 5 7 7 5 Max Max 08/16/2000–LDS.3347-G Min Min 12 12 W 0 5 0 3 5 5 0 5 0 3 5 5 LF3347 12* 12 6 Max Max LF3347 DEVICES INCORPORATED High-Speed Image Filter with Coefficient RAM NOTES 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of IOH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Never- used. Parasitic capacitance is 30 pF theless, conventional precautions minimum, and may be distributed. should be observed during storage, handling, and use of these circuits in This device has high-speed outputs caorder to avoid exposure to excessive pable of large instantaneous current electrical stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping testing of this device. The following of transient undershoot. Input levels measures are recommended: below ground will be clamped beginning at –0.6 V. The device can with- a. A 0.1 µF ceramic capacitor should be stand indefinite operation with inputs installed between VCC and Ground or outputs in the range of –0.5 V to leads as close to the Device Under Test +5.5 V. Device operation will not be (DUT) as possible. Similar capacitors adversely affected, however, input cur- should be installed between device VCC rent levels will be well in excess of 100 and the tester common, and device mA. ground and tester common. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT socket or contactor fingers. anteed as specified. 5. Supply current for a given application can be accurately approximated by: NCV2 F c. Input voltages on a test fixture should be adjusted to compensate for inductive ground and VCC noise to maintain required DUT input levels relative to the DUT ground pin. 10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.0 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT S1 IOL CL IOH VTH DUT FIGURE B. THRESHOLD LEVELS tENA OE Z 0 1.5 V 1.5 V 1.5 V tDIS 3.0V Vth VOL* 0.2 V 0 1 Z Z 1.5 V VOH* 0.2 V Z 1 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA 4 where N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with all outputs changing every cycle and no load, at a 30 MHz clock rate. 7. Tested with all inputs within 0.1 V of VCC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. Video Imaging Products 8 08/16/2000–LDS.3347-G LF3347 DEVICES INCORPORATED High-Speed Image Filter with Coefficient RAM ORDERING INFORMATION CLK GND SELRND3 SELRND2 SELRND1 SELRND0 ACC ENB4 D411 D410 D49 D48 D47 D46 D45 D44 D43 D42 D41 D40 VCC GND ENB3 D311 D310 D39 D38 D37 D36 D35 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 SHIFT0 SHIFT1 SHIFT2 SHIFT3 SHIFT4 SELLMT0 SELLMT1 SELLMT2 SELLMT3 LMTEN OCEN OE VCC GND S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 120-pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Top View D34 D33 D32 D31 D30 CC11 CC10 CC9 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 CCCLK LD ENBA GND VCC A7 A6 A5 A4 A3 A2 A1 A0 Speed 0°C to +70°C — COMMERCIAL SCREENING 15 ns 12 ns LF3347QC15 LF3347QC12 VCC GND ENB1 D111 D110 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 VCC GND ENB2 D211 D210 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Plastic Quad Flatpack (Q1) Video Imaging Products 9 08/16/2000–LDS.3347-G 121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 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1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 DEVICES INCORPORATED Speed –55°C to +125°C — MIL-STD-883 COMPLIANT –55°C to +125°C — COMMERCIAL SCREENING 0°C to +70°C — COMMERCIAL SCREENING ORDERING INFORMATION 120-pin M G N H D C K E B A F L J SHIFT2 SHIFT1 GND SRND0 D411 D48 SLMT3 SLMT1 SHIFT3 SLMT0 SHIFT4 SHIFT0 SRND3 ACC D49 OCEN LMTEN SLMT2 GND VCC CLK SRND2 SRND1 ENB4 D410 D47 S12 S13 S0 S3 S4 S7 S9 1 ENB1 D19 GND D110 D18 S11 S15 S1 S5 S8 2 VCC D111 D17 S14 S10 OE S2 S6 3 D16 4 Discontinued Package Top View Through Package (i.e., Component Side Pinout) D14 D15 High-Speed Image Filter with Coefficient RAM 5 Ceramic Pin Grid Array (G4) KEY D11 GND ENB2 D29 D12 D13 6 10 VCC D210 D26 D10 D211 D28 D45 D44 D46 7 D41 ENB3 D38 D42 D43 8 VCC D311 D39 D40 GND D310 D37 9 D27 D25 D22 10 CC10 CC8 CC2 CC6 D24 D21 D32 CC11 CC9 D35 LD CCCLK CC0 11 A0 A3 A7 GND ENBA CC1 CC5 D23 D33 D36 12 A6 A1 A4 Video Imaging Products CC3 CC4 CC7 VCC D20 D30 D31 D34 13 A2 A5 08/16/2000–LDS.3347-G LF3347