LF43881

LF43881 DEVICES INCORPORATED 8 x 8-bit Digital Filter LF43881 DEVICES INCORPORATED 8 x 8-bit Digital Filter DESCRIPTION The LF43881 is a video-speed digital filter that contains eight filter cells (taps) cascaded internally and a shiftand-add output stage. An 8 x 8 multiplier, three decimation registers, and a 26-bit accumulator are contained in each filter cell. The output stage of the LF43881 contains a 26-bit accumulator which can add the contents of any filter stage to the output stage accumulator shifted right by 8 bits. 8-bit unsigned or two’s complement format for data and coefficients can be independently selected. Expanded coefficients and word sizes can be processed by cascading multiple LF43881s to implement larger filter lengths without affecting the sample rate. By reducing the sample rate, a single LF43881 can process larger filter lengths by using multiple passes. The sampling rate can range from 0 to 40 MHz. Over 1000 taps may be processed without overflows due to the architecture of the device. The output sample rate can be reduced to one-half, one-third, or onefourth the input sample rate by using the three decimation registers contained in every filter cell. Matrix multiplication, N x N spatial correlations/convolutions, and other 2-D operations for image processing can also be achieved using these registers. FEATURES u u u u 25 MHz Maximum Sampling Rate 320 MHz Multiply-Accumulate Rate 8 Filter Cells 8-bit Unsigned or Two’s Complement Data u 8-bit Unsigned or Two’s Complement Coefficients u 26-bit Data Outputs u Shift-and-Add Output Stage for Combining Filter Outputs u Expandable Data Size, Coefficient Size, and Filter Length u User-Selectable 2:1, 3:1, or 4:1 Decimation u Replaces Harris HSP43881 u 84-pin PLCC, J-Lead LF43881 BLOCK DIAGRAM DIN7-0 8 DIENB, CIENB, ERASE, DCM1-0 5 TCS TCCI CIN7-0 ADR2-0 8 FILTER CELL 0 8 FILTER CELL 1 8 FILTER CELL 2 8 FILTER CELL 3 8 FILTER CELL 4 8 FILTER CELL 5 8 FILTER CELL 6 8 FILTER CELL 7 TCCO 8 COUT7-0 COENB 3 26 26 26 26 26 26 26 26 MUX 26 SHADD SENBL SENBH RESET 26 OUTPUT STAGE TO ALL CELLS CLK TO ALL REGISTERS SUM25-0 Video Imaging Products 1 08/16/2000–LDS.43881-J LF43881 DEVICES INCORPORATED 8 x 8-bit Digital Filter FIGURE 1. FILTER CELL DIAGRAM CIENB.D DCM0.D DCM1.D TCCI CIN7 CIN7-0 LD C REG C.TCCI LD D1 REG LD D2 REG 1 MUX LD D3 REG 1 MUX TRI-STATE BUFFERS ON FILTER CELL 7 ONLY TCCO COUT7-0 COENB C7-0 D.TCCI D7-0 0 0 B DIENB.D TCS DIN7 DIN7-0 LD X REG C8-0 X8-0 M REG0 DCM1 DCM0 RESET DIENB CIENB ADR0 ADR1 ADR2 ERASE LATCHES DCM1.D DCM0.D RESET.D DIENB.D CIENB.D ADR0.D ADR1.D ADR2.D ERASE.D RESET.D ERASE.D ACCUMULATOR ACC25-0 SIGN EXTENSION 25-18 17-0 M REG1 CELL n CELL 0 CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 CELL 7 ACC.D25-0 ADR0 ADR1 ADR2 DECODER CELL n D Q LD T REG AOUT25-0 CLK RESET.D TO ALL REGISTERS TO ALL REGISTERS (EXCEPT ACCUMULATOR AND T-REGISTER) Video Imaging Products 2 08/16/2000–LDS.43881-J LF43881 DEVICES INCORPORATED 8 x 8-bit Digital Filter FIGURE 2. OUTPUT STAGE DIAGRAM SHADD ADR2-0.D 26 26 26 26 26 26 26 26 FILTER CELL DESCRIPTION 8-bit coefficients are loaded into the C register (CIN7-0 ) and are output as COUT7-0 (the COENB signal enables the COUT7-0 outputs). The path taken by the coefficients varies according to the decimation mode chosen. With no decimation, the coefficients move directly from the C register, bypassing all decimation registers, and are available at the output on the following clock cycle. When decimation is chosen, the coefficient output is delayed by 1, 2, or 3 clock cycles depending on how many decimation registers the coefficients pass through (D1, D2, or D3). The number of decimation registers the coefficients pass through is determined by DCM1-0 . Refer to Table 1 for choosing a decimation mode. CIENB enables the C and D registers for coefficient loading. The registers are loaded on the rising edge of CLK when CIENB is LOW. CIENB is latched and delayed internally which enables the registers for loading one clock cycle after CIENB goes active (loading takes place on the second rising edge of CLK after CIENB goes LOW). Therefore, CIENB must be LOW one clock cycle before the coefficients are placed on the CIN7-0 inputs. The coefficients are held when CIENB is HIGH. DIENB enables the X register for the loading of data. The X register is loaded on the rising edge of CLK when DIENB is LOW. DIENB is latched and delayed internally (loading takes place on the second rising edge of CLK after DIENB goes LOW). Therefore, DIENB must be LOW one clock cycle before the data is placed on the DIN7-0 inputs. The X register is loaded with all zeros when DIENB is HIGH. The output of the C register (C8-0) and X register (X8-0) provide the inputs of the 8 x 8 multiplier. The multiplier is followed by two pipeline registers, D CELL RESULT MUX Q 26 0 18 ZERO MUX SIGN EXTENSION 25-18 17-0 17-0 1 0 26 OUTPUT BUFFER 25-8 26 1 OUTPUT MUX 26 0 D Q SENBL SENBH 2 TRI-STATE BUFFER 26 CLK RESET.D TO ALL REGISTERS TO ALL REGISTERS M REG0 and M REG1. The output of the multiplier is sign extended and is used as one of the inputs to the 26-bit adder. The output of the 26-bit accumulator provides the second input to the adder. Both the accumulator and T register are loaded simultaneously with the output of the adder. The accumulator is loaded with the output of the adder on every clock cycle unless cleared. Clearing the accumulator can be achieved using two methods. The first method, when both RESET and ERASE are LOW, causes all accumulators and all registers in the device to be cleared together. RESET and ERASE are latched and delayed internally causing the clearing to occur on the second clock cycle after RESET and ERASE go active. The second method, when only ERASE is LOW, clears a single accumulator of a selected cell. The cell is selected using the ADR2-0 inputs (decoded to Cell n). ERASE is latched and delayed internally causing the clearing to occur on the second clock cycle after ERASE goes active. Refer to Table 2 for clearing registers and accumulators. Video Imaging Products 3 08/16/2000–LDS.43881-J LF43881 DEVICES INCORPORATED 8 x 8-bit Digital Filter SIGNAL DEFINITIONS Power VCC and GND +5 V power supply. All pins must be connected. Clock TABLE 1. DCM1 0 0 1 1 DECIMATION MODE SELECTION Decimation Function Decimation registers not used One decimation register used (decimation by one-half) Two decimation registers used (decimation by one-third) Three decimation registers used (decimation by one-fourth) AND DCM0 0 1 0 1 TABLE 2. ERASE 0 0 1 1 REGISTER 0 1 0 1 ACCUMULATOR CLEARING CLK — Master Clock The rising edge of CLK strobes all registers. All timing specifications are referenced to the rising edge of CLK. Inputs DIN7-0 — Data Input 8-bit data is latched into the X register of each filter cell simultaneously. The TCS signal selects the appropriate data format type. The DIENB signal enables loading of the data. CIN7-0 — Coefficient Input 8-bit coefficients are latched into the C register of Filter Cell 0. The TCCI signal selects the appropriate coefficient format type. The CIENB signal enables loading of the coefficients. Outputs SUM25-0 — Data Output The 26-bit result from an individual filter cell will appear when ADR2-0 is used to select the filter cell result. SHADD in conjunction with ADR2-0 is used to select the output from the shift-and-add output stage. COUT7-0 — Coefficient Output The 8-bit coefficient output from Filter Cell 7 can be connected to the CIN7-0 coefficient input of the same LF43881 to recirculate the coefficients. COUT7-0 can also be connected to the CIN7-0 of another LF43881 to cascade the devices. The COENB signal enables the output of the coefficients. RESET Clearing Effect All accumulators and all registers are cleared Only the accumulator addressed by ADR2-0 is cleared All registers are cleared (accumulators are not cleared) No clearing occurs, internal state remains the same OUTPUT STAGE DESCRIPTION The 26-bit adder contained in the output stage can add the contents of any filter cell accumulator (selected by ADR2-0) with the 18 most significant bits of the output buffer. The result is stored back into the output buffer. The complete operation takes only one clock cycle. The eight least significant bits of the output buffer are lost. The Zero multiplexer is controlled by the SHADD input signal. This allows selection of either the 18 most significant bits of the output buffer or all zeros for the adder input. When SHADD is LOW, all zeros will be selected. When SHADD is HIGH, the 18 most significant bits of the output buffer are selected enabling the shiftand-add operation. SHADD is latched and delayed internally by one clock cycle. The output multiplexer is also controlled by the SHADD input signal. This allows selection of either a filter cell accumulator, selected by ADR2-0, or the output buffer to be output to the SUM25-0 bus. Only the 26 least significant bits from either a filter cell accumulator or the output buffer are output on SUM25-0. If SHADD is LOW during two consecutive clock cycles (low during the current and previous clock cycle), the output multiplexer selects the contents of a filter cell accumulator addressed by ADR2-0. Otherwise, the output multiplexer selects the contents of the output buffer. If the same address remains on the ADR2-0 inputs for more than one clock cycle, SUM25-0 will not change to reflect any updates to the addressed cell accumulator. Only the result from the first selection of the cell (first clock cycle) will be output. This allows the interface of slow memory devices where the output needs to be active for more than one clock cycle. Normal FIR operation is not affected because ADR2-0 is changed sequentially. NUMBER SYSTEMS Data and coefficients can be represented as either unsigned or two's complement numbers. The TCS and TCCI inputs determine which of the two formats is to be used. All values are represented as 9-bit two's complement numbers internally. The value of the ninth bit is determined by the number system selected. The ninth bit is a sign extended bit when the two's complement mode is chosen. When the unsigned mode is chosen, the ninth bit is zero. Video Imaging Products 4 08/16/2000–LDS.43881-J LF43881 DEVICES INCORPORATED 8 x 8-bit Digital Filter CIENB — Coefficient Input Enable The CIENB input enables the C and D registers of every filter cell. While CIENB is LOW, the C and appropriate D registers are loaded with the coefficient data on the rising edge of CLK. While CIENB is HIGH, the contents of the C and D registers are held and the CLK signal is ignored. By using CIENB in its active state, coefficient data can be shifted from cell to cell. CIENB must be low one clock cycle prior to presenting the coefficient data on the CIN7-0 input since it is latched and delayed internally. COENB — Coefficient Output Enable The COENB input enables the COUT7-0 and TCCO outputs. When COENB is LOW, the outputs are enabled. When COENB is HIGH, the outputs are placed in a high-impedance state. DCM1-0 — Decimation Control The DCM1-0 inputs select the number of decimation registers to use (Table 1). Coefficients are passed from one cell to another at a rate determined by DCM1-0 . When no decimation registers are selected, the coefficients are passed from cell to cell on every rising edge of CLK (no decimation). When one decimation register is selected, the coefficients are passed from cell to cell on every other rising edge of CLK (2:1 decimation). When two decimation registers are selected, the coefficients are passed from cell to cell on every third rising edge of CLK (3:1 decimation) and so on. DCM1-0 is latched and delayed internally. ADR2-0 — Cell Accumulator Select The ADR2-0 inputs select which cell’s accumulator will available at the SUM25-0 output or added to the output stage accumulator. In both cases, ADR2-0 is latched and delayed by one clock cycle. If the same address remains on the ADR2-0 inputs for more than one clock cycle, SUM25-0 will not change if the contents of the accumulator changes. Only the result from the first selection of the cell (first clock cycle) by ADR2-0 will be available. ADR2-0 is also used to select which accumulator to clear when ERASE is LOW. SENBH — MSB Output Enable When SENBH is LOW, SUM25-16 is enabled. When SENBH is HIGH, SUM25-16 is placed in a high-impedance state. SENBL — LSB Output Enable When SENBL is LOW, SUM15-0 is enabled. When SENBL is HIGH, SUM15-0 is placed in a high-impedance state. RESET — Register Reset Control When RESET is LOW, all registers are cleared simultaneously except the cell accumulators. RESET can be used with ERASE to clear all cell accumulators. RESET is latched and delayed internally. Refer to Table 2. ERASE — Accumulator Erase Control When ERASE is LOW, the cell accumulator specified by ADR2-0 is cleared. When RESET is LOW in conjunction with ERASE, all cell accumulators are cleared. Refer to Table 2. Controls TCS — Data Format Control The TCS input determines the interpretation of the input data. When TCS is HIGH, two’s complement arithmetic is used. When TCS is LOW, unsigned arithmetic is used. TCCI — Coefficient Input Format Control The TCCI input determines the interpretation of the coefficients. When TCCI is HIGH, two’s complement arithmetic is used. When TCCI is LOW, unsigned arithmetic is used. TCCO — Coefficient Output Format The TCCO output shows the format of the COUT7-0 coefficient output. TCCO follows the TCCI input. When cascading multiple LF43881s, the TCCO output of one device should be connected to the TCCI input of another device. The COENB signal enables TCCO. DIENB — Data Input Enable The DIENB input enables the X register of every filter cell. While DIENB is LOW, the X registers are loaded with the data present at the DIN7-0 inputs on the rising edge of CLK. While DIENB is HIGH, all bits of DIN7-0 are forced to zero and a rising edge of CLK will load the X register of every filter cell with all zeros. DIENB must be low one clock cycle prior to presenting the input data on the DIN7-0 input since it is latched and delayed internally. Video Imaging Products 5 08/16/2000–LDS.43881-J LF43881 DEVICES INCORPORATED 8 x 8-bit Digital Filter MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ............................................................................... –0.5 V to V CC + 0.5 V Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0°C to +70°C –55°C to +125°C Supply Voltage 4.75 V ≤ VCC ≤ 5.25 V 4.50 V ≤ VCC ≤ 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol VOH VOL VIH VIL IIX IOZ ICC1 ICC2 CIN COUT Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent Input Capacitance Output Capacitance (Note 3) Test Condition VCC = Min., IOH = –400 µA VCC = Min., IOL = 2.0 mA Min 2.6 Typ Max Unit V 0.4 2.0 0.0 VCC 0.8 ±10 ±10 160 750 10 10 V V V µA µA mA µA pF pF Ground ≤ VIN ≤ VCC (Note 12) (Note 12) (Notes 5, 6) (Note 7) TA = 25°C, f = 1 MHz TA = 25°C, f = 1 MHz Video Imaging Products 6 08/16/2000–LDS.43881-J 432109876543210987654321 432109876543210987654321 432109876543210987654321 *DISCONTINUED SPEED GRADE Symbol Symbol †includes TCCO, SUM25-0, and COUT7-0. ‡includes SENBL, SENBH, and COENB. 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 Min DEVICES INCORPORATED COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) SWITCHING CHARACTERISTICS LF43881– 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 Min 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 Min SWITCHING WAVEFORMS MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) tDIS tENA tODS tODC tH tS tPW tCYC tDIS tENA tODS tODC tH tS tPW tCYC OUTPUT ENABLES‡ CONTROLS* OUTPUTS† Parameter Parameter Three-State Output Disable Delay (Note 11) Three-State Output Enable Delay (Note 11) Sum Output Delay Coefficient Output Delay Input Hold Time Input Setup Time Clock Pulse Width Cycle Time Three-State Output Disable Delay (Note 11) Three-State Output Enable Delay (Note 11) Sum Output Delay Coefficient Output Delay Input Hold Time Input Setup Time Clock Pulse Width Cycle Time DIN7-0 CIN7-0 CLK *includes DIENB, CIENB, ERASE, RESET, TCS, TCCI, SHADD, DCM1-0, and ADR2-0. tS tH tODC tODS 7 50 16 20 0 50* Max 27 20 20 24 tDIS tPW Min 50 39 20 14 20 16 0 0 50* 40 Video Imaging Products Max Max 25 31 20 20 24 15 15 20 HIGH IMPEDANCE 8 x 8-bit Digital Filter tPW Min LF43881– 40* 39 33 17 13 16 13 0 0 tENA 33* Max Max 21 25 20 15 15 18 15 15 08/16/2000–LDS.43881-J LF43881 Min Min 33 25 13 10 13 10 0 0 33* 25* Max Max 18 21 15 15 18 16 12 12 LF43881 DEVICES INCORPORATED 8 x 8-bit Digital Filter NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of IOH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a minN = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with all outputs changing every cycle and no load, at a 20 MHz clock rate. 7. Tested with all inputs within 0.1 V of VCC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. imum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT DUT S1 IOL CL IOH VTH FIGURE B. THRESHOLD LEVELS tENA OE Z 0 1.5 V 1.5 V 1.5 V tDIS 3.5V Vth VOL* 0.2 V 0 1 Z Z 1.5 V VOH* 0.2 V Z 1 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA Video Imaging Products 8 08/16/2000–LDS.43881-J LF43881 DEVICES INCORPORATED 8 x 8-bit Digital Filter ORDERING INFORMATION 84-pin GND SUM24 DCM1 SUM25 SENBH VCC ADR0 ADR1 GND DCM0 ADR2 CLK SHADD COUT0 COUT1 GND COUT2 COUT3 COUT4 COUT5 VCC SUM23 SUM22 VCC SUM21 SUM20 SUM19 SUM18 GND SUM17 SUM16 VCC SUM15 SUM14 SUM13 SUM12 GND SUM11 SUM10 SUM9 SUM8 SUM7 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 74 13 73 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 72 71 70 69 68 67 66 Top View 65 64 63 62 61 60 59 58 57 56 55 32 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 COUT6 COUT7 GND TCCO COENB VCC ERASE RESET DIENB TCS DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 CIENB TCCI VCC Speed 0°C to +70°C — COMMERCIAL SCREENING 40 ns LF43881JC40 SUM6 GND SUM5 SUM4 VCC SUM3 SUM2 SUM1 SUM0 GND SENBL CIN0 CIN1 VCC CIN2 CIN3 CIN4 CIN5 GND CIN6 CIN7 Plastic J-Lead Chip Carrier (J3) Video Imaging Products 9 08/16/2000–LDS.43881-J 210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 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210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 DEVICES INCORPORATED Speed 0°C to +70°C — COMMERCIAL SCREENING ORDERING INFORMATION 100-pin DCM1 SUM24 GND GND SUM23 SUM22 VCC VCC SUM21 SUM20 SUM19 SUM18 GND GND SUM17 SUM16 VCC VCC SUM15 SUM14 SUM13 SUM12 GND SUM11 SUM10 SUM9 SUM8 SUM7 NC SUM6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Discontinued Package Plastic Quad Flatpack (Q2) 10 GND GND SUM5 SUM4 VCC SUM3 SUM2 SUM1 SUM0 GND GND SENBL CIN0 CIN1 VCC CIN2 CIN3 CIN4 CIN5 GND 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Top View 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 COUT4 COUT5 VCC VCC COUT6 COUT7 GND GND TCCO COENB VCC VCC ERASE RESET DIENB TCS DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 CIENB TCCI VCC CIN7 CIN6 GND Video Imaging Products 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 SUM25 SENBH VCC VCC ADR0 ADR1 GND GND DCM0 ADR2 CLK SHADD VCC VCC COUT0 COUT1 GND GND COUT2 COUT3 8 x 8-bit Digital Filter 08/16/2000–LDS.43881-J LF43881 121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 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INCORPORATED Speed –55°C to +125°C — MIL-STD-883 COMPLIANT –55°C to +125°C — COMMERCIAL SCREENING 0°C to +70°C — COMMERCIAL SCREENING ORDERING INFORMATION 84-pin G H D C K E B A F L J SENBH SUM24 GND VCC SUM19 GND SUM15 SUM12 SUM10 SUM8 SUM6 COUT1 GND COUT2 COUT3 COUT4 COUT5 COUT6 DCM1 SUM23 SUM22 SUM21 SUM18 SUM14 VCC SUM13 GND SUM11 SUM9 GND COUT0 SHADD GND COENB VCC RESET DIN7 DIN6 DIN3 DIN0 TCCI VCC GND ADR1 ADR0 ADR2 DCM0 CLK VCC SUM25 VCC COUT7 TCCO ERASE TCS DIN1 DIN2 CIENB CIN7 CIN6 CIN4 1 2 3 4 Discontinued Package Ceramic Pin Grid Array (G3) (i.e., Component Side Pinout) SUM20 SUM17 SUM16 DIENB DIN5 DIN4 5 Through Package 11 Top View 6 7 8 CIN1 CIN0 SENBL SUM1 SUM3 SUM2 SUM0 VCC GND 9 CIN2 VCC CIN5 CIN3 SUM7 GND SUM5 SUM4 Video Imaging Products 10 8 x 8-bit Digital Filter 11 08/16/2000–LDS.43881-J LF43881