LF48908

LF48908 DEVICES INCORPORATED Two Dimensional Convolver LF48908 DEVICES INCORPORATED Two Dimensional Convolver DESCRIPTION The LF48908 is a high-speed two dimensional convolver that implements a 3 x 3 kernel convolution at real-time video rates. Programmable row buffers are located on-chip, eliminating the need for external data storage. Each row buffer can store up to 1024 pixels. Two internal register banks are provided allowing two separate sets of filter coefficients to be stored simultaneously. Adaptive filter operations are possible when both register banks are used. An on-chip ALU is provided, allowing real-time arithmetic and logical pixel point operations to be performed on the image data. The 3 x 3 convolver comprises nine 8 x 8-bit multipliers, various pipeline registers, and summers. A complete sum-of-products operation is performed every clock cycle. The FRAME signal resets all data registers without affecting the control and coefficient registers. Pixel and coefficient input data are both 8-bits and can be either signed or unsigned integers. Image data should be in a raster scan non-interlaced format. The LF48908 can internally store images as wide as 1024 pixels for the 3 x 3 convolution. By using external row buffers and multiple LF48908s, longer pixel rows can be used and convolutions with larger kernel sizes can be performed. Output data is 20-bits and this guarantees no overflow for kernel sizes up to 4 x 4. A separate cascade input is used as the data input for summing results from multiple LF48908s. It can also function as the data input path when external line buffers are used. FEATURES u 40 MHz Data and Computation Rate u Nine Multiplier Array with 8-bit Data and 8-bit Coefficient Inputs u Separate Cascade Input and Output Ports u On-board Programmable Row Buffers u Two Coefficient Mask Registers u On-board 8-bit ALU u Two’s Complement or Unsigned Operands u Replaces Harris HSP48908 u DECC SMD No. 5962-93007 u Package Styles Available: • 84-pin Plastic LCC, J-Lead • 100-pin Plastic Quad Flatpack 1 2 3 4 5 6 7 8 9 FIGURE 1. LF48908 BLOCK DIAGRAM 16 CASI15-0 8 DIN7-0 8 CIN9-0 ALU 3 ROW BUFFERS 10 11 A2-0 LD CS 3x3 CONVOLVER 20 DOUT19-0 8 CASO7-0 CLK HOLD EALU RESET FRAME OE CONTROL LOGIC Video Imaging Products 1 08/9/2000–LDS.48908-J LF48908 DEVICES INCORPORATED Two Dimensional Convolver FIGURE 2. LF48908 FUNCTIONAL BLOCK DIAGRAM ALU DIN7-0 1-4 8 7-0 8 ROW BUFFER 8 ROW BUFFER 15-8 8 8 CASO7-0 CIN9-0 7-0 8 2:1 ALU REGISTER 10 2:1 I F C 3 A2-0 LD CS H E B CONTROL LOGIC G CLK HOLD EALU RESET FRAME OE D A 16 CASI15-0 SHIFT 20 20 0 20 DOUT19-0 NOTE: NUMBERS IN REGISTER INDICATE NUMBER OF PIPELINE DELAYS. 2:1 Video Imaging Products 2 08/9/2000–LDS.48908-J LF48908 DEVICES INCORPORATED Two Dimensional Convolver CASO7-0 — Cascade Output The data presented on CASO7-0 is the internal ALU output delayed by twice the programmed internal row buffer length. Controls A2-0 — Control Logic Address Lines A2-0 determines which Control Logic Register will receive the CIN9-0 data. CS — Chip Select When CS is LOW, data can be loaded into the Control Logic Registers. When CS is HIGH, data can not be loaded and the register contents will not be changed. LD — Load Strobe If CS and LD are LOW, the data present on CIN9-0 will be latched into the Control Logic Register addressed by A2-0 on the rising edge of LD. FUNCTIONAL DESCRIPTION The LF48908, a two-dimensional convolver, executes convolutions using internal row buffers to reduce design complexity and board space requirements. 8-bit image data, in raster scan, non-interlace format, is convolved with one of two internal, 3 x 3 userprogramable filter kernels. Two 1024 x 8bit row buffers provide the data delay needed to perform two-dimensional convolutions on a single chip. The result output of 20-bits allows for word growth during the convolution operation. The input data path (DIN7-0) provides access to an 8-bit ALU. This allows point operations to be performed on the incoming data stream before reaching the row buffers and the convolver. The length of these buffers is programmable for use in various video formats without the need for additional external delay. This device is configured by loading the coefficent data (filter kernels) and row buffer length through the coefficent data path (CIN7-0). Internal registers are addressed using the A2-0 address lines. Chip Select (CS) and Load Strobe (LD) complete the configuration interface which may be controlled by standard microprocessors without additional external logic. SIGNAL DEFINITIONS Power VCC and GND +5 V power supply. All pins must be connected. Clock CLK — Master Clock The rising edge of CLK strobes all enabled registers except for the Control Logic Registers. Inputs DIN7-0 — Pixel Data Input DIN7-0 is the 8-bit registered pixel data input port. Data is latched on the rising edge of CLK. CIN9-0 — Coefficient and Control Logic Register Input CIN7-0 is used to load the Coefficient Registers or can be used to provide a second operand input to the ALU. CIN8-0 is used to load the Initialization Register. CIN9-0 is used to load the ALU Microcode and Row Buffer Length Registers. The Control Register Address Lines, A2-0, determine which register will receive the CIN data. The CIN data is loaded into the addressed register by using the CS and LD control inputs. CASI15-0 — Cascade Input The cascade input is used when multiple LF48908s are cascaded together or when external row buffers are needed. This allows convolutions of larger kernels or longer row sizes. Outputs DOUT19-0 — Data Output DOUT19-0 is the 20-bit registered data output port. 1 2 3 4 5 6 7 8 9 10 11 RESET — Reset Control When RESET is LOW, all internal circuitry is reset, all outputs are forced LOW, all Control Logic Registers are loaded with their default values (which is 0 for each one except the ALU Microcode Register which has a default value of “0000011000”), and all other internal registers are loaded with a “0”. FRAME — New Frame Input Control When asserted, FRAME signals the start of a new frame. When FRAME is LOW, all internal circuitry is reset except for the ALU Microcode, Row Length, Initialization, Coefficient, and ALU Registers. EALU — Enable ALU Register Input When HIGH, data on CIN7-0 is latched into the ALU Register on the next rising edge of CLK. When LOW, data on CIN7-0 will not be latched into the ALU Register and the register contents will not be changed. HOLD — Hold Control The HOLD input is used to disable CLK from all of the internal circuitry. HOLD is latched on the rising edge of CLK and takes effect on the next rising edge of CLK. When HOLD is HIGH, CLK will have no effect on the LF48908 and all internal data will remain unchanged. OE — Output Enable When OE is LOW, DOUT19-0 is enabled for output. When OE is HIGH, DOUT19-0 is placed in a highimpedance state. Video Imaging Products 3 08/9/2000–LDS.48908-J LF48908 DEVICES INCORPORATED Two Dimensional Convolver data path, while the “B” operand is taken from the ALU Register. The ALU Register is loaded using CIN7-0 and EALU. With EALU HIGH, data from CIN7-0 is loaded into the ALU Register on the rising edge of CLK. With EALU LOW, the data is held in the ALU Register. Since CIN7-0 is also used to load the Control Logic Registers, it is possible to overwrite data in those registers if CS and LD are active when loading the ALU Register. Therefore, special care must be taken to ensure that CS and LD are not active when writing to the ALU Register. Programmable Row Buffers The two internal row buffers provide the delay needed to perform the twodimensional convolution. The row buffers function like 8-bit serial shift registers with a user-programmable delay from 1 to 1024 stages (it is possible to select delay stages of 1 or 2, but this leads to meaningless results for a 3 x 3 kernel convolution). The row buffer length is set via the Row Length Register (see Row Length Register Section). The row buffers are connected in series to provide the proper pixel information to the multiplier array. The Cascade Output (CASO7-0) provides a 2X row delay of the input data allowing for cascading of LF48908s to handle larger frames and/or kernel sizes. If more than 1024 delay stages are needed, it is possible to use external row buffers and bypass the internal row buffers. Bit 0 of the Initialization Register determines if internal or external row buffers are used. If Bit 0 is a “0”, the internal row buffers are used. If Bit 0 is a “1”, the internal row buffers are bypassed and external row buffers may be used. 3 x 3 Multiplier Array The multiplier array comprises nine 8 x 8-bit multipliers. The active Coefficient Register supplies the coefficents to each of the multipliers, while the pixel data comes from the data input path and row buffers. The array forms a sum-of-products result as defined by the equation listed in Figure 3. CONTROL LOGIC Four sets of registers, the ALU Microcode, Row Length, Initialization, and Coefficient, define the Control Logic section. These registers are updated The filtered image data is output on the Data Output bus (DOUT19-0). This bus is registered with three-state drivers to facilatate use on a standard microprocessor system bus. Data Input Image data is input to the 3 x 3 convolver using DIN7-0. Data present on DIN7-0 is latched into a programmable pipeline delay on the rising edge of CLK. The programmable pipeline delay (1 to 4 clock cycles) allows for synchronization of input data when multiple LF48908s are cascaded together to perform larger convolutions. This delay is programed via the Initialization Register (see Table 3). The image data format, unsigned or two’s complement, is also controlled by this register. Coefficient data is input to the 3 x 3 convolver using either of two Coefficient Registers (CREG0 or CREG1). The Coefficient Registers are loaded through CIN7-0 using the A2-0, CS, and LD controls. The coefficient data format, unsigned or two’s complement, is determined by the Initialization Register. Arithmetic Logic Unit The input data path ALU with shifter allows pixel point operations to be performed on the incoming image. These operations include arithmetic functions, logical masking, and left/ right shifts. The 10-bit ALU Microcode Register controls the various operations. The three upper bits control the shift amount and direction while the seven lower bits determine the arithmetic or logical operation. The shift operation is performed on the output of the ALU. This shift operation is independent of the arithmetic or logical operation of the ALU. Tables 1 and 2 show the operations of the ALU Microcode Register. The “A” operand comes from the DIN input FIGURE 3. MULTIPLIER ARRAY OUTPUT FILTER KERNEL A D G B E H C F I PIXEL INPUT DATA P1 P4 P7 P2 P5 P8 P3 P6 P9 MULTIPLIER ARRAY OUTPUT = A(P1) + B(P2) + C(P3) + D(P4) + E(P5) + F(P6) + G(P7) + H(P8) + I(P9) Video Imaging Products 4 08/9/2000–LDS.48908-J LF48908 DEVICES INCORPORATED Two Dimensional Convolver FIGURE 4. LF48908 CONTROL LOGIC BLOCK DIAGRAM ENCR1 3 A2-0 LD CS ADDRESS DECODE ENCR0 CAS CR1 CR0 LMC EOR 1 2 10 ALU MICROCODE 10 CIN9-0 LMC ALU MICROCODE REGISTER 3 10 EOR 9 INITIALIZATION REGISTER ROW LENGTH REGISTER ROW LENGTH 8-0 CAS 9 INITIALIZATION DATA 4 5 C0 OE OE COEFFICIENT REGISTER 0 7-0 CR0 8 I0 OE H0 OE G0 OE F0 OE E0 OE D0 B0 OE A0 OE 8 I ENCR1 ENCR0 SQ RQ 8 8 H 8 G 8 8 8 8 8 6 7 A OE F E D C B 7-0 CR1 8 OE OE OE OE OE OE OE OE 8 9 I1 H1 G1 F1 E1 D1 C1 B1 A1 COEFFICIENT REGISTER 1 through the CIN bus using A2-0, CS, and LD (see Figure 4). All the Control Logic Registers are set to their default values when RESET is active. FRAME does not affect the values in these registers. ALU Microcode Register Operation of the ALU and shifter are determined by the value stored in the ALU Microcode Register. This 10-bit instruction word is divided into two fields. The lower seven bits define the arithmetic and logical operations of the ALU. The upper three bits specify shift distance and direction. Tables 1 and 2 detail the various instruction words. This register is loaded through CIN9-0 using the A2-0, CS, and LD controls. Also see Arithmetic Logic Unit section. Row Length Register The value stored in the Row Length Register determines the number of delay stages for each row buffer. The number of delay stages should be set equal to the row length of the input image. The Row Length Register may be loaded with the values 0 through 1023 (0 represents 1024 delay stages). It is possible to program the row buffers to have 1 or 2 delay stages, but this will lead to meaningless results for a 3 x 3 convolution. This register is loaded through CIN9-0 using the A2-0, CS, and LD controls. Once the Row Length Register has been loaded, a new value can not be loaded until the LF48908 has been reset. This is done by asserting RESET. After RESET goes HIGH, the Row Length Register must be loaded within 1024 CLK cycles. If the Row Length Register is not loaded within 1024 CLK cycles, the register will automatically be loaded with a “0”. Initialization Register The Initialization Register configures various functions of the device including: input data delay, input data format, coefficent data format, output rounding, cascade mode, and cascade input shift (see Table 3). This register is loaded through CIN8-0 using the A2-0, CS, and LD controls. Coefficient Registers - CREG0, CREG1 The Coefficient Registers are used to store the filter coefficients for the multiplier array. Each Coefficient 10 11 Video Imaging Products 5 08/9/2000–LDS.48908-J LF48908 DEVICES INCORPORATED Two Dimensional Convolver TABLE 2. ALU LOGICAL AND ARITHMETIC OPERATIONS ALU MICROCODE REGISTER REGISTER BIT TABLE 1. ALU SHIFT OPERATIONS ALU MICROCODE REGISTER REGISTER BIT 9 0 0 0 0 1 1 1 1 8 0 0 1 1 0 0 1 1 7 0 1 0 1 0 1 0 1 OPERATION No Shift (Default) Shift Right 1 Shift Right 2 Shift Right 3 Shift Left 1 Shift Left 2 Shift Left 3 Not Valid 6 0 1 0 0 1 1 0 1 1 5 0 1 0 1 1 0 1 0 0 0 0 1 1 0 1 1 0 1 0 4 0 1 1 0 0 1 1 0 0 0 1 0 1 1 0 1 0 1 0 3 0 1 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 1 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 OPERATION Logical (00000000) Logical (11111111) Logical (A) (Default) Logical (B) Logical (A) Logical (B) Arithmetic (A + B) Arithmetic (A – B) Arithmetic (B – A) Logical (A AND B) Logical (A AND B) Logical (A AND B) Logical (A OR B) Logical (A OR B) Logical (A OR B) Logical (A NAND B) Logical (A NOR B) Logical (A XOR B) Logical (A XNOR B) Register can hold nine 8-bit values. This allows two different 3 x 3 filter kernels to be stored simultaneously on the LF48908. The outputs of CREG0 and CREG1 are connected to the coefficient inputs of the multiplier array (A through I). The register used to supply the coefficient data is determined by the address written to the Address Decoder. If a “101” is written to the Address Decoder, CREG0 will provide the coefficient data. If a “110” is written to the Address Decoder, CREG1 will be used. It is possible to switch between the two Coefficient Registers in real time. This facilitates adaptive filtering operations. It is important to remember to meet the tLCS timing specification when switching the Coefficient Registers. When a Coefficient Register is selected to supply data to the multiplier array (one of the registers is always selected), all of its outputs are enabled simultaneously. When RESET is asserted, CREG0 is the default register selected to supply the coefficient data. CREG0 and CREG1 are loaded through CIN7-0 using the A2-0, CS, and LD controls. The nine coefficient values are presented on CIN7-0 one by one, in order from A to I. As each value is placed on CIN7-0, it is latched into the selected Coefficient Register using CS and LD. The register to be 0 0 0 0 1 1 1 1 0 1 loaded is determined by the data on A2-0 during the load operation. If CREG0 is to be loaded, “010” must be placed on A2-0 during the load operation. If CREG1 is to be loaded, “011” must be placed on A2-0. If desired, the Coefficient Register that is not being used to send data to the multiplier array can be loaded with coefficient data while the LF48908 is in active operation. Address Decoder The Address Decoder is used to load the Control Logic Registers and to determine which Coefficient Register sends data to the multiplier array. To load a Control Logic Register, the address of the register must be placed on A2-0, the data to be written must be placed on the CIN bus, and CS and LD must be asserted. The data is latched into the addressed register when LD goes HIGH. To select a Coefficient Register (CREG0 or CREG1) to send data to the multiplier array, the appropriate address must be placed on A2-0, and CS and LD must be asserted. When LD goes HIGH, the addressed register will begin supplying coefficient data to the multiplier array. Table 4 lists all of the register addresses. The Control Logic Registers can be modified during active operation of the LF48908. If this is done, it is very important to meet the tLCS timing specification. This is to ensure that the outputs of the Control Logic Registers have enough time to change before the next rising edge of CLK. If tLCS is not met, unexpected results may occur on DOUT19-0 for one clock cycle. There are two situations in which tLCS may Video Imaging Products 6 08/9/2000–LDS.48908-J LF48908 DEVICES INCORPORATED Two Dimensional Convolver TABLE 3. INITIALIZATION REGISTER BIT 0 0 FUNCTION CASCADE MODE Multiplier input from internal row buffers Multiplier input from external buffers 1 0 1 0 1 3 0 1 4 0 1 6 0 0 1 1 8 0 0 1 1 5 0 1 0 1 7 0 1 0 1 INPUT DATA DELAY No data delay registers used One data delay register used Two data delay registers used Three data delay registers used INPUT DATA FORMAT Unsigned integer format Two’s complement format COEFFICIENT DATA FORMAT Unsigned integer format Two’s complement format OUTPUT ROUNDING No rounding Round to 16 bits (i.e. DOUT19-4) Round to 8 bits (i.e. DOUT19-12) Not valid CASI15-0 INPUT SHIFT No shift Shift CASI15-0 left two Shift CASI15-0 left four Shift CASI15-0 left eight be ignored. If the LF48908 is not in active operation or if the innactive Coefficient Register is being written to during active operation. Cascade Operation The Cascade Input lines (CASI15-0) and Cascade Output lines (CASO7-0) are used to allow convolutions of kernel sizes larger than 3 x 3. The Cascade Input lines are also used to allow convolutions on row lengths longer than 1024 pixels. The Cascade Mode Bit (Bit 0) of the Initialization Register determines the function of the Cascade Input lines. If the Cascade Mode Bit is a “0”, then the Cascade Input lines are to be used to cascade multiple LF48908s together to perform convolutions of larger kernel sizes. CASI15-0 will be left shifted (by an amount determined by bits 7 and 8 of the Initialization Register) and then added to DOUT19-0. Cascading is accomplished by connecting CASO7-0 and DOUT19-0 of one LF48908 to DIN7-0 and CASI15-0 respectively of another LF48908. If the Cascade Mode Bit is a “1”, then the Cascade Input lines are to be used with external row buffers to allow for longer row lengths. In this mode, the Cascade Input lines are split into two 8-bit data busses (CASI15-8 and CASI7-0) which are fed directly into the multiplier array. TABLE 4. A2-0 000 001 010 011 100 101 110 111 CONTROL LOGIC ADDRESS MAP FUNCTION 1 2 0 0 1 1 Load Row Buffer Length Register Load ALU Microcode Register Load Coefficient Register 0 Load Coefficient Register 1 Load Initialization Register Select Coefficient Register 0 for Internal Processing Select Coefficient Register 1 for Internal Processing No Operation 1 2 3 4 5 6 7 8 9 10 11 Video Imaging Products 7 08/9/2000–LDS.48908-J LF48908 DEVICES INCORPORATED Two Dimensional Convolver MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ............................................................................... –0.5 V to V CC + 0.5 V Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0°C to +70°C –55°C to +125°C Supply Voltage 4.75 V ≤ VCC ≤ 5.25 V 4.50 V ≤ VCC ≤ 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol VOH VOL VIH VIL IIX IOZ ICC1 ICC2 CIN COUT Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent Input Capacitance Output Capacitance (Note 3) Test Condition VCC = Min., IOH = –400 µA VCC = Min., IOL = 2.0 mA Min 2.8 Typ Max Unit V 0.4 2.0 0.0 VCC 0.8 ±10 ±10 110 500 10 12 V V V µA µA mA µA pF pF Ground ≤ VIN ≤ VCC (Note 12) Ground ≤ VOUT ≤ VCC (Note 12) (Notes 5, 6) (Note 7) TA = 25°C, f = 1 MHz TA = 25°C, f = 1 MHz Video Imaging Products 8 08/9/2000–LDS.48908-J LF48908 DEVICES INCORPORATED Two Dimensional Convolver SWITCHING CHARACTERISTICS COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) 50 Symbol Parameter Min Max LF48908– 31 Min Max Min 25 Max 1 2 3 4 tCYC tPWH tPWL tDS tDH tCS tCH tES tEH tD tENA tDIS Cycle Time Clock Pulse Width High Clock Pulse Width Low Data Input Setup Time Data Input Hold Time CIN7-0 Setup Time CIN7-0 Hold Time EALU Setup Time EALU Hold Time Output Delay Three-State Output Enable Delay (Note 11) Three-State Output Disable Delay (Note 11) 50 20 20 14 0 16 0 14 0 22 22 32 31 12 13 13 0 14 0 12 0 16 16 28 25 8 8 8 0 10 0 10 0 15 15 8 5 6 7 SWITCHING WAVEFORMS: CONVOLVER DATA I/O tCYC tPWL CLK tDS DIN7-0 CASI15-0 tCS CIN7-0 (ALU REG DATA) tES EALU tEH tCH tDH tPWH 8 9 10 tDIS tENA OE tD CASO7-0 tD DOUT19-0 HIGH IMPEDANCE 11 Video Imaging Products 9 08/9/2000–LDS.48908-J 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 *DISCONTINUED SPEED GRADE Symbol 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 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54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 54321098765432121098765432109876543210987654321 Min DEVICES INCORPORATED MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) SWITCHING WAVEFORMS: tDIS tENA tD tEH tES tCH tCS tDH tDS tPWL tPWH tCYC CIN7-0 (ALU REG DATA) DOUT19-0 Parameter Three-State Output Disable Delay (Note 11) Three-State Output Enable Delay (Note 11) Output Delay EALU Hold Time EALU Setup Time CIN7-0 Hold Time CIN7-0 Setup Time Data Input Hold Time Data Input Setup Time Clock Pulse Width Low Clock Pulse Width High Cycle Time CASO7-0 DIN7-0 CASI15-0 EALU CLK OE CONVOLVER DATA I/O tPWL tCS tDS tES tCYC tCH tDH tEH tD tD tPWH 10 20 20 20 17 50 17 0 0 0 50* tDIS Max Two Dimensional Convolver 28 40 28 Video Imaging Products Min 15 15 17 16 37 15 LF48908– 37* 0 0 0 HIGH IMPEDANCE Max 19 35 19 tENA 08/9/2000–LDS.48908-J Min 10 25 10 8 8 8 0 0 0 LF48908 25* Max 15 15 8 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 *DISCONTINUED SPEED GRADE Symbol Symbol 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 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4321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432 Min DEVICES INCORPORATED SWITCHING WAVEFORMS: CONFIGURATION DATA MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) tCSH tCSS tAH tAS tCDH tCDS tLCS tLPW tCSH tCSS tAH tAS tCDH tCDS tLCS tLPW CIN9-0 CLK A2-0 CS LD *applies only when the LF48908 is in active operation. Parameter Parameter CS Hold Time CS Setup Time Address Hold Time Address Setup Time Configuration Data Hold Time Configuration Data Setup Time LD Setup Time (Applies only during active operation) LD Pulse Width CS Hold Time CS Setup Time Address Hold Time Address Setup Time Configuration Data Hold Time Configuration Data Setup Time LD Setup Time (Applies only during active operation) LD Pulse Width tCSS tCDS tAS tLPW tCDH 11 tAH tCSH tLCS* Min 15 13 20 20 20 16 37 30 0 0 0 0 0 0 0 0 50* 50 Max Max Two Dimensional Convolver Video Imaging Products Min Min 15 13 15 12 17 14 30 25 LF48908– 37* LF48908– 31 0 0 0 0 0 0 0 0 Max Max 08/9/2000–LDS.48908-J Min Min 10 10 10 10 15 15 0 0 8 8 0 0 0 0 0 0 LF48908 25* 25 Max Max 11 10 9 8 7 6 5 4 3 2 1 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 *DISCONTINUED SPEED GRADE Symbol Symbol 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 Min DEVICES INCORPORATED COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) SWITCHING WAVEFORMS: CONTROL SIGNALS MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) tRPW tFS tFPW tHH tHS tRPW tFS tFPW tHH tHS FRAME RESET HOLD CLK Parameter RESET Pulse Width FRAME Setup Time FRAME Pulse Width HOLD Hold Time HOLD Setup Time Parameter RESET Pulse Width FRAME Setup Time FRAME Pulse Width HOLD Hold Time HOLD Setup Time tHS tRPW tHH tHS 12 tFPW Min 50 12 25 50 50 14 30 50 1 2 50* 50 Max Max Two Dimensional Convolver Video Imaging Products tFS Min Min 31 11 21 31 37 13 25 37 LF48908– 31 LF48908– 37* 1 2 Max Max 08/9/2000–LDS.48908-J Min Min 20 20 8 0 9 8 0 9 8 8 LF48908 25* 25 Max Max LF48908 DEVICES INCORPORATED Two Dimensional Convolver NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of I OH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. where 4 10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter6. Tested with all outputs changing ev- nal system must supply at least that ery cycle and no load, at a 20 MHz clock much time to meet the worst-case requirements of all parts. Responses from rate. the internal circuitry are specified from 7. Tested with all inputs within 0.1 V of the point of view of the device. Output VCC or Ground, no load. delay, for example, is specified as a 8. These parameters are guaranteed maximum since worst-case operation of any device always provides data within but not 100% tested. that time. N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. 1 2 3 4 5 FIGURE A. OUTPUT LOADING CIRCUIT DUT S1 IOL CL IOH VTH 6 7 8 9 10 11 FIGURE B. THRESHOLD LEVELS tENA OE Z 0 1.5 V 1.5 V 1.5 V tDIS 3.5V Vth VOL* 0.2 V 0 1 Z Z 1.5 V VOH* 0.2 V Z 1 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA Video Imaging Products 13 08/9/2000–LDS.48908-J LF48908 DEVICES INCORPORATED Two Dimensional Convolver ORDERING INFORMATION 84-pin CIN2 CIN1 CIN0 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 VCC OE GND CASO0 CASO1 CASO2 CASO3 CASO4 GND CASO5 CIN3 CIN4 CIN5 CIN6 CIN7 CIN8 CIN9 GND CLK VCC HOLD LD CS A2 A1 A0 EALU CASI15 CASI14 CASI13 CASI12 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 74 13 73 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 72 71 70 69 68 67 66 Top View 65 64 63 62 61 60 59 58 57 56 55 32 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 CASO6 CASO7 DOUT0 DOUT1 DOUT2 GND DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 VCC DOUT8 GND DOUT9 DOUT10 DOUT11 DOUT12 DOUT13 DOUT14 GND Speed 0°C to +70°C — COMMERCIAL SCREENING 50 ns 31 ns 25 ns LF48908JC50 LF48908JC31 LF48908JC25 –40°C to +85°C — COMMERCIAL SCREENING CASI11 CASI10 CASI9 CASI8 CASI7 CASI6 CASI5 CASI4 CASI3 VCC CASI2 CASI1 CASI0 FRAME RESET GND DOUT19 DOUT18 DOUT17 DOUT16 DOUT15 Plastic J-Lead Chip Carrier (J3) Video Imaging Products 14 08/9/2000–LDS.48908-J LF48908 DEVICES INCORPORATED Two Dimensional Convolver ORDERING INFORMATION 100-pin CIN0 DIN7 DIN6 DIN5 DIN6 DIN3 DIN2 DIN1 DIN0 VCC VCC OE GND GND CASO0 CASO1 CASO2 CASO3 CASO4 GND 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CIN1 CIN2 NC NC CIN3 CIN4 CIN5 CIN6 CIN7 CIN8 CIN9 GND GND CLK VCC VCC HOLD LD CS A2 A1 A0 EALU CASI15 CASI14 CASI13 CASI12 NC NC CASI11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Top View 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 GND CASO5 NC CASO6 CASO7 DOUT0 DOUT1 DOUT2 GND GND DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 VCC VCC DOUT8 GND GND DOUT9 DOUT10 DOUT11 DOUT12 DOUT13 DOUT14 GND GND DOUT15 DOUT16 1 2 3 4 5 6 7 8 9 10 11 Speed 0°C to +70°C — COMMERCIAL SCREENING 31 ns 25 ns LF48908QC31 LF48908QC25 –40°C to +85°C — COMMERCIAL SCREENING CASI10 CASI9 CASI8 CASI7 CASI6 CASI5 CASI4 CASI3 VCC VCC CASI2 CASI1 CASI0 FRAME RESET GND GND DOUT19 DOUT18 DOUT17 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Plastic Quad Flatpack (Q2) Video Imaging Products 15 08/9/2000–LDS.48908-J 121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 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DOUT5 Two Dimensional Convolver VCC GND DOUT8 9 DOUT14 DOUT12 DOUT11 DOUT10 CASO7 DOUT1 DOUT2 GND 10 Video Imaging Products 11 08/9/2000–LDS.48908-J LF48908