LMS12
DEVICES INCORPORATED
12-bit Cascadable Multiplier-Summer
LMS12
DEVICES INCORPORATED
12-bit Cascadable Multiplier-Summer
DESCRIPTION
The LMS12 is a high-speed 12 x 12-bit combinatorial multiplier integrated with a 26-bit adder in a single 84-pin package. It is an ideal building block for the implementation of very highspeed FIR filters for video, RADAR, and other similar applications. The LMS12 implements the general form (A•B) + C. As a result, it is also useful in implementing polynomial approximations to transcendental functions. ARCHITECTURE A block diagram of the LMS12 is shown below. Its major features are discussed individually in the following paragraphs. MULTIPLIER The A11-0 and B11-0 inputs to the LMS12 are captured at the rising edge of the clock in the 12-bit A and B input registers, respectively. These registers are independently enabled by the ENA and ENB inputs. The registered input data are then applied to a 12 x 12-bit multiplier array, which produces a 24-bit result. Both the inputs and outputs of the multiplier are in two’s complement format. The multiplication result forms the input to the 24-bit product register. SUMMER The C 25-0 inputs to the LMS12 form a 26-bit two’s complement number which is captured in the C register at the rising edge of the clock. The C register is enabled by assertion of the ENC input. The summer is a 26-bit adder which operates on the C register data and the sign extended contents of the product register to produce a 26-bit sum. This sum is applied to the 26-bit S register. OUTPUT The FTS input is the feedthrough control for the S register. When FTS is asserted, the summer result is applied directly to the S output port. When FTS is deasserted, data from the S register is output on the S port, effecting a one-cycle delay of the summer result. The S output port can be forced to a high-impedance state by driving the OE control line high. FTS would be asserted for conventional FIR filter applications, however the insertion of zero-coefficient filter taps may be accomplished by negating FTS. Negating FTS also allows application of the same filter transfer function to two interleaved datastreams with successive input and output sample points occurring on alternate clock cycles.
FEATURES
u 12 x 12-bit Multiplier with Pipelined 26-bit Output Summer u Summer has 26-bit Input Port Fully Independent from Multiplier Inputs u Cascadable to Form Video Rate FIR Filter with 3-bit Headroom u A, B, and C Input Registers Separately Enabled for Maximum Flexibility u 28 MHz Data Rate for FIR Filtering Applications u High Speed, Low Power CMOS Technology u 84-pin PLCC, J-Lead
LMS12 BLOCK DIAGRAM
A 11-0 12 ENA A REGISTER B 11-0 12 B REGISTER ENB
CLK
24 PRODUCT REGISTER
SIGN EXTENDED
FTS 2 24
C REGISTER
C 25-0 26
S REGISTER
S 25-0 26 26 OE
26
ENC
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LMS12
DEVICES INCORPORATED
12-bit Cascadable Multiplier-Summer
FIGURE 1.
FLOW DIAGRAM FOR 5-TAP FIR FILTER
x(n) h4 h3 h2 h1 h0
Z –1
Z –1
Z –1
Z –1
y(n)
x(n)
A4
A3
A2
A1
A0
h4
h3
h2
h1
h0
Z –1
Z –1
Z –1
Z –1
Z –1
y(n)
APPLICATIONS The LMS12 is designed specifically for high-speed FIR filtering applications requiring a throughput rate of one output sample per clock period. By cascading LMS12 units, the transpose form of the FIR transfer function is implemented directly, with each of the LMS12 units supplying one of the filter weights, and the cascaded summers accumulating the results. The signal flow graph for a 5-tap FIR filter and the equivalent implementation using LMS12’s is shown in Figure 1.
The operation of the 5-tap FIR filter implementation of Figure 1 is depicted in Table 1. The filter weights h4 - h0 are assumed to be latched in the B input registers of the LMS12 units. The x(n) data is applied in parallel to the A input registers of all devices. For descriptive purposes in the table, the A register contents and sum output data of each device is labelled
according to the index of the weight applied by that device; i.e., S0 is produced by the rightmost device, which has h0 as its filter weight and A0 as its input register contents. Each column represents one clock cycle, with the data passing a particular point in the system illustrated across each row.
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LMS12
DEVICES INCORPORATED
12-bit Cascadable Multiplier-Summer
TABLE 1.
CLK Cycle X(n) A4 Register Sum 4 A3 Register Sum 3 A2 Register Sum 2
TIMING EXAMPLE FOR 5-TAP NONDECIMATING FIR FILTER
1 Xn 2 Xn+1 Xn Xn 3 Xn+2 Xn+1 h4Xn Xn+1 h3Xn + h4Xn–1 Xn+1 h2Xn + h3Xn–1 + h4Xn–2 Xn+1 h1Xn + h2Xn–1 + h3Xn–2 + h4Xn–3 Xn+1 h0Xn + h1Xn–1 + h2Xn–2 + h3Xn–3 + h4Xn–4 4 Xn+3 Xn+2 h4Xn+1 Xn+2 h3Xn+1 + h4Xn Xn+2 h2Xn+1 + h3Xn + h4Xn–1 Xn+2 h1Xn+1 + h2Xn + h3Xn–1 + h4Xn–2 Xn+2 h0Xn+1 + h1Xn + h2Xn–1 + h3Xn–2 + h4Xn–3 5 Xn+4 Xn+3 h4Xn+2 Xn+3 h3Xn+2 + h4Xn+1 Xn+3 h2Xn+2 + h3Xn+1 + h4Xn Xn+3 h1Xn+2 + h2Xn+1 + h3Xn + h4Xn–1 Xn+3 h0Xn+2 + h1Xn+1 + h2Xn + h3Xn–1 + h4Xn–2 6 Xn+5 Xn+4 h4Xn+3 Xn+4 h3Xn+3 + h4Xn+2 Xn+4 h2Xn+3 + h3Xn+2 + h4Xn+1 Xn+4 h1Xn+3 + h2Xn+2 + h3Xn+1 + h4Xn Xn+4 h0Xn+3 + h1Xn+2 + h2Xn+1 + h3Xn + h4Xn–1 7 Xn+6 Xn+5 h4Xn+4 Xn+5 h3Xn+4 + h4Xn+3 Xn+5 h2Xn+4 + h3Xn+3 + h4Xn+2 Xn+5 h1Xn+4 + h2Xn+3 + h3Xn+2 + h4Xn+1 Xn+5 h0Xn+4 + h1Xn+3 + h2Xn+2 + h3Xn+1 + h4Xn 8 Xn+7 Xn+6 h4Xn+5 Xn+6 h3Xn+5 + h4Xn+4 Xn+6 h2Xn+5 + h3Xn+4 + h4Xn+3 Xn+6 h1Xn+5 + h2Xn+4 + h3Xn+3 + h4Xn+2 Xn+6 h0Xn+5 + h1Xn+4 + h2Xn+3 + h3Xn+2 + h4Xn+1 9 Xn+8 Xn+7 h4Xn+6 Xn+7 h3Xn+6 + h4Xn+5 Xn+7 h2Xn+6 + h3Xn+5 + h4Xn+4 Xn+7 h1Xn+6 + h2Xn+5 + h3Xn+4 + h4Xn+3 Xn+7 h0Xn+6 + h1Xn+5 + h2Xn+4 + h3Xn+3 + h4Xn+2
Xn
A1 Register Sum 1
Xn
A0 Register Sum 0
Xn
FIGURE 2A.
INPUT FORMATS
AIN Fractional Two’s Complement 11 10 9 –20 2–1 2–2
(Sign)
BIN
210 2–9 2–10 2–11
11 10 9 –20 2–1 2–2
(Sign)
210 2–9 2–10 2–11
Integer Two’s Complement 11 10 9 –211 210 29
(Sign)
210 22 21 20
11 10 9 –211 210 29
(Sign)
210 22 21 20
FIGURE 2B.
OUTPUT FORMATS
Fractional Two’s Complement 25 24 –23 22
(Sign)
23 22 21 21 20 2–1
14 13 12 2–8 2–9 2–10
11 10 9 2–11 2–12 2–13
210 2–20 2–21 2–22
Integer Two’s Complement 25 24 –225 224
(Sign)
23 22 21 223 222 221
14 13 12 214 213 212
11 10 9 211 210 29
210 22 21 20
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LMS12
DEVICES INCORPORATED
12-bit Cascadable Multiplier-Summer
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0°C to +70°C –55°C to +125°C Supply Voltage 4.75 V ≤ VCC ≤ 5.25 V 4.50 V ≤ VCC ≤ 5.50 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol VOH VOL VIH VIL IIX IOZ ICC1 ICC2 Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent
(Note 3)
Test Condition VCC = Min., IOH = –2.0 mA VCC = Min., IOL = 4.0 mA
Min 2.4
Typ
Max
Unit V
0.5 2.0 0.0 VCC 0.8 ±20 ±20 15 25 1.0
V V V µA µA mA mA
Ground ≤ VIN ≤ VCC (Note 12) Ground ≤ VOUT ≤ VCC (Note 12)
(Notes 5, 6) (Note 7)
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432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
*DISCONTINUED SPEED GRADE
Symbol
32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321
Min
DEVICES INCORPORATED
SWITCHING WAVEFORMS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
SWITCHING CHARACTERISTICS
tDIS
tENA
tD
tHEN
tHC
tHAB
tSEN
tSC
tSAB
tPW
tCP
R OUTPUTS
S OUTPUTS
ENA ENB, ENC
INPUTS A, B, C
CLOCK
Parameter
Three-State Output Disable Delay (Note 11)
Three-State Output Enable Delay (Note 11)
Clock to S–FT = 0
Clock to S–FT = 1
ENA, ENB, ENC Hold Time
C Data Hold Time
A, B, Data Hold Time
ENA, ENB, ENC Setup Time
C Data Setup Time
A, B, Data Setup Time
Clock Pulse Width
Clock Period
OE
tSEN
tSAB tSC
tDIS
5
HIGH IMPEDANCE
12-bit Cascadable Multiplier-Summer
tHAB tHC
tHEN
tPW
15
40
15
15
15
5
5
5
tD
65*
tENA
Max
25
50
22
25
Min
10
35
12
15
12
5
5
5
50*
Max
25
40
22
25
LMS12–
Multiplier-Summers
tPW
Min
30
12
12
12
5
7
5
5
40
Max
25
35
22
25
08/16/2000–LDS.S12-J
Min
25
10
10
2
7
2
2
8
LMS12
35
Max
20 30
20 20
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
*DISCONTINUED SPEED GRADE
Symbol
2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321 2121098765432109876543210987654321
Min
DEVICES INCORPORATED
SWITCHING WAVEFORMS
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
SWITCHING CHARACTERISTICS
tDIS
tENA
tD
tHEN
tHC
tHAB
tSEN
tSC
tSAB
tPW
tCP
R OUTPUTS
S OUTPUTS
ENA ENB, ENC
INPUTS A, B, C
CLOCK
Parameter
Three-State Output Disable Delay (Note 11)
Three-State Output Enable Delay (Note 11)
Clock to S–FT = 0
Clock to S–FT = 1
ENA, ENB, ENC Hold Time
C Data Hold Time
A, B, Data Hold Time
ENA, ENB, ENC Setup Time
C Data Setup Time
A, B, Data Setup Time
Clock Pulse Width
Clock Period
OE
tSEN
tSAB tSC
tDIS
6
HIGH IMPEDANCE
12-bit Cascadable Multiplier-Summer
tHAB tHC
tHEN
tPW
tD
tENA
15
40
15
15
15
5
5
5
65*
Max
25
50
22
25
Multiplier-Summers
tPW
Min
15
35
15
15
15
LMS12– 50*
5
5
5
Max
25
45
22
25
08/16/2000–LDS.S12-J
Min
12
30
12
12
12
5
5
5
LMS12
40*
Max
25 35
22 25
LMS12
DEVICES INCORPORATED
12-bit Cascadable Multiplier-Summer
NOTES
9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of I OH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter6. Tested with all outputs changing ev- nal system must supply at least that ery cycle and no load, at a 5 MHz clock much time to meet the worst-case requirements of all parts. Responses from rate. the internal circuitry are specified from 7. Tested with all inputs within 0.1 V of the point of view of the device. Output VCC or Ground, no load. delay, for example, is specified as a 8. These parameters are guaranteed maximum since worst-case operation of any device always provides data within but not 100% tested. that time. N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
DUT
S1 IOL CL IOH VTH
FIGURE B. THRESHOLD LEVELS
tENA OE
Z 0
1.5 V 1.5 V 1.5 V
tDIS
3.5V Vth VOL*
0.2 V
0 1
Z Z
1.5 V
VOH*
0.2 V
Z
1
0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA
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LMS12
DEVICES INCORPORATED
12-bit Cascadable Multiplier-Summer
ORDERING INFORMATION
84-pin
B1 B0 ENA A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ENC C0 C1 C2 C3 C4
B2 B3 B4 CLK B5 B6 B7 B8 B9 B10 B11 ENB S25 S24 S23 S22 S21 S20 OE FTS VCC
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 74 13 73 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 72 71 70 69 68 67 66
Top View
65 64 63 62 61 60 59 58 57 56
55 32 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
GND C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24
Speed
0°C to +70°C — COMMERCIAL SCREENING
40 ns 35 ns LMS12JC40 LMS12JC35
S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 C25
Plastic J-Lead Chip Carrier (J3)
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121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 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DEVICES INCORPORATED
Speed
–55°C to +125°C — MIL-STD-883 COMPLIANT
–55°C to +125°C — COMMERCIAL SCREENING
0°C to +70°C — COMMERCIAL SCREENING
ORDERING INFORMATION
84-pin
G
H
D
C
K
E
B
A
F
L
J
ENB
CLK
VCC
S20
S22
S25
OE
B9
B4
B1
B6
1
ENA
FTS
S19
S17
S21
S24
B2
B7
B8
B5
B3
2
S16
S18
S23
B11
B10
A11
B0
3
Ceramic Pin Grid Array (G3)
Discontinued Package
S14
S15
A10
A9
4
(i.e., Component Side Pinout)
S11
S12
S10
A5
A7
A6
5
Through Package
9
Top View
S13
S8
S9
A4
A3
A8
6
12-bit Cascadable Multiplier-Summer
S7
S6
S5
A0
A1
A2
7
ENC
C0
S4
S3
8
C18
C14
C13
C3
C1
S2
S0
9
C24
C23
C20
C17
C15
C11
10
C8
C5
C4
C2
S1
GND
C25
C22
C21
C19
C16
C10
C12
11
C9
C7
C6
Multiplier-Summers LMS12
08/16/2000–LDS.S12-J
工商网监
湘ICP备2023018690号
