LR24C08D

LESHAN RADIO COMPANY, LTD. 1024 × 8 (8K bits) LR24C08 Two-Wire Serial EEPROM Features Compatible with all I2C bidirectional  data transfer  – 8K bits (1024 X 8) of EEPROM – Page size: 16 bytes  1 MHz Endurance: 1 Million Write Cycles – Data Retention: 100 Years  Write: – – Byte Write within 3 ms – Page Write within 3 ms – Partial Page Writes Allowed High-reliability – Random and sequential Read modes  Schmitt Trigger, Filtered Inputs for Noise Suppression Single supply voltage and high speed:  Write Protect Pin for Hardware Data Protection protocol Memory array:  –  Enhanced ESD/Latch-up protection HBM 8000V  8-lead SOP and TSSOP package Description The LR24C08 provides 8192 bits of  The device is optimized for use in many  serial electrically erasable and industrial and commercial applications programmable read-only memory where low-power and low-voltage (EEPROM), organized as 1024 words of operation are essential. 8 bits each. Pin Configuration ８-lead PDIP ８-lead SOP ８-pad DFN ８-lead TSSOP A0 １ 8 VCC A0 １ 8 VCC A0 １ 8 VCC VCC 8 1 A0 A1 ２ 7 WP A1 ２ 7 WP A1 ２ 7 WP WP 7 2 A1 A2 ３ 6 SCL A2 ３ 6 SCL A2 ３ 6 SCL SCL 6 3 A2 GND ４ 5 SDA GND ４ 5 SDA GND ４ 5 SDA SDA 5 4 GND Bottem view V2.1 1／16 LESHAN RADIO COMPANY, LTD. Pin Descriptions Pin Name Type Functions SDA I/O Serial Data SCL I Serial Clock Input WP I Write Protect GND P Ground Vcc P Power Supply A0-A2 I Address Input(A0 & A1 NC) Table 1 Block Diagram Vcc GND WP SCL START STOP LOGIC SDA EN SERIAL CONTROL LOGIC HIGH VOLTAGE PUMP/TIMING LOAD DATA RECOVERY CCMP DEVICE ADDRESS COMPARATOR LOAD INC A0(NC) X DECODER DATA WORD ADRESS COUNTER EEPROM A1(NC) A2 Y DECODER DIN SERIAL MUX DOUT/ACKNOWLEDGE DOUT SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or opencollector devices. SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. WRITE PROTECT (WP): The LR24C08 has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to V2.1 2／16 LESHAN RADIO COMPANY, LTD. ground (GND). When the Write Protection pin is connected to Vcc, the write protection feature is enabled and operates as shown in the following Table 2. WP Pin Status LR24C08 At VCC Full Array At GND Normal Read/Write Operations Functional Description 1. Memory Organization LR24C08 , 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing. 2. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 3). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The LR24C08 features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition. V2.1 3／16 LESHAN RADIO COMPANY, LTD. Figure 2. Data Validity SDA SCL DATA STABLE DATA CHANGE DATA STABLE Figure 3. Start and Stop Definition SDA SCL START STOP Figure 4. Output Acknowledge SCL 1 8 9 DATA IN DATA OUT START ACKNOWLEDGE V2.1 4／16 LESHAN RADIO COMPANY, LTD. 3. Device Addressing The LR24C08 EEPROM devices require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 5) The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices. For the 8K EEPROM, uses the A2 input for hardwire addressing and the next 2 bits being for memory page addressing. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state. 4. Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 6). PAGE WRITE: The LR24C08 EEPROM devices are capable of 16-byte page writes.A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to fifteen (8K) more data words. The EEPROM will respond with a "0" after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 7). The data word address lower four (8K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than sixteen (8K) data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten. V2.1 5／16 LESHAN RADIO COMPANY, LTD. ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read or write sequence to continue. 5. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop condition (see Figure 8). RANDOM READ:A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 9) SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 10). V2.1 6／16 LESHAN RADIO COMPANY, LTD. Figure 5. Device Address MSB LSB 1 8K 0 1 0 A2 P1 P0 R/W Figure 6. Byte Write S T A R T DEVICE ADDRESS W R I T E WORD ADDRESS S T O P DATA SDA LINE M S B L R A S / C BWK L A S C B K L A S C B K Figure 7. Page Write S T A R T DEVICE ADDRESS W R I T E WORD ADDRESS DATA(n+1) DATA(n) S T O P DATA(n+1) SDA LINE M S B V2.1 L R A S / C BWK L A S C B K A C K A C K A C K 7／16 LESHAN RADIO COMPANY, LTD. Figure 8. Current Address Read S T A R T R E A D DEVICE ADDRESS S T O P DATA SDA LINE M S B L R A S / C BWK NO ACK Figure 9. Random Read S T A R T DEVICE ADDRESS W R I T E S T A R T WORD ADDRESS DEVICE ADDRESS R E A D DATA(n) S T O P SDA LINE M S B L R A S / C BWK A C K L A S C B K NO ACK DUMMY WRITE Figure 10. Sequential Read DEVICE ADDRESS R E A D DATA(n+1) DATA(n) DATA(n+2) DATA(n+x) S T O P SDA LINE R A / C WK V2.1 A C K A C K A C K NO ACK 8／16 LESHAN RADIO COMPANY, LTD. Electrical Characteristics Absolute Maximum Stress Ratings：  DC Supply Voltage . . . . . . . . . . . . . . . ... .-0.3V to +6.5V  Input / Output Voltage . . . . . ………... … .GND-0.3V to VCC+0.3V  Operating Ambient Temperature . . . .  Storage Temperature . . . . . . . . . . …….. . -65℃ to +150℃ -55℃ to +125℃ Comments： Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Applicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +1.7V to +5.5V (unless otherwise noted) Parameter Symbol Min Typ Max Unit Condition Supply Voltage VCC1 1.7 - 5.5 V Supply Current VCC=5.0V ICC1 - 0.40 1.5 mA VCC=5V;READ at 400KHZ Supply Current VCC=5.0V ICC2 - 1.50 2.0 mA VCC=5V;WRITE at 400KHZ Supply Current VCC=5.5V ISB1 - 1.50 2.0 μA VIN=VCC or VSS/VCC=1.7V Input Leakage Current IL1 - 0.10 2.0 μA VIN=VCC or VSS Output Leakage Current ILO - 0.05 2.0 μA VOUT=VCC or VSS Input Low Level VIL1 -0.3 - VCC×0.3 V VCC=1.8V to 5.5V Input High Level VIH1 VCC×0.7 - VCC+0.3 V VCC=1.7V to 5.5V Output Low Level VCC=1.7V VOL1 - - 0.2 V IOL=0.15mA Output Low Level VCC=5.0V VOL2 - - 0.4 V IOL=3.0mA - Table 5 Thermal Characteristics Thermal Resistance,Junction-to-Ambient V2.1 RθJA 125 ℃/W 9／16 LESHAN RADIO COMPANY, LTD. Pin Capacitance Applicable over recommended operating range from TA = 25℃, f = 1.0 MHz, VCC = +1.7V Parameter Symbol Min Typ Max Unit Condition Input/Output Capacitance(SDA) CI/O - - 8 pF VIO=0V Input Capacitance(SCL) CIN - - 6 pF VIN=0V Table 6 AC Electrical Characteristics Applicable over recommended operating range from TA = -40℃ to +85℃, VCC = +1.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Parameter 1.7V≤VCC﹤2.5V Symbol 2.5V≤VCC﹤5.5V Min Typ Max Min Typ Max Units Clock Frequency,SCL fSCL - - 400 - - 1000 KHZ Clock Pulse Width Low tLOW 1.2 - - 0.6 - - μs Clock Pulse Width High tHIGH 0.6 - - 0.4 - - μs Noise Suppression Time tI - - 50 - - 50 ns Clock Low to Data Out Valid tAA 0.1 - 0.9 0.05 - 0.9 μs Time the bus must be free before a new transmission can start tBUF 1.2 - - 0.5 - - μs Start Hold Time tHD:STA 0.6 - - 0.25 - - μs Start Setup Time tSU:DAT 0.6 - - 0.25 - - μs Data In Hold Time tHD:DAT 0 - - 0 - - μs Data in Setup Time tSU:DAT 100 - - 100 - - ns Input Rise Time(1) tR - - 0.3 - - 0.3 μs Input Fall Time(1) tF - - 0.3 - - 0.1 μs Stop Setup Time tSu:STO 0.6 - - 0.25 - - μs Data Out Hold Time tDH 50 - - 50 - - ns Write Cycle Time twR - 3.3 4 - 3.3 4 ms Endurance 1M - - - - - Write Cycle 5.0V,25℃,Byte Mode(1) Notes: Table 7 1. This parameter is characterized and is not 100% tested. 2. AC measurement conditions: RL (connects to VCC): 1.3 k Input pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall time: 50 ns V2.1 10／16 LESHAN RADIO COMPANY, LTD. Bus Timing Figure 11. SCL: Serial Clock, SDA: Serial Data I/O tF tHIGH tR tLOW tLOW SCL tSU.DAT tHD.DAT tHD.STA tSU.STA tSU.STO SDA_IN tAA t BUF tDH SDA_OUT Write Cycle Timing Figure 12. SCL: Serial Clock, SDA: Serial Data I/O SCL ACK SDA Word n tWR(1) STOP CONDITION START CONDITION Notes: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. V2.1 11／16 LESHAN RADIO COMPANY, LTD. Package Information Package 8-Pin DIP8L 8 5 E1 1 4 D E A2 L C A1 b S A eB e b1 Dimensions Symbol Unit A Min mm b b1 C D E E1 0.38 3.18 0.36 1.14 0.20 9.02 7.62 6.22 3.30 0.46 1.52 0.25 9.27 7.87 6.35 3.43 0.56 1.78 0.36 10.16 8.13 0.125 0.014 0.045 0.008 0.355 0.130 0.018 0.060 0.010 0.135 0.022 0.070 0.014 5.33 Min 0.015 Nom Max V2.1 A2 Nom Max Inch A1 0.21 e SL S 7.87 2.92 0.76 8.89 3.30 1.14 6.48 9.53 3.81 1.52 0.300 0.245 0.310 0.115 0.030 0.365 0.310 0.250 0.350 0.130 0.045 0.400 0.320 0.255 0.375 0.150 0.060 2.54 0.10 eB 12／16 LESHAN RADIO COMPANY, LTD. Package 8-Pin UDFN D D2 L PIN 1 DOT BY MARKING E E2 PIN #1 IDENTIFICATION CHAMFER TOP VIEW A A3 A1 SIDE VIEW V2.1 b e BOTTOM VIEW PKG REF A A1 A3 D E b L D2 E2 e COMMON DIMENSION(MM) UT:ULTRA THIN MIN NOM MAX >0.50 0.55 0.60 0.00 0.05 0.15REF 1.95 2.00 2.05 2.95 3.00 3.05 0.20 0.25 0.30 0.20 0.30 0.40 1.25 1.40 1.50 1.15 1.30 1.40 0.50BSC 13／16 LESHAN RADIO COMPANY, LTD. Package 8-Pin SOP 150-mil 5 8 θ E E1 L L1 1 4 C D A2 S b e A A1 Dimensions Symbol A1 A2 b C D E E1 Min 0.10 1.35 0.36 0.15 4.77 5.80 3.80 Nom 0.15 1.45 0.41 0.20 4.90 5.99 3.90 Unit mm Max Inch 1.75 e 1.27 L L1 S θ 0.46 0.85 0.41 0 0.66 1.05 0.54 5 0.20 1.55 0.51 0.25 5.03 6.20 4.00 0.86 1.25 0.67 8 Min 0.004 0.053 0.014 0.006 0.188 0.228 0.150 0.018 0.033 0.016 0 Nom 0.006 0.057 0.016 0.008 0.193 0.236 0.154 0.026 0.041 0.021 5 0.008 0.061 0.020 0.010 0.198 0.244 0.158 0.034 0.049 0.026 8 Max V2.1 A 0.069 0.05 14／16 LESHAN RADIO COMPANY, LTD. Package 8-Pin TSSOP 5 8 θ E E1 1 L L1 4 C D A2 S b e A A1 Dimensions Symbol A A1 A2 b C D E E1 e L L1 θ Min - 0.05 0.80 0.20 0.10 2.90 6.30 4.30 - 0.45 0.85 0 Nom - 0.10 0.90 0.25 0.15 3.00 6.40 4.40 0.65 0.60 1.00 4 Max 1.20 0.15 1.00 0.30 0.20 3.10 6.50 4.50 - 0.75 1.15 8 Min - 0.002 0.031 0.008 0.004 0.144 0.248 0.169 - 0.018 0.033 0 Nom - 0.004 0.035 0.010 0.006 0.118 0.252 0.173 0.026 0.024 0.039 4 Max 0.047 0.006 0.039 0.012 0.008 0.122 0.256 0.177 - 0.030 0.045 8 Unit mm Inch V2.1 15／16 LESHAN RADIO COMPANY, LTD. Order Information LR 24C 08 X Package Type T :TSSOP8 D:SOP8 U:DFN2*3 Density 02:2Kbits 04:4Kbits 08:8Kbits 16:16Kbits 32:32Kbits 64:64Kbits 128:128Kbits 256:256Kbits 512:512Kbits Product Family 24C:Two-wire EEPROM Internal serial number V2.1 16／16