L9A0212

TinyRISC® LR4102 Microprocessor Datasheet The TinyRISC LR4102 Microprocessor is a compact, high performance 32-bit microprocessor implemented in the LSI Logic G11™ technology. The LR4102 is a complete microprocessor solution with caches, an external bus interface with built-in memory controllers, and on-chip debug. The LR4102 is built using the EZ4102 EasyMACRO subsystem, available to customers through the LSI Logic CoreWare® program. The LR4102 provides a 32-bit FBusMACRO to control all off-chip data transactions (including DRAM or SDRAM) and an EJTAG interface for on-chip debug with PC trace output. Figure 1 illustrates the LR4102 chip. Figure 1 LR4102 LR4102 Block Diagram MMU TLB RAM Caches Clock Controller 32-bit TinyRISC 4102 CPU and FastMDU BIU and Cache Controller (BBCC) OCM FBusMACRO FBus Two 32-bit Timers SerialICE™-1 Port EJTAG SerialICE-1 Interface EJTAG Interface EJTAG Extended Debug MACRO PC Trace Output The LR4102 microprocessor is powered by either 2.5 V (for 85 MHz operation) or 1.8 V (for 50 MHz operation). The chip I/O ring requires 3.3 V. With a system clock of 85 MHz, peak performance is 85 MIPS and sustained performance is estimated at 68 MIPS. With a 50 MHz clock, performance is 50 MIPS peak and 40 MIPS sustained. March 2000 Copyright © 1998–2000 by LSI Logic Corporation. All rights reserved. 1 LR4102 Features Components • Caches – – 16 Kbytes of two-way set-associative I-Cache 8 Kbytes of direct-mapped D-Cache • R3000 MIPS CPU executes MIPS II and MIPS16 instructions 32-bit FBus, a fast demultiplexed multimaster bus, with built in control of: – – – RAM, EPROM, or similar simple devices DRAM and SDRAM General-purpose I/O • • Clock module with integrated PLL and programmable clock speeds Technology • LSI Logic G11 Technology – – 0.18 µ Leff (0.25 µ drawn) 2.5 or 1.8 V operation • • Two 32-bit Timers FastMDU – 4/5 cycle multiply and accumulate (32-bit to 64-bit) Performance and Compatibility • • • • – 34/35 cycle divide BBCC with four writeback buffers included Clock speed is 85 MHz at 2.5 V (85 MIPS peak and estimated 68 MIPS sustained) Low power mode allows LR4102 to use minimal power when idle Compatible with the full range of MIPS and third-party software development tools 16-bit and 32-bit code can be mixed arbitrarily with full support on a subroutine basis All instructions execute in one cycle except for Load and Store, Move To Coprocessor, and Move From Coprocessor, which execute in two cycles, and MDU instructions, which execute in several cycles • MMU with 64-entry TLB RAM • EJTAG Version 2.0.0: – Nonintrusive debug • – Real-time PC trace – Hardware breakpoints SerialICE-1 Port included for • backward compatibility with other TinyRISC designs JTAG Boundary Scan On-Chip Memory (OCM), 1 Kbyte • • • 2 TinyRISC LR4102 Microprocessor Block Diagram This section provides short descriptions of the major components of the LR4102, as shown in Figure 1. The CPU performs all arithmetic, logical, shift, and address calculations. The CPU supports EJTAG debug and is closely coupled with the FastMDU. The FastMDU calculates all multiply and divide operations for the LR4102, and provides 4/5 cycle multiply and accumulate operations (32 bit to 64 bit), 34/35 cycle divide, saturated math, and overflow indication. The memory management unit (MMU) translates virtual addresses from the CPU into physical addresses and includes a 64-entry translation look-aside buffer (TLB) RAM. The BIU and cache controller (BBCC) provides an internal bus interface and connects the CPU to the caches. For the caches, the LR4102 contains 16 Kbytes of two-way set-associative I-Cache and 8 Kbytes of direct-mapped D-Cache. Four Write Buffers are integrated with the BBCC in the LR4102 design. The 32-bit FBusMACRO (FBM) controls the FBus, a dedicated, multimaster bus that connects off-chip logic with the LR4102. The FBus allows seamless LR4102 connection to a variety of devices, including EPROM, FLASH, RAM, DRAM, SDRAM, and general-purpose I/O pins. The FBus also supports burst read (one cycle) and write, built-in arbitration for an external FBus master, and snooping of external write accesses to memory. Internally, the FBusMACRO interfaces mainly with the BBCC module. Each 32-bit Timer can count down from a preloaded value, roll over or stop at zero, generate an interrupt on zero, or act as bus watchdog. The CPU can program either of the two internal 32-bit timers. The LR4102 includes 1 Kbyte of on-chip memory (OCM). The Clock Controller steps CPU clock speed up or down, and can stop the internal LR4102 clock altogether. The LR4102 also supports a low power mode. The LR4102 Clock Controller is designed to support a crystal or canned oscillator, and has an on-chip PLL for frequency multiplication. TinyRISC LR4102 Microprocessor 3 The EJTAG with PC Trace output provides real-time program counter (PC) trace and breakpoint capability in an EJTAG compatible debug design. PC trace outputs are provided through the Extended Debug MACRO for complete and accurate chip debug. A SerialICE-1 Port (UART) is also included in the LR4102 to provide backward compatibility with previous TinyRISC designs. Pipeline Architecture The LR4102 implements a 3-stage pipeline (Fetch, Execute, and Writeback) that uses a single adder for the ALU, the data address, and the instruction address. Sharing a single adder dramatically reduces the circuitry required to implement the microprocessor, and eliminates pipeline registers and bypass logic. The LR4102 design does not require a load delay slot. Figure 2 shows the microprocessor CPU 3-stage pipeline. Figure 2 LR4102 CPU Pipeline with X2 Stall Cycle IF X1 X2 Stall WB Instruction Fetch Execute Writeback The execution of a single LR4102 instruction consists of the following three pipeline stages: 1. Instruction Fetch – The LR4102 fetches the instruction (IF), and if necessary, decompresses a 16-bit instruction into a 32-bit instruction. 2. Execute – The LR4102 executes all ALU instructions, resolves conditional branches, and calculates load and store addresses (X1). The CPU then transfers load or store data from external memory or cache and performs move to/from coprocessor operations in a second execute (stall) cycle (X2), which is only inserted when required. 3. Writeback – The LR4102 writes the results into the register file (WB). 4 TinyRISC LR4102 Microprocessor Instruction Set Summary Table 1 summarizes the 32-bit instruction set for the LR4102, and Table 2 lists the unimplemented MIPS II instructions. Table 3 provides a summary of the LR4102 MIPS16 instruction set. Table 1 LR4102 32-Bit Instruction Set Summary Load and Store Instructions LB LBU LH LHU LW LWL LWR Load Byte Load Byte Unsigned Load Halfword Load Halfword Unsigned Load Word Load Word Left Load Word Right SB SH SW SWL SWR SYNC – Store Byte Store Halfword Store Word Store Word Left Store Word Right Synchronize (load/store synchronization) – Arithmetic Instructions: ALU Immediate ADDI ADDIU ANDI LUI Add Immediate Add Immediate Unsigned AND Immediate Load Upper Immediate ORI SLTI SLTIU XORI OR Immediate Set on Less Than Immediate Set on Less Than Immediate Unsigned Exclusive OR Immediate Arithmetic Instructions: Three-Operand, Register-Type ADD ADDU AND NOR OR Add Add Unsigned Logical AND Logical NOR Logical OR SLT SLTU SUB SUBU XOR Set on Less Than Set on Less Than Unsigned Subtract Subtract Unsigned Logical Exclusive OR (Sheet 1 of 4) TinyRISC LR4102 Microprocessor 5 Table 1 LR4102 32-Bit Instruction Set Summary (Cont.) Shift Instructions SLL SLLV SRA Shift Left Logical Shift Left Logical Variable Shift Right Arithmetic SRAV SRL SRLV Shift Right Arithmetic Variable Shift Right Logical Shift Right Logical Variable Multiply/Divide Instructions DIV DIVU MADD1 MADDU1 MFHI MFLO MSUB1 Divide Divide Unsigned Multiply Add Multiply Add Unsigned Move From HI Move From LO Multiply Subtract MSUBU1 MTHI MTLO MUL1 MULT MULTU – Multiply Subtract Unsigned Move To HI Move To LO Three-Operand Multiply Multiply Multiply Unsigned – Jump and Branch Instructions BCzF BCzT BEQ BGEZ BGEZAL BGTZ BLEZ BLTZ BCzFL Branch on Coprocessor z False Branch on Coprocessor z True Branch on Equal Branch on Greater Than or Equal to Zero Branch on Greater Than or Equal to Zero and Link Branch on Greater Than Zero BLTZAL BNE J JAL JALR JALX Branch on Less Than Zero and Link Branch on Not Equal Jump Jump and Link Jump and Link Register Jump and Link Exchange Jump Register Branch on Greater Than Zero Likely Branch on Less Than or Equal to Zero Likely Branch on Less Than or Equal to Zero JR Branch on Less Than Zero Branch on Coprocessor z False Likely BGTZL BLEZL (Sheet 2 of 4) 6 TinyRISC LR4102 Microprocessor Table 1 LR4102 32-Bit Instruction Set Summary (Cont.) Jump and Branch Instructions (Cont.) BCzTL BEQL BGEZALL BGEZL Branch on Coprocessor z True Likely Branch on Equal Likely Branch on Greater Than or Equal to Zero and Link Likely Branch on Greater Than or Equal to Zero Likely BLTZALL BLTZL BNEL – Branch on Less Than Zero and Link Likely Branch on Less Than Zero Likely Branch on Not Equal Likely – Coprocessor Instructions BCzF BCzT COPz CTCz CFCz LWCz Branch on Coprocessor z False Branch on Coprocessor z True Coprocessor Operation Move Control to Coprocessor z Move Control from Coprocessor z Load Word to Coprocessor z (z ≠ 0) MTCz MFCz SWCz BCzFL BCzTL – Move to Coprocessor z Move from Coprocessor z Store Word from Coprocessor z (z ≠ 0) Branch on Coprocessor z False Likely Branch on Coprocessor z True Likely – System Control Coprocessor (CP0) MFC0 MTC0 TLBR TLBWR Move from CP0 Move to CP0 Read Indexed TLB Entry Write Random TLB Entry RFE WAITI1 TLBWI TLBP Restore from Exception Wait for Interrupt Write Indexed TLB Entry Probe TLB for Matching Entry Special Control Instructions BREAK Breakpoint SYSCALL System Call Trap Instructions TEQ Trap if Equal TLT Trap if Less Than (Sheet 3 of 4) TinyRISC LR4102 Microprocessor 7 Table 1 LR4102 32-Bit Instruction Set Summary (Cont.) Trap Instructions (Cont.) TEQI TGE TGEI TGEIU TGEU Trap if Equal Immediate Trap if Greater Than or Equal Trap if Greater Than or Equal Immediate Trap if Greater Than or Equal Immediate Unsigned TLTI TLTIU TLTU TNE Trap if Less Than Immediate Trap if Less Than Immediate Unsigned Trap if Less Than Unsigned Trap if Not Equal Trap If Not Equal Immediate Trap if Greater Than or Equal Unsigned TNEI EJTAG Debug Instructions SDBBP Software Debug Breakpoint DERET Debug Exception Return (Sheet 4 of 4) 1. LR4102/EZ4102-specific instruction. Table 2 Unimplemented Instructions Summary Unimplemented MIPS II Instructions COP1 LL SC All floating-point instructions Load Linked Word Store Conditional Word ERET LDCz SDCz Exception Return Load Doubleword to Coprocessor Store Doubleword to Coprocessor 8 TinyRISC LR4102 Microprocessor Table 3 LR4102 16-Bit Instruction Set Summary Load and Store Instructions LB1 LBU1 LH1 LHU1 Load Byte Load Byte Unsigned Load Halfword Load Halfword Unsigned LW1 SB1 SH1 SW1 Load Word Store Byte Store Halfword Store Word Arithmetic Instructions: ALU Immediate LI1 ADDIU1 SLTI1 Load Immediate Add Immediate Unsigned Set on Less Than Immediate SLTIU1 CMPI1 – Set on Less Than Immediate Unsigned Compare Immediate – Arithmetic Instructions: Two/Three Operand, Register Type ADDU SUBU SLT SLTU CMP NEG Add Unsigned Subtract Unsigned Set on Less Than Set on Less Than Unsigned Compare Negate AND OR XOR NOT MOVE – Logical AND Logical OR Exclusive Logical OR Logical NOT Move – Shift Instructions SLL1 SRL1 SRA1 Shift Left Logical Shift Right Logical Shift Right Arithmetic SLLV SRLV SRAV Shift Left Logical Variable Shift Right Logical Variable Shift Right Arithmetic Variable (Sheet 1 of 2) TinyRISC LR4102 Microprocessor 9 Table 3 LR4102 16-Bit Instruction Set Summary (Cont.) Multiply/Divide Instructions MULT MULTU DIV Multiply Multiply Unsigned Divide DIVU MFHI MFLO Divide Unsigned Move From HI Move From LO Jump and Branch Instructions JAL JALX JR JALR BEQZ1 Jump and Link Jump and Link Exchange Jump Register Jump and Link Register Branch on Equal to Zero BNEZ1 BTEQZ1 BTNEZ1 B1 – Branch on Not Equal to Zero Branch on T Equal to Zero Branch on T Not Equal to Zero Branch Unconditional – Special Instructions EXTEND Extend BREAK Breakpoint EJTAG Debug Instructions SDBBP Software Debug Breakpoint – – (Sheet 2 of 2) 1. Extensible instruction; for details, please see the documentation on the MIPS16 Application Specific Extension to the MIPS ISA, which is available from MIPS Technologies Incorporated. 10 TinyRISC LR4102 Microprocessor LR4102 Register Map Table 4 shows the LR4102 microprocessor register memory map. Table 4 LR4102 Register Memory Map Physical Address Description Register Name System configuration registers in BBCC SCR1 SCR2 SCR3 Timer registers T0ICR T0CCR T1ICR T1CCR TMR TISR 0x1FFF.0100 0x1FFF.0104 0x1FFF.0108 0x1FFF.010C 0x1FFF.0110 0x1FFF.0114 Timer 0 Initial Count Register Timer 0 Current Count Register Timer 1 Initial Count Register Timer 1 Current Count Register Mode Register Interrupt Status Register 0x1FFF.0000 0x1FFF.0004 0x1FFF.0008 System Configuration Register 1 System Configuration Register 2 System Configuration Register 3 SerialICE-1 Port (UART) registers RxStatus RxSetup RxData TxStatus TxData 0x1FFF.0200 0x1FFF.0200 0x1FFF.0204 0x1FFF.0208 0x1FFF.020C Receive (Rx) Status Register (Reading) Receive (Rx) Setup Register (Writing) Receive (Rx) Data Register Transmit (Tx) Status Register Transmit (Tx) Data Register Reserved registers Reserved FBus registers FACFG0 FACFG1 (Sheet 1 of 2) 0x1FFF.0400 0x1FFF.0404 Configuration for address range 0 Configuration for address range 1 0x1FFF.0300–.03FF Reserved for LSI Logic use TinyRISC LR4102 Microprocessor 11 Table 4 LR4102 Register Memory Map (Cont.) Physical Address Description Register Name FBus registers (Cont.) FACFG2 FACFG3 FACFG4 FACFG5 FBUSTA FACMP0 FACMP1 FACMP2 FACMP3 FACMP4 FACMP5 FBUSCMP FBUSAC FBUSCFG FSDRAM FDRAMT FSDRAMT FGPCFG FGPOUTPUT FGPINPUT 0x1FFF.0408 0x1FFF.040C 0x1FFF.0410 0x1FFF.0414 0x1FFF.0418 0x1FFF.0440 0x1FFF.0444 0x1FFF.0448 0x1FFF.044C 0x1FFF.0450 0x1FFF.0454 0x1FFF.0470 0x1FFF.0474 0x1FFF.0480 0x1FFF.0490 0x1FFF.0494 0x1FFF.0498 0x1FFF.04C0 0x1FFF.04C4 0x1FFF.04C8 Configuration for address range 2 Configuration for address range 3 Configuration for address range 4 Configuration for address range 5 Bus turnaround register for address range 0–5 Address compare register address range 0 Address compare register address range 1 Address compare register address range 2 Address compare register address range 3 Address compare register address range 4 Address compare register address range 5 Address compare register for FBus address range. Address compare register for FBus I/O, memory, and configuration address range. Configuration for FBus when accessing outside programmable address range 0–5. Configuration for external EDO (S)DRAM Timing parameters for external EDO DRAM Timing parameters for external SDRAM Configuration for General-Purpose I/O Output value for General-Purpose Outputs Input value for General-Purpose Inputs Reserved registers Reserved 0x1FFF.0500–.06FF Reserved for LSI Logic use On Chip Memory (OCM), 1 Kbytes OCM area (Sheet 2 of 2) 0x1FFF.8000–.83FF On chip memory. Placed on CBus, 1 cycle access 12 TinyRISC LR4102 Microprocessor Signal Descriptions The signals are described in alphabetical order by mnemonic. Each signal definition contains the mnemonic and the full signal name. Mnemonics for signals that are active LOW end in an “N”, and mnemonics for signals that are active HIGH end in a “P.” In the descriptions that follow, the verb assert means to drive active. The verb deassert means to drive inactive. The LR4102 signals are divided into the following groups: • • • • • • • • • Control Signals Clocking Interface Timer Interface SerialICE-1 Interface EJTAG Interface and JTAG boundary scan signals PC Trace Output FBus Interface Test Interface Power Lines Table 5 lists all of the LR4102 signals, grouped by interface. Table 5 LR4102 Signal List Mnemonic Name RESETN BIG_ENDIANP CWAITIP INTP[5:0] DEBUGMP (Sheet 1 of 4) Functional Description Asynchronous system reset Big/Little Endian select Wait for interrupt (low power mode) Condition/Interrupt Debug mode I/O Input Input Output Input Output Signal Group Control Signals TinyRISC LR4102 Microprocessor 13 Table 5 LR4102 Signal List (Cont.) Mnemonic Name EXTAL XTAL PBCLKP SDCLKP DIVC[1:0] DIVA[1:0] SELECT_PLLN RESET_OUTN PLLENP PLLENARSTP Functional Description Input from crystal/Oscillator Output to crystal FAPI clock SDRAM clock The divide value for DIV C upon reset The divide value for DIV A Control clock source MUX Delayed reset signal for FAPI bus Enable PLL Enable PLL auto reset Timer 0 output Timer 1 output SerialICE-1 Port clock SerialICE-1 Port receive SerialICE-1 Port transmit EJTAG Interface clock EJTAG Interface mode select EJTAG Interface data in/Debug interrupt EJTAG Interface data out/PC out EJTAG Interface reset PC Trace clock output PC Trace status set 1 [2:0] PC Trace PC out [4:2] I/O Input Output Output Output Input Input Input Output Input Input Output Output Input Input Output Input Input Input Output Input Output Output Output Signal Group Clocking Interface Timer Interface T0_OUTN T1_OUTN SerialICE-1 Interface ICECLKP ICERXP ICETXP EJTAG Interface and JTAG boundary scan signals TCK TMS TDI_DINT TDO_TPC TRST PC Trace Output DCLK PCST1[2:0] TPC[4:2] (Sheet 2 of 4) 14 TinyRISC LR4102 Microprocessor Table 5 LR4102 Signal List (Cont.) Mnemonic Name CBEN[3:0] DEVSELN FADDRP[28:0] FADP[31:0] FALEP FRAMEN GNTN GP[5:0] GPIO[3:0] GPRDN GPWEN[3:0] IRDYN REQN SD_CASN0_DMP0 SD_CASN1_DMP1 SD_CASN2_DMP2 SD_CASN3_DMP3 SD_OEN_CASN SDONEP SD_RASN SD_RASN0_CSN0 SD_RASN1_CSN1 SD_WEN_WEN STOPN Functional Description Command/byte enable Device select Demultiplexed address bus Multiplexed address/Data bus Address latch enable Cycle frame indicating a bus transaction is beginning Grant the FBus General-purpose pins General-purpose I/O pins General-purpose read enable General-purpose write byte enable Initiator ready Request FBus DRAM CAS0 or SDRAM data mask 0 DRAM CAS1 or SDRAM data mask 1 DRAM CAS2 or SDRAM data mask 2 DRAM CAS3 or SDRAM data mask 3 DRAM output enable or SDRAM CAS Snooping done SDRAM RAS DRAM RAS bank 0 or SDRAM CAS0 DRAM RAS bank 1 or SDRAM CAS1 I/O Bidirectional Bidirectional Output Bidirectional Output Bidirectional Output Bidirectional Bidirectional Output Output Bidirectional Input Output Output Output Output Output Output Output Output Output Signal Group FBus Interface DRAM write enable or SDRAM write enable Output Stop transaction Bidirectional (Sheet 3 of 4) TinyRISC LR4102 Microprocessor 15 Table 5 LR4102 Signal List (Cont.) Mnemonic Name TRDYN CSHTSTP IDDTN JTAGALSOP PMON_OUTP SCAN_ENABLEP SCAN__INP SCAN_MODEP SCAN_OUTP SCAN_RAMWEP SELECT_CKOUT1N TN Functional Description Target ready Cache test enable IDD test JTAG controller present Process monitor output Enable scan chain loading Input to the scan chain Enable scan testing Output from the scan chain RAM write enable Select PLL test 3-state all LR4102 output and bidirectional signals VDD for CPU core and oscillator 2.5 V or 1.8 V VDD for I/O 3.3 V VDD to PLL 2.5 V. Requires VDD CPU core and oscillator at 2.5 V, since PLL must be disabled for VDD CPU core and clock at 1.8 V VSS for CPU core, clock, I/O and PLL I/O Bidirectional Input Input Input Output Input Input Input Output Input Input Input Power Power Power Signal Group FBus Interface Test Interface Power Lines VDD, VDD2 VDD4 PLLVDD1 VSS, VSS2, VSS4, PLLVSS1 (Sheet 4 of 4) Power 16 TinyRISC LR4102 Microprocessor LR4102 Specifications This section specifies the LR4102 electrical characteristics and includes the following subsections: • • “AC Timing” “Electrical Requirements” AC Timing This section describes the AC timing characteristics of the LR4102 interface. Figures 3 and 4 show the EXTAL and TCK clocks. Figures 5 through 9 illustrate the input and output timing relationship with respect to various clocks (PBCLKP, SDCLKP, and DCLKP). Tables 6 through 14 list the minimum and maximum input and output values for the LR4102 interface signals. Note that all output signals have a 65 pF load. Figure 3 EXTAL 1 EXTAL Clock Timing Figure 4 TCK TCK Clock Timing 2 TinyRISC LR4102 Microprocessor 17 Figure 5 PBCLKP Input Timing with Respect to PBCLKP Input Setup Hold Note: PBCLKP equals the system clock (PCLKP) when the DIV C value in the Clock module is 0b01. DIV C = 0b01 is used to show timing for signals related to the system clock. The setting of DIV C only affects PBCLKP and the timing for signals related to the FAPI clock (PBCLKP). Figure 6 PBCLKP Output Timing with Respect to PBCLKP Output Min Output Max Output Figure 7 SDCLKP Input Timing with Respect to SDCLKP Input Setup Hold 18 TinyRISC LR4102 Microprocessor Figure 8 SDCLKP Output Timing with Respect to SDCLKP Output Min Output Max Output Figure 9 DCLK Output Timing with Respect to DCLK Output Min Output Max Output Table 6 EXTAL Input Timing Frequency Parameter 1 Input Signal EXTAL Clock Period 5.88 ns Min – Max 170 Units MHz Table 7 TCK Input Timing Frequency Parameter 2 Input Signal TCK Clock Period 11.76 ns Min – Max 85 Units MHz TinyRISC LR4102 Microprocessor 19 Table 8 AC Input Timing with respect to rising edge of PBCLKP1 Input Signal CBEN[3:0] DEVSELN FADP[31:0]3 FRAMEN GP[5:0]2 GPIO[3:0]2 IRDYN REQN STOPN TRDYN Setup 7.2 4.7 2.9 7.4 2.8 1.8 7.5 3.5 4.7 4.6 Hold 1.4 2.2 2.7 2.2 2.6 2.8 1.9 1.5 1.7 2.0 Units ns ns ns ns ns ns ns ns ns ns 1. With 65 pF load 2. This signal is related to the system clock, but not to the FAPI bus (see Figure 5 note). 3. This signal is related to both the system clock and the FAPI bus (see Figure 5 note). Table 9 AC Input Timing with respect to rising edge of SDCLKP1 Input Signal FADP[31:0] Setup 2.0 Hold 3.4 Units ns 1. With 65 pF load. Table 10 AC Input Timing with respect to rising edge of TCK Input TDI_DINT TMS Setup 1.9 1.6 Hold 1.1 0.7 Units ns ns 20 TinyRISC LR4102 Microprocessor Table 11 AC Output Timing with respect to rising edge of PBCLKP1 Output Signal1 CBEN[3:0] CWAITIP2 DEBUGMP DEVSELN FADDRP[28:0]2 FADP[31:0]3 FALEP FRAMEN GNTN GP[5:0]2 GPIO[3:0]2 GPRDN2 GPWEN[3:0]2 IRDYN RESET_OUTN2 Min 1.0 2.8 3.1 0.8 1.3 0.8 1.6 1.0 2.3 0.4 0.3 1.7 1.4 1.0 2.1 1.3 1.4 1.8 1.3 1.4 0.8 2.6 Max 8.0 8.8 9.3 7.2 6.2 7.4 6.1 7.5 7.0 7.0 6.8 5.8 6.2 7.5 7.3 6.0 5.9 6.4 5.9 5.7 7.2 8.8 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SD_CASN[3:0]_DMP[3:0]2 SD_OEN_CASN2 SDONEP SD_RASN[1:0]_CSN[1:0]2 SD_WEN_WEN2 STOPN T0_OUTN2 (Sheet 1 of 2) TinyRISC LR4102 Microprocessor 21 Table 11 AC Output Timing with respect to rising edge of PBCLKP1 (Cont.) Output Signal1 T1_OUTN2 TRDYN Min 2.7 0.8 Max 8.9 7.2 Units ns ns (Sheet 2 of 2) 1. With 65 pF load 2. This signal is related to the system clock, but not to the FAPI bus (see Figure 5 note). 3. This signal is related to both the system clock and the FAPI bus (see Figure 5 note). Table 12 AC Output Timing with respect to rising edge of SDCLKP1 Min 1.7 1.2 1.7 1.8 1.7 1.7 1.8 Max 6.9 8.3 6.9 6.6 6.4 6.8 6.6 Units ns ns ns ns ns ns ns Output Signal1 FADDRP[28:0] FADP[31:0] SD_CASN[3:0]_DMP[3:0] SD_OEN_CASN SD_RASN SD_RASN[1:0]_CSN[1:0] SD_WEN_WEN 1. With 65 pF load. Table 13 AC Output Timing with respect to falling edge of TCK Min 2.1 Max 8.9 Units ns Output Signal1 TDO_TPC 1. With 65 pF load 22 TinyRISC LR4102 Microprocessor Table 14 EZ4102 AC Output Timing with respect to rising edge of DCLK1 Min −2.9 −3.2 −3.2 Max 1.9 1.8 2.0 Units ns ns ns Output Signal1 PCST1[2:0] TDO_TPC TPC[4:2] 1. With 65 pF load. Note: there is no setup/hold time requirements for the interrupt pins, INTP[5:0], because they are synchronized internally within the LR4102. Electrical Requirements This section contains the electrical parameters for the TinyRISC LR4102 Microprocessor in the following tables: • • • • Table 15 lists the absolute maximum ratings Table 16 defines the recommended operating supply voltage and temperature Table 17 shows the pin capacitance Table 18 lists the DC characteristics Absolute Maximum Rating1 Parameter DC Supply Voltage2, core and oscillator 3.3 V DC Supply Voltage2, I/O 3.3 V Drive Input Voltage2 Storage Temperature Range (Plastic) Limits −0.3 to 3.1 −0.3 to 3.9 −1.0 to VDD4 + 0.3 −40 to 125 Unit V V V ˚C Table 15 Symbol VDD/DD2 VDD4 VIN TSTG 1. Exceeding these values may cause damage to the LR4102. 2. Referenced to VSS. TinyRISC LR4102 Microprocessor 23 Table 16 Symbol VDD/DD2 Recommended Operating Conditions Parameter DC Supply Voltage1 at VDD/VDD2 nominal 1.8 V at VDD/VDD2 nominal 2.5 V Ambient Temperature Limits Unit 1.71 to 1.89 2.38 to 2.63 0 to 70 V V ˚C TA 1. Referenced to VSS. Table 17 Symbol CIN COUT Capacitance Parameter Input Capacitance Output Capacitance Min 4.6 4.6 Typ – – Max 5.2 5.2 Unit pF pF Table 18 Symbol VDD4 VIL VIH IIL DC Characteristics Parameter Supply Voltage, I/O Voltage Input Low Voltage Input High Condition1 – – – Min 3.0 −0.5 2.0 Typ 3.3 – – Max 3.6 0.8 VDD4 + 0.3 10 222 −214 0.4 VDD4 100 – 10 Units V V V Current Input Leakage Inputs with no Pull-up/-down Resistor VIN = VSS/VDD4 Inputs with Pull-down Resistor VIN = VDD4 Inputs with Pull-up Resistor VIN = VSS Voltage Output Low Voltage Output High Quiescent Supply Current Dynamic Supply Current Z-state Output Leakage Current – – – – VOH = VSS/VDD4 −10 35 −35 – 2.4