LS7566

UL ® LSI/CSI LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 RS2 RS1 RS0 CHS1 CHS0 NC NC RD/ CS/ LS7566 (631) 271-0400 FAX (631) 271-0405 July 2005 A3800 24-BIT FOUR-AXES QUADRATURE COUNTER FEATURES: • Read/write registers for count and I/O modes. Count modes include: Non-quadrature (Up/Down), Quadrature (x1, x2, x4), Free-run, Non-recycle, Modulo-n and Range limit • Separate mode-control registers for each axis • Interrupt output and interrupt mask register. • 40 MHz count frequency, 5V 20 MHz count frequency, 3V • Sets of 24-bit counters, preset registers, comparators and output latches and 8-bit status registers for each axis • Digital filtering of the input quadrature clocks for noise immunity. • 3-state Octal I/O bus • 3V to 5.5V operating voltage range • LS7566-TS (TSSOP) -See Figure 1GENERAL DESCRIPTION: The LS7566 consists of four identical modules of 24-bit programmable counters with direct interface to incremental encoders. The modules can be configured to operate as quadratureclock counters or non-quadrature up/down counters. In both quadrature and non-quadrature modes, the modules can be further configured into free-running, non-recycle, modulo-n and range-limit count modes. The mode configuration is made through two 8-bit read/write addressable control registers, MDR0 and MDR1. Data can be ported to a 24-bit preset register PR, organized in directly addressable (write-only) byte0 [PR0] byte1 [PR1] and byte2 [PR2] segments. PR can be transferred to the 24-bit counter CNTR either by instruction to MDR1 or by hardware input control. A 24-bit digital comparator perpetually checks for the equality of the CNTR and the PR and can be used to set an output flag when the equality occurs. For reading the CNTR, its instantaneous value can be transferred to a 24-bit output latch OL, either by instruction to MDR1 or by hardware input control. The OL in turn can be read in directly addressable (read-only) byte0 [OL0], byte1 [OL1] and byte2 [OL2] segments. An addressable (read-only) Octal status register STR, stores the count related status information such as CNTR overflow, underflow, count direction etc. Data communication for read/write is performed through an Octal 3-state parallel I/O bus. REGISTER DESCRIPTION: PIN ASSIGNMENT - Top View 1 2 3 4 5 6 7 8 9 48 x0FLGa 47 x0FLGb 46 x1FLGa 45 INT/ 44 NC 43 GND 42 x1FLGb 41 x2FLGa 40 x2FLGb WR/ 10 DB0 11 DB1 12 DB2 13 DB3 14 DB4 15 DB5 16 DB6 17 DB7 18 NC 19 NC 20 PCK 21 GND 22 x0INDX 23 x0A 24 LSI LS7566 39 x3FLGa 38 x3FLGb 37 VDD 36 x3B 35 x3A 34 x3INDX 33 x2B 32 x2A 31 NC 30 NC 29 x2INDX 28 x1B 27 x1A 26 x1INDX 25 x0B Following is a list of the hardware registers. There are four sets of registers, with name prefixes x0 through x3 to refer to axes x0 through x3. FIGURE 1 The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. 7566-072205-1 PR (x0PR, x1PR, x2PR, x3PR) The PR is a 24-bit data register directly addressable for write in individual segments of byte0 [PR0], byte1 [PR1] and byte2 [PR2]. The PR serves as the input portal for the counter (CNTR), since the CNTR is not directly addressable for either read or write. In order to preset the CNTR to any desired value the data is first written into the PR and then transferred into the CNTR. B23------------------------------------------------------------B0 PR: PR2 PR1 PR0 B7----------------B0 B7-------------B0 B7--------------B0 STR (x0STR, x1STR, x2STR, x3STR): The STR is an 8-bit status register indicating count related status. STR: CY BW CMP IDX CEN 0 B7 B6 B5 B4 B3 U/D S B0 B2 B1 In mod-n and range-limit count modes the PR serves as the repository for the division factor n and the count range-limit, respectively. The PR can also be used to hold the compare data for the CNTR wherein the equality PR = CNTR sets an output flag. CNTR (x0CNTR, x1CNTR, x2CNTR, x3CNTR): The CNTR is a 24-bit up/down counter which counts the up/down pulses resulting from tthe quadrature clocks applied at A and B inputs or alternatively, in nonquadrature mode, pulses applied at the A input. The CNTR is not directly accessible for read or write; instead it can be preloaded with data from the PR or it can port its own data out to the OL which in turn can be accessed by read operation. In both quadrature and nonquadrature modes, the CNTR can be further configured into either free-running or single-cycle or mod-n or range-limit mode. OL (x0OL, x1OL, x2OL, x3OL): The OL is a 24-bit register directly addressable for read in individual segments of byte0 [OL1], byte1 [OL1] and byte2 [OL2]. OL serves as the output portal for the CNTR. Snapshot of the CNTR data can be loaded in the OL without interfering with the counting process, which then can be accessed by read. B23-----------------------------------------------------------B0 OL: OL2 OL1 OL0 An individual STR bit is set to 1 when the bit related event has taken place. The STR is cleared to 0 at power-up. The STR can also be cleared through the control register CMR with the exception of bit1 (U/D) and bit3 (CEN). These two STR bits always indicate the instantaneous status of the count_direction and count_enable assertion/de-assertion. The STR bits are described below: B7 (CY): Carry; set by CNTR overflow B6 (BW): Borrow; set by CNTR underflow B5 (CMP): Set when CNTR = PR B4 (IDX): Set when INDX input is at active level B3 (CEN): Set when counting is enabled, reset when counting is disabled B2 (0): Always 0 B1 (U/D): Set when counting up, reset when counting down B0 (S): Sign of count value; set when negative, reset when positive IMR: The IMR is a trans-axis global register used for masking out the interrupt function of individual axes. It is a 4-bit read/write register with the following bit assignments. IMR: B3 B0 B1 B2 B3 = 0: = 1: = 0: = 1: = 0: = 1: = 0: = 1: B2 B1 B0 disable axis 0 interrupt enable axis 0 interrupt disable axis 1 interrupt enable axis 1 interrupt disable axis 2 interrupt enable axis 2 interrupt disable axis 3 interrupt enable axis 3 interrupt B7----------------B0 B7-------------B0 B7--------------B0 A write to IMR places the lower nibble of the databus into the IMR with identical bit map. A read of IMR produces a joint read of IMR and ISR (interrupt status register), with IMR occupying the lower nibble and ISR occupying the upper nibble of the databus. 7566-112904-2 ISR: The ISR is a trans-axis global register used to hold the interrupt assertion status of all the axes. It is a 4-bit read-only register with the following bit assignment. CMR (x0CMR, x1CMR, x2CMR, x3CMR): The CMR is a write only register, which when written into, generates transient signals to perform load and reset operations as described below: CMR: B7 B6 B5 B4 B3 B2 B1 B0 ISR: B3 B0 B2 B1 B0 = 0: = 1: B1 = 0: = 1: B2 = 0: = 1: B3 = 0: = 1: axis_0 interrupt cleared axis_0 interrupt asserted axis_1 interrupt cleared axis_1 interrupt asserted axis_2 interrupt cleared axis_2 interrupt asserted axis_3 interrupt cleared axis_3 interrupt asserted An ISR bit gets set when the FLGa output of the associated axis switches low. For this reason, in order for the interrupt to be enabled for any axis, its associated FLGa output must be enabled. In addition, the associated IMR bit must also be set for the interrupt to be enabled. An individual ISR bit can be cleared through its axis relevant CMR register. The ISR is cleared upon power-up. A read of ISR produces a joint read of ISR and IMR (interrupt mask register) with ISR occupying the upper nibble and IMR occupying the lower nibble of the databus. B0 = 0: Nop = 1: Reset CNTR and sign to 0. (Should not be combinedwith load_CNTR operation). B1 = 0: Nop = 1: Load CNTR from PR. Affects all 24 bits. (Should not be combined with reset_CNTR operation) B2 = 0: Nop = 1: Load OL from CNTR. Affects all 24 bits. B3 = 0: Nop = 1: Reset STR. Affects status bits corresponding to carry, borrow, compare and index. Status bits corresponding to count_enable, count direction and sign are not affected. B4 = 0: Nop. 1: Master reset. Resets MDR0, MDR1, STR, CNTR, PR, OL, ISR and IMR B5 = 0: Nop 1: Set sign bit B6 = 0: Nop 1: Reset sign bit B7 = 0: Nop. 1: Reset ISR bit for the selected axis 7566-112904-3 MDR0 (x0MDR0, x1MDR0, x2MD0, x3MDR0): The MDR0 is an 8-bit read/write register which configures the counting modes and the index input functionality. Upon power-up, the MDR0 is cleared to zero. MDR0: B7 B6 B5 B4 B3 B2 B1 B0 B1B0 = 00: = 01: = 10: = 11: B3B2 = 00: = 01: = 10: = 11: Non-quadrature count mode (A = clock, B = direction). x1 quadrature count mode (one count per quadrature cycle). x2 quadrature count mode (two counts per quadrature cycle). x4 quadrature count mode (four counts per quadrature cycle). Free-running count mode. Single-cycle count mode (CNTR disabled with carry and borrow, re-enabled with reset or load) Range-limit count mode (up and down count ranges are limited between PR and zero, respectively. Counting freezes at these limits but resumes when the direction is reversed) Modulo-n count mode (input count clock frequency is divided by a factor of [n+1], where n = PR. In up direction, the CNTR is cleared to 0 at CNTR = PR and up count continues. In down direction, the CNTR is preset to the value of PR at CNTR = 0 and down count continues. A mod-n rollover marker pulse is generated at each limit at the FLGa output). Disable INDX input. Configure INDX input as the load CNTR input (transfers PR to CNTR). Configure INDX as the reset_CNTR input (clears CNTR to 0). Configure INDX as the load_OL input (transfers CNTR to OL). Negative INDX input. Positive INDX input. Input filter clock (PCK) division factor = 1. Filter clock frequency = fPCK. Input filter clock division factor = 2. Filter clock frequency = fPCK/2. B5B4 = 00: = 01: = 10: = 11: B6 = 0: = 1: B7 = 0: = 1: MDR1 (x0MDR1, x1MDR1, x2MD1, x3MDR1): The MDR1 is an 8-bit read/write register which configures the FLGa and FLGb output functionality. In addition, the MDR1 can be used to enable/disable counting. Upon power-up, the MDR1 is cleared to zero: MDR1: B7 B6 B5 B4 B3 B2 B1 B0 = 1: Enable Carry on FLGa (flags CNTR overflow; latched or unlatched logic low on carry). = 1: Enable Borrow on FLGa (flags CNTR underflow, latched or unlatched logic low on borrow). = 1: Enable Compare on FLGa (In free-running count mode, a latched or unlatched logic low is generated in both up and down count directions at CNTR = PR. In contrast, in range-limit and mod-n count modes a latched or unlatched low is generated at CNTR = PR in the up-count direction only. Also, in these two modes in the down-count direction, a latched or unlatched low is generated when the CNTR underflows. (See NOTE 2) B3 = 1: Enable index on FLGa (flags index, latched or unlatched logic low when INDX input is at active level) B5B4 = 00: FLGb disabled (fixed high) = 01: FLGb = Sign, high for negative signifying CNTR underflow, low for positive. = 10: FLGb = Up/Down count direction, high in count-up, low in count-down. B6 = 0: Enable counting. = 1: Disable counting. B7 = 0: FLGa is latched. (See NOTE 2) = 1: FLGa is non-latched and instantaneous. NOTE 1: Carry, Borrow, Compare and Index can all be simultaneously enabled on FLGa. NOTE 2: In mod-n or range-limit modes, if Compare output is enabled on FLGa, instantaneous (non-latched) Compare signals are generated at PR = CNTR in up-count mode and instantaneous Borrow signals are generated at CNTR = 0 in down-count mode, independent of the states of B7. Carry and Borrow signals on FLGa remain unaffected in these two modes. Consequently, a latched Carry or Index state willblock the instantaneous Compare and Borrow clocks. It is recommended that only non-latched Flag mode is used in the mod-n and range-limit modes if carry and index signals are enablrd on FLGa as well in these two modes. 7566-032305-4 B0 B1 B2 I/O PINS: The following is a description of the input/out pins. RSO(Pin 3), RS1 (Pin 2), RS2 (Pin1). Inputs. These three inputs select the hardware registers for read/write access according to Table 1. TABLE 1 CS/ 1 x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RS2 x x x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 x x x 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 x x x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RD/ x 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WR/ x 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 SELECTED REGISTER none none none [ISR:IMR] MDR0 MDR1 STR OL0 OL1 OL2 none IMR MDR0 MDR1 none PR0 PR1 PR2 CMR OPERATION none none none READ (see Note 2) READ READ READ READ READ READ none WRITE WRITE WRITE none WRITE WRITE WRITE WRITE Note 1. x indicates don’t care case. Note 2. DB0 through DB3 contain IMR B0 through B3; DB4 through DB7 contain ISR B0 through B3. CHS0 (Pin 5), CHS1 (Pin 4) Inputs. These two inputs select one of four axes for read/write access according to the following table. The registers within the axis are selected according to Table 1. TABLE 2 CHS1 0 0 1 1 CHS0 0 1 0 1 AXIS x0 x1 x2 x3 DB (Pin 18 thru Pin 11) Input/Output. The octal databus, DB, is the input/output portal for write and read data transfers between LS7566 and the outside world. During a read operation, when both CS/ and the RD/ inputs are low, DB are outputs. During a write operation, when both CS/ and WR/ are low, DB are inputs. When CS/ is high, DB are in high impedance state independent of the states of RD/ and WR/. PCK (Pin 21) Input. A clock applied at PCK input is used for validating the logic states of the A and B quadrature clocks and the INDX input. The PCK input frequency, fPCK, is divided down by a factor of 1 or 2 according to bit7 of MDR0. The resultant clock is used to sample the logic levels of the RD/ (Pin 8) Input. A low on RD/ input accesses an addressed register for read and places the data on the octal databus, DB. The register selection is made according to Table 1. CS/ (Pin 9) Input. A low on the CS/ input enables the chip for read or write operation. When the CS/ input is high, read and write operations are disabled and the databus, DB, is placed in a high impedance state. WR/ (Pin 10) Input. A low pulse on the WR/ input writes the data on the databus, DB, into the addressed register according to Table 1. The write operation is completed at the trailing edge of the WR/ pulse. 7566-112904-5 A, the B and the INDX inputs. If a logic level at any of these inputs remains stable for a minimum of two filter clock periods, it is validated as a correct logic state. The PCK input is common to all four axes, but the filter clock frequency for any axis is set by its associated MDR0 register. In non-quadrature mode no filter clock is used and the PCK input should be tied to either VDD or GND. x0A (pin 24), x0B (Pin 25) Inputs. These are the A and B count inputs in axis x0. These inputs can configured to function either in quadrature mode or in non-quadrature mode. The configuration is made through MDR0. In quadrature mode, A and B clocks are 90 degrees out of phase. When A leads B in phase, the CNTR counts up and when B leads A in phase, the CNTR counts down. In non-quadrature mode, A is the count input and B is the count direction control input. When B is high, positive transitions at the A input causes the CNTR to count up. Conversely, when B is low, the positive transition at the A input causes the CNTR to count down. In quadrature mode, A and B inputs are sampled by an internal filter clock generated from the PCK input. In nonquadrature mode A and B inputs are not sampled and the count clocks are applied to the CNTR bypassing the filter circuit. x1A (Pin 27), x1B (Pin 28), x2A (Pin 32), x2B (Pin33), x3A (Pin 35), x3B (Pin36) These are the A and B inputs corresponding to axes x1, x2 and x3. Functionally, they are identical with the A and B inputs of axis x0. x0INDX (Pin 23) Input. The INDX input in axis x0. The INDX input can be configured by MDR0 to function as load_CNTR or reset_CNTR or load_OL input. In quadrature mode the INDX input is sampled with the same filter clock used for sampling the A and the B inputs. In quadrature mode the INDX must satisfy the phase relationship with A and B in which INDX is at the active level during a minimum of quarter cycle of both A and B high or both A and B low. The active level can be configured to be either high (positive index) or low (negative index). In non-quadrature mode the INDX input is not sampled and can be applied in any phase relationship with respect to the A and B inputs. The INDX input can be either enabled or disabled in both quadrature and non-quadrature modes. x1INDX (Pin 26), x2INDX (Pin 29), x3INDX (Pin 34) These are the INDX inputs corresponding to axes x1, x2 and x3. Functionally, they are identical with the INDX input of axis x0. INT/ (Pin 45) Output The INT/ output is the common interrupt output for all the axes. When any of the ISR bits gets set, INT/ switches low indicating an asserted interrupt. The axis generating the interrupt can then be identified by reading the ISR register. x0FLGa (Pin 48) Output. The FLGa output in axis x0. The FLGa output is configured by MDR1 register to function as either Carry or Borrow or Compare flag. A Carry flag is generated when the CNTR overflows, a Borrow flag is generated when the CNTR underflows and a Compare flag is generated by the condition, CNTR = PR. The FLGa can be configured to produce outputs in either latched mode or instantaneous mode. In the latched mode when the selected event of Carry or Borrow or Compare has taken place, the FLGa switches low and remains low until the status register, STR is cleared. In the instantaneous mode a negative pulse is generated instantaneously when the event takes place. The FLGa output can be disabled to remain at a fixed logic high. x1FLGa (Pin 46), x2FLGa (Pin 41), x3FLGa (Pin 39) These outputs are the FLGa outputs corresponding to axes x1, x2 and x3, respectively. Functionally, they are identical with the FLGa output of axis x0. x0FLGb (Pin 47) Output. The FLGb output in axis x0. The FLGb output is configured by MDR1 to function as either Index or Sign or Up/Down status indicator. When configured as Sign, the FLGb output remains high when CNTR is in an underflow state (caused by down counts at or below zero), indicating a negative number. When the CNTR counts up past zero, FLGb switches low, indicating a positive number. When configured as Up/Down indicator, a high at the FLGb indicates that the current count direction is up (incremental) whereas a low indicates that the direction is down (decremental). The FLGb output can be disabled to remain at a fixed logic high. x1FLGb (Pin 42), x2FLGb (Pin 40) x3FLGb (Pin 38) These are the FLGb outputs corresponding to axes x1, x2 and x3 respectively. Functionally, they are identical with the FLGb output of x0. 7566-032205-6 Absolute Maximum Ratings: Parameter Symbol Voltage at any input VIN Supply Voltage VDD Operating Temperature TA Storage Temperature TSTG Values VSS - 0.3 to VDD + 0.3 +7.0 -25 to +85 -65 to +150 Unit V V oC oC DC Electrical Characteristics. (TA = -25˚C to +85˚C, VDD = 3V to 5.5V) Parameter Supply Voltage Supply Current Input Logic Low Input Logic High Output Low Voltage Output High Voltage Input Leakage Current Data Bus Leakage Current Data Bus Source Current Data Bus Sink Current FLGa, FLGb, INT/ Source FLGa, FLGb, INT/ Sink Symbol VDD IDD VIL VIH VOL VOH IILK IDLK IOSRC IOSNK IOSRC IOSNK Min. Value 3.0 0.5VDD VDD - 0.5 3.0 8.0 1.0 6.0 Max.Value 5.5 800 0.15VDD 0.5 30 60 Unit V µA V V V V nA nA mA mA mA mA Remarks All clocks off IOSNK = 5mA, VDD = 5V IOSRC = 1mA, VDD = 5V Data bus off VO = VDD - 0.5V, VDD = 5V VO = 0.5V, VDD = 5V VO = VDD - 0.5V, VDD = 5V VO = 0.5V, VDD = 5V Transient Characteristics. (TA = -25˚ to +85˚C) For VDD = 3V to 5.5V Parameter Symbol Min. Value Read Cycle (See Fig. 2) RD/ Pulse Width tr1 80 CS/ Set-up Time tr2 80 CS/ Hold Time tr3 0 RS Set-up Time tr4 80 RS Hold Time tr5 10 CHS Set-up Time tr6 80 CHS Hold Time tr7 10 DB AccessTime tr8 80 DB Release Time Back to Back Read delay Write Cycle (See Fig. 3) WR/ Pulse Width CS/ Set-up Time CS/ Hold Time RS Set-up Time RS Hold Time CHS Set-up Time CHS Hold Time DB Set-up Time DB Hold Time Back to Back Write Delay tr9 tr10 10 Max.Value 35 - Unit ns ns ns ns ns ns ns ns ns ns Remarks Access starts when both RD/ and CS/ are low. Release starts when either RD/ or CS/ is terminated. - tW1 tW2 tW3 tW4 tW5 tW6 tW7 tW8 tW9 tW10 45 45 0 45 10 45 10 45 10 90 - ns ns ns ns ns ns ns ns ns ns - 7566-032205-7 For VDD = 3.3V ± 10% Parameter Quadrature Mode (See Fig. 4-6) PCK High Pulse Width PCK Low Pulse Width PCK Frequency Filter Clock(ff)Period Symbol t1 t2 fpCK t3 t3 ff t4 t5 fQA, fQB tQ1 tQ2 tfda tfdb tnt tid tis tih tfw Min. Value 24 24 50 100 52 105 4t3 25 4.5t3 3t3 0 60 10 10 50 Max.Value 20 20 4.5 5t3 5.5t3 4t3 - Unit ns ns MHz ns ns MHz ns ns MHz ns ns ns ns ns ns ns ns Remarks t3 = t1+ t2, MDR0 = 0 t3 = t1+ t2, MDR0 = 1 ff = 1/t3 t4 > t3 t5 > 2t3 fQA = fQB t4 tfw ≈ t4 fA = (1/ (t6 + t7)) t10 = t7 Remarks ns ns MHz ns ns MHz ns ns MHz ns ns ns ns ns ns ns ns t3 = t1+ t2, MDR0 = 0 t3 = t1+ t2, MDR0 = 1 t4 > t3 t5 > 2t3 fQA = fQB < 1/4t3 tQ2 = t3/2 tid > t4 tfw ≈ t4 fA = (1/ (t6 + t7)) t10 = t7 - Filter clock frequency Quadrature Separation Quadrature Clock Pulse Width Quadrature Clock frequency Quadrature Clock to Count Delay x1 / x2 / x4 Count Clock Pulse Width Quadrature Clock to FLGa delay Quadrature Clock to FLGb delay FLGa to INT/ delay INDX Input Pulse Width INDX set-up time INDX hold time FLGa Output Width Non-Quadrature Mode (See Fig. 7-8) Clock A - High Pulse Width Clock A - Low Pulse Width Direction Input B Set-up Time Direction Input B Hold Time Clock Frequency Clock to FLGa Out Delay FLGa Out Pulse Width INDX Pulse Width For VDD = 5V ±10% Parameter Quadrature Mode (See Fig. 4-6) PCK High Pulse Width PCK Low Pulse Width PCK Frequency Filter Clock (ff) Period t6 t7 t8s t8 fA t9 t10 t11 24 24 24 20 24 30 Min. Value 12 12 25 50 26 52 4t3 12 4.5t3 3t3 0 32 5 5 24 20 40 Max.Value 40 40 9.6 5t3 5.5t3 4t3 Unit ns ns ns ns MHz ns ns ns Symbol t1 t2 fpCK t3 t3 ff t4 t5 fQA, fQB tQ1 tQ2 tfda tfdb tnt tid tis tih tfw Filter clock frequency Quadrature Separation Quadrature Clock Pulse Width Quadrature Clock frequency Quadrature Clock to Count Delay x1 / x2 / x4 Count Clock Pulse Width Quadrature Clock to FLGa delay Quadrature Clock to FLGb delay FLGa to INT/ delay INDX Input Pulse Width INDX set-up time INDX hold time FLGa Output Width Non-Quadrature Mode (See Fig. 7-8) Clock A - High Pulse Width Clock A - Low Pulse Width Direction Input B Set-up Time Direction Input B Hold Time Clock Frequency Clock to FLGa Out Delay FLGa Out Pulse Width INDX Pulse Width 7566-112904-8 t6 t7 t8 t8 fA t9 t10 t11 12 12 12 10 12 15 40 20 - ns ns ns ns MHz ns ns ns tr1 RD tr2 CS tr4 RS tr6 CHS tr8 DB tr9 VALID DATA tr10 tr3 tr5 tr7 VALID DATA FIGURE 2. READ CYCLE tw1 tw10 WR CS RS tw6 tw7 tw9 INPUT DATA tw2 tw4 tw5 tw3 CHS tw8 DB INPUT DATA FIGURE 3. WRITE CYCLE t1 PCK t2 t3 f f (Note 4) (MDR0 = 0) t3 t5 t4 t is Note 1 f f (Note 4) (MDR0 = 1) t5 t4 t ih t4 t is Note 2 A t4 t ih B INDX t id Note 1. Note 2. Note 3. Note 4. Positive index coincident with both A and B high. Positive index coincident with both A and B low. The index logic level in the above examples are inverted for negative index. fF is the internal effective filter clock. FIGURE 4. PCK, A, B and INDX 7566-032205-9 UP A B X4_CLK (see note) DOWN t Q1 X2_CLK (see note) t Q2 X1_CLK (see note) NOTE. x1, x2 and x4 CLKs are internal Up/Down clocks derived from filtered and decoded quadrature clocks. FIGURE 5. A/B QUADRATURE CLOCKS vs INTERNAL COUNT CLOCKS UP A B X4_CLK DOWN CNTR FLGa FLGb (up/dn) FLGb (sign) FFFFFC FFFFFD FFFFFE FFFFFF 000000 000001 000002 000001 000000 FFFFFF FFFFFE FFFFFD t fda CY (SHOWN WITH PR=000OO1) t fw CMP t fdb BW negative positive t nt INT/ NOTE. FLG is a non-latched mode. FIGURE 6. QUADRATURE CLOCKS vs FLGa, FLGb and INT/ OUTPUTS 7566-112904-10 DOWN UP DOWN B t6 A t7 t 8S t 8H FIGURE 7. COUNT (A) AND DIRECTION (B) INPUTS IN NON-QUADRATURE MODE B A (Shown with PR=2) CNTR FLGa FFFFFC FFFFFD FFFFFE FFFFFF 000000 000002 000001 000000 FFFFFF t9 CY t 10 CNTR ENABLED (load CNTR) CNTR DISABLED t 11 CNTR DISABLED INDX FIGURE 8. SINGLE-CYCLE, NON-QUADRATURE B A UP DOWN (Shown with PR=3) CNTR 000000 000001 000002 000003 000000 000001 000002 DFLAG/ 000001 000000 000003 000002 000001 CMP BW FIGURE 9. MODULO-N, NON-QUADRATURE B A UP DOWN (Shown with PR=3) CNTR 000000 000001 000002 FLGa 000003 000002 000001 000000 CMP CMP CMP CMP BW BW BW FIGURE 10. RANGE-LIMIT, NON-QUADRATURE 7566-112904-11 AXES_SLCT IN_BUS REG_RD REG_WR REG_RD CY, BW, CMP, INDX UP/DN,SIGN, CEN IMR (4) FLG0a OUT_BUS AND (4) FLAG_MASKS ISR MODE MUX DRV x0FLGb STR (8) OUT_BUS (4) AND-OR DRV x0FLGa FLG0a OR REG_WR DRV INT/ OUT_BUS AXES_SLCT MODE_CONTROLS FLAG_MASKS 2 PR0 (8) LD/RST_CNTR C O M P A R A T O R MDR1 (8) MDR0 (8) PR2 (8) PR1 (8) 24 UP/DN CLOCK COUNT MODE CONTROL CMP REG_RD CNTR (24) 24 CEN DB INPUT BUFFER & REGISTER IN_BUS 2 OL2 (8) OUT_BUS OL1 (8) OL0 (8) MARKER LOGIC CY, BW, SIGN RD/ WR/ CS/ INPUT BUFFER & RD/WR LOGIC READ OUTPUT BUFFER LD/RST_OL WRITE RS0 RS1 RS2 INPUT BUFFER & SELECT LOGIC REG_WR REG_RD (0) CMR POWER ON RESET ONE-SHOT CHS0 CHS1 INPUT BUFFER & SELECT LOGIC AXES_SLCT MODE PCK INPUT BUFFER AND DIVIDER FLTR_CK LOAD, SET & RESET PULSES FOR ALL REGISTERS x0A x0B x0INDX FILTER AND CLOCK COUNT & INDEX GENERATOR MODE CLOCK UP/DN CEN INDX FIGURE 11. LS7566 BLOCK DIAGRAM NOTE : For Clarity, only Axis0 is included 7566-112904-12 (8) IN_BUS ISA/EISA BUS IOW/ IOR/ WR/ RD/ D DB7 D DB6 D DB5 D DB4 D DB3 D DB2 D DB1 D DB0 A A A A A A A ADDRESS DECODE AEN LS7566 D PC RS2 RS1 RS0 CHS1 CHS0 CS/ FIGURE 12. LS7566 TO ISA / EISA INTERFACE R/W LDS RD/ WR/ D DB7 D DB6 DTACK/ MC68HC000 D D D DB5 D DB4 D DB3 D DB2 D DB1 D DB0 A A A A A A A A ADDRESS DECODE LS7566 RS2 RS1 RS0 CHS1 CHS0 CS/ FIGURE 13. LS7566 TO MC68HC000 INTERFACE 7566-112904-13