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IUHTXHQF\ï $FWLYDWð LQJ 7$26 FDXVHV 7326 DQG 71(* LQSXWV WR EH LJQRUHGï 7$26 LV LQKLELWHG GXULQJ 5HPRWH /RRSEDFNï 'LJLWDO 2XWSXWâ $, $QDORJ ,QSXWâ $2 $QDORJ 2XWSXWâ 6 6XSSO\ï (&ì ', ëé 6', (&ë ', ', ëè 6'2 '2 (&ê ', ëç CS ', 5/223 ', ëæ 6&/. //223 ', ', ', ëå &/.( 7$26 ', ìï (QWULHV LQ ,î2 FROXPQ DUHã ', 'LJLWDO ,QSXWâ '2 ëðéë L1 )XQFWLRQDO 'HVFULSWLRQ )81&7,21$/ '(6&5,37,21 7KH /;7êíè$ LV D IXOO\ LQWHJUDWHG 3&0 WUDQVFHLYHU IRU ERWK ìïèéé 0ESV õ'6;ðìô DQG ëïíéå 0ESV õ(ìô DSSOLFDð WLRQVï ,W DOORZV IXOOðGXSOH[ WUDQVPLVVLRQ RI GLJLWDO GDWD RYHU H[LVWLQJ WZLVWHGðSDLU LQVWDOODWLRQVï 7KH ILUVW SDJH RI WKLV GDWD VKHHW VKRZV D VLPSOLILHG EORFN GLDJUDP RI WKH /;7êíè$ï 7KH /;7êíè$ WUDQVFHLYHU LQWHUIDFHV ZLWK WZR WZLVWHGðSDLU OLQHV õRQH WZLVWHGðSDLU IRU WUDQVPLWñ RQH WZLVWHGðSDLU IRU UHFHLYHô WKURXJK VWDQGDUG SXOVH WUDQVIRUPHUV DQG DSSURSULDWH UHVLVWRUVï 5HFHLYHU The LXT305A receives the signal input from one twistedpair line on each side of a center-grounded transformer. Positive pulses are received at RTIP and negative pulses are received at RRING. Recovered data is output at RPOS and RNEG, and the recovered clock is output at RCLK. Refer to Test Specifications for LXT305A receiver timing. The signal received at RPOS and RNEG is processed through the peak detector and data slicers. The peak detector samples the inputs and determines the maximum value of the received signal. A percentage of the peak value is provided to the data slicers as a threshold level to ensure optimum signal-to-noise ratio. For T1 applications (determined by Equalizer Control inputs EC1 - EC3 ≠ 000 or 001) the threshold is set to 70% of the peak value. This threshold is maintained above 65% for up to 15 successive zeros over the range of specified operating conditions. For E1 applications (EC inputs = 000 or 001) the threshold is 50%. The receiver is capable of accurately recovering signals with up to -13.6 dB of attenuation (from 2.4 V), corresponding to a received signal level of approximately 500 mV. Maximum line length is 1500 feet of ABAM cable (approximately 6 dB of attenuation). Regardless of received signal level, the peak detectors are held above a minimum level of .3 V to provide immunity from impulsive noise. After processing through the data slicers, the received signal is routed to the data and clock recovery sections, and to the receive monitor. The data and clock recovery circuits are highly tolerant with an input jitter tolerance significantly better than required by Pub 62411. Refer to Test Specifications for additional information. The receiver monitor loads a digital counter at the RCLK frequency. The count is incremented each time a zero is received, and reset to zero each time a one (mark) is received. Upon receipt of 175 consecutive zeros the LOS pin goes High, and a smooth transition replaces the RCLK output with the MCLK. Received marks are output regardless of the LOS status, but the LOS pin will not reset until the ones density reaches 12.5%. This level is based on receipt of at least 4 ones in any 32-bit period with no more than 15 consecutive zeros. 3RZHU 5HTXLUHPHQWV 7KH /;7êíè$ LV D ORZðSRZHU &026 GHYLFHï ,W RSHUDWHV IURP D VLQJOH òè 9 SRZHU VXSSO\ ZKLFK FDQ EH FRQQHFWHG H[WHUQDOO\ WR ERWK WKH WUDQVPLWWHU DQG UHFHLYHUï +RZHYHUñ WKH WZR LQSXWV PXVW EH ZLWKLQ ‘ ïê9 RI HDFK RWKHUñ DQG GHFRXSOHG WR WKHLU UHVSHFWLYH JURXQGV VHSDUDWHO\ï 5HIHU WR $SSOLFDWLRQ ,QIRUPDWLRQ IRU W\SLFDO GHFRXSOLQJ FLUFXLWU\ï ,VRODWLRQ EHWZHHQ WKH WUDQVPLW DQG UHFHLYH FLUFXLWV LV SURð YLGHG LQWHUQDOO\ï 7KH WUDQVPLWWHU SRZHUV GRZQ WR FRQVHUYH SRZHU ZKHQ WKH UHTXLUHG FORFN LQSXW LV QRW VXSSOLHGï 7KH /;7êíè$ HQWHUV WKH SRZHU GRZQ PRGH GXULQJ QRUPDO RSHUDWLRQ DQG ORFDO ORRSEDFN LI 7&/. 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LV XVHG DV WKH WUDQVPLWWHU UHIHUHQFH FORFNï 7KH WUDQVFHLYHU FDQ DOVR EH UHVHW IURP WKH +RVW RU +DUGð ZDUH 0RGHï ,Q +RVW 0RGHñ UHVHW LV FRPPDQGHG E\ VLPXOð WDQHRXVO\ ZULWLQJ 5/223 DQG //223 WR WKH UHJLVWHUï ,Q +DUGZDUH 0RGHñ UHVHW LV FRPPDQGHG E\ KROGLQJ 5/223 DQG //223 +LJK VLPXOWDQHRXVO\ IRU ëíí QVï 5HVHW LV LQLð WLDWHG RQ WKH IDOOLQJ HGJH RI WKH UHVHW UHTXHVWï ,Q HLWKHU PRGHñ UHVHW FOHDUV DQG VHWV DOO UHJLVWHUV WR í DQG WKHQ EHJLQV FDOLEUDWLRQï L1 ëðéê /;7êíè$ ,QWHJUDWHG 7ìî(ì 6KRUWð+DXO 7UDQVFHLYHU ZLWK 7UDQVPLW -$ 7UDQVPLWWHU Data received for transmission onto the line is clocked serially into the device at TPOS and TNEG. Input synchronization is supplied by the transmit clock (TCLK). The transmitted pulse shape is determined by Equalizer Control signals EC1 through EC3 as shown in Table 4. Refer to Test Specifications for master and transmit clock timing characteristics. Shaped pulses are applied to the AMI line driver for transmission onto the line at TTIP and TRING. Equalizer Control signals may be hardwired in the Hardware Mode, or input as part of the serial data stream (SDI) in the Host Mode Pulses can be shaped for either 1.544 or 2.048 Mbps applications. 1.544 Mbps pulses for DSX-1 applications can be programmed to match line lengths from 0 to 655 feet of ABAM cable. The LXT305A also matches FCC and ECSA specifications for CSU applications. 2.048 Mbps pulses can drive coaxial or shielded twisted-pair lines. racy). Series resistors also provide increased surge protection and reduced short circuit current flow. )LJXUH ëã èíø $0, &RGLQJ %LW &HOO 77,3 ì 75,1* í ì 7DEOH ëã /;7êíè$ 6HULDO 'DWD 2XWSXW %LWV õ6HH )LJXUH éô %LW 'è í í í í ì ì ì ì %LW 'ç í í ì ì í í ì ì %LW 'æ í ì í ì í ì í ì 6WDWXV 5HVHW KDV RFFXUUHGñ RU QR SURJUDP LQSXWï 7$26 LV DFWLYHï /RFDO /RRSEDFN LV DFWLYHï 7$26 DQG /RFDO /RRSEDFN DUH DFWLYHï 5HPRWH /RRSEDFN LV DFWLYHï '30 KDV FKDQJHG VWDWH VLQFH ODVW &OHDU '30 RFFXUUHGï /26 KDV FKDQJHG VWDWH VLQFH ODVW &OHDU /26 RFFXUUHGï /26 DQG '30 KDYH ERWK FKDQJHG VWDWH VLQFH ODVW &OHDU '30 DQG &OHDU /26 RFFXUUHGï -LWWHU $WWHQXDWLRQ Jitter attenuation of the LXT305A transmit outputs is provided by a Jitter Attenuation Loop (JAL) and an Elastic Store (ES). An external crystal oscillating at 4 times the bit rate provides clock stabilization. Refer to Application Information for crystal specifications. The ES is a 32 x 2bit register. Transmit data is clocked into the ES with the transmit clock (TCLK) signal, and clocked out of the ES with the dejittered clock from the JAL. When the bit count in the ES is within two bits of overflowing or underflowing, the ES adjusts the output clock by 1/8 of a bit period. The ES produces an average delay of 16 bits in the receive path. 'ULYHU 3HUIRUPDQFH 0RQLWRU 7KH WUDQVFHLYHU LQFRUSRUDWHV D 'ULYHU 3HUIRUPDQFH 0RQLð WRU õ'30ô LQ SDUDOOHO ZLWK 77,3 DQG 75,1* DW WKH RXWSXW WUDQVIRUPHUï 7KH '30 RXWSXW JRHV +LJK XSRQ GHWHFWLRQ RI çê FRQVHFXWLYH ]HURVï ,W LV UHVHW ZKHQ D RQH LV GHWHFWHG RQ WKH WUDQVPLW OLQHñ RU ZKHQ D UHVHW FRPPDQG LV UHFHLYHGï 2SHUDWLQJ 0RGHV The LXT305A can be controlled through hard-wired pins (Hardware Mode) or by a microprocessor through a serial interface (Host Mode). The mode of operation is set by the MODE pin logic level. The LXT305A can also be commanded to operate in one of several diagnostic modes. /LQH &RGH The LXT305A transmits data as a 50% AMI line code as shown in Figure 2. The output driver maintains a constant low output impedance regardless of whether it is driving marks or spaces. This well controlled output impedance provides excellent return loss (> 18 dB) when used with external 9.1 ″ precision (± 1 % accuracy) in series with a transmit transformer with a turns ratio of 1:2.3 (± 2% accu- ëðéé L1 )XQFWLRQDO 'HVFULSWLRQ +RVW 0RGH 2SHUDWLRQ To allow a host microprocessor to access and control the LXT305A through the serial interface, MODE is set High. The serial interface (SDI/SDO) uses a 16-bit word consisting of an 8-bit Command/Address byte and an 8-bit Data byte. Figure 3 shows the serial interface data structure and relative timing. The Host Mode provides a latched Interrupt output (INT) which is triggered by a change in the Loss of Signal (LOS) and/or Driver Performance Monitor (DPM) bits. The Interrupt is cleared when the interrupt condition no longer exists, and the host processor enables the respective bit in the serial input data byte. Host Mode also allows control of )LJXUH êã /;7êíè$ 6HULDO ,QWHUIDFH 'DWD 6WUXFWXUH CS SCLK the serial data and receive data output timing. The Clock Edge (CLKE) signal determines when these outputs are valid, relative to the Serial Clock (SCLK) or RCLK as listed in Table 3. 7DEOH êã 9DOLG &/.( 6HWWLQJV &/.( /RZ 2XWSXW 5326 51(* 6'2 5326 51(* 6'2 &ORFN 5&/. 5&/. 6&/. 5&/. 5&/. 6&/. 9DOLG (GJH 5LVLQJ 5LVLQJ )DOOLQJ )DOOLQJ )DOOLQJ 5LVLQJ +LJK ï ADDRESS / COMMAND BYTE DATA INPUT / OUTPUT BYTE SDI/ SDO R/W A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 ADDRESS / COMMAND BYTE R/W 0 A0 0 0 0 1 A4 0 X A6 R/W- = 1: Read R/W- = 0: Write 127( 2XWSXW GDWD E\WH LV WKH VDPH DV WKH LQSXW GDWD E\WH H[FHSW IRU ELWV 'áèãæ! VKRZQ LQ 7DEOH ëï CLEAR INTERRUPTS INPUT DATA BYTE X=DON’T CARE SET LOOPBACKS OR RESET LOS D0 (LSB) DFM EC1 EC2 EC3 REMOTE LOCAL TAOS D7(MSB) 7DEOH éã (TXDOL]HU &RQWURO ,QSXWV (&ê í ì ì ì ì í í í (&ë ì í í ì ì í í ì (&ì ì í ì í ì í ì í /LQH /HQJWKì &DEOH /RVVë $SSOLFDWLRQ %LW 5DWH í a ìêê IW $%$0 íïç G% ìêê a ëçç IW $%$0 ìïë G% ëçç a êää IW $%$0 ìïå G% êää a èêê IW $%$0 ëïé G% èêê a çèè IW $%$0 êïí G% ,78 5HFRPPHQGDWLRQ *ïæíê )&& 3DUW çåñ 2SWLRQ $ '6;ðì (ì ð &RD[ õæè Ωô (ì ð 7ZLVWHGðSDLU õìëí Ωô &68 õ'6ðìô ìïèéé 0ESV ëïíéå 0ESV ìïèéé 0ESV L1 ëðéè /;7êíè$ ,QWHJUDWHG 7ìî(ì 6KRUWð+DXO 7UDQVFHLYHU ZLWK 7UDQVPLW -$ The LXT305A serial port is addressed by setting bit A4 in the Address/Command byte, corresponding to address 16. The LXT305A contains only a single output data register so no complex chip addressing scheme is required. The register is accessed by causing the Chip Select (CS) input to transition from High to Low. Bit 1 of the serial Address/ Command byte provides Read/Write control when the chip is accessed. A logic 1 indicates a read operation, and a logic 0 indicates a write operation. Table 2 lists serial data output bit combinations for each status. Serial data I/O timing characteristics are shown in the Test Specifications section. 'LDJQRVWLF 0RGH 2SHUDWLRQ 7UDQVPLW $OO 2QHV ,Q 7UDQVPLW $OO 2QHV õ7$26ô 0RGH WKH 7326 DQG 71(* LQSXWV WR WKH WUDQVFHLYHU DUH LJQRUHGï 7KH WUDQVð FHLYHU WUDQVPLWV D FRQWLQXRXV VWUHDP RI RQHV ZKHQ WKH 7$26 PRGH LV DFWLYDWHGï 7$26 FDQ EH FRPPDQGHG VLPXOWDQHRXVO\ ZLWK /RFDO /RRSEDFNñ EXW LV LQKLELWHG GXULQJ 5HPRWH /RRSEDFNï 'XULQJ 7$26ñ WKH WUDQVð PLWWHU LV ORFNHG WR 0&/.ï ,I 0&/. LV QRW VXSSOLHGñ WKH WUDQVPLWWHU SRZHUV GRZQï ,Q 5HPRWH /RRSEDFN õ5/223ô 0RGHñ WKH WUDQVPLW GDWD DQG FORFN LQSXWV õ7326ñ 71(* DQG 7&/.ô DUH LJQRUHGï 7KH 5326 DQG 51(* RXWSXWV DUH ORRSHG EDFN WKURXJK WKH WUDQVPLW FLUFXLWV DQG RXWSXW RQ 77,3 DQG 75,1* DW WKH 5&/. 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Includes device and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load. 2. Functionality of pins 23 and 25 depends on mode. See Host/Hardware Mode descriptions. 3. Output drivers will output CMOS logic levels into CMOS loads. 4. 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