LXT304A

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LV XVHG DV WKH UHFHLYHU UHIHUHQFH FORFNï 7KH WUDQVFHLYHU FDQ DOVR EH UHVHW IURP WKH +RVW RU +DUGð ZDUH 0RGHï ,Q +RVW 0RGHñ UHVHW LV FRPPDQGHG E\ VLPXOð WDQHRXVO\ ZULWLQJ 5/223 DQG //223 WR WKH UHJLVWHUï ,Q +DUGZDUH 0RGHñ UHVHW LV FRPPDQGHG E\ KROGLQJ 5/223 DQG //223 +LJK VLPXOWDQHRXVO\ IRU ëíí QVï 5HVHW LV LQLð WLDWHG RQ WKH IDOOLQJ HGJH RI WKH UHVHW UHTXHVWï ,Q HLWKHU PRGHñ UHVHW FOHDUV DQG VHWV DOO UHJLVWHUV WR í DQG WKHQ EHJLQV FDOLEUDWLRQï 5HFHLYHU 7KH /;7êíé$ UHFHLYHV WKH VLJQDO LQSXW IURP RQH WZLVWHGð SDLU OLQH RQ HDFK VLGH RI D FHQWHUðJURXQGHG WUDQVIRUPHUï 3RVLWLYH SXOVHV DUH UHFHLYHG DW 57,3 DQG QHJDWLYH SXOVHV -LWWHU $WWHQXDWLRQ Jitter attenuation of the LXT304A clock and data outputs is provided by a Jitter Attenuation Loop (JAL) and an Elastic Store (ES). An external crystal oscillating at 4 times the bit rate provides clock stabilization. Refer to Application Information for crystal specifications. The ES is a 32 x 2- L1 ëðëè /;7êíé$ /RZð3RZHU 7ìî(ì 6KRUWð+DXO 7UDQVFHLYHU bit register. Recovered data is clocked into the ES with the recovered clock signal, and clocked out of the ES with the dejittered clock from the JAL. When the bit count in the ES is within two bits of overflowing or underflowing, the ES adjusts the output clock by 1/8 of a bit period. The ES produces an average delay of 16 bits in the receive path. (&6$ VSHFLILFDWLRQV IRU &68 DSSOLFDWLRQVï $ ìãìïìè WUDQVð PLW WUDQVIRUPHU LV XVHG IRU ìïèéé 0ESV V\VWHPVï )RU KLJKHU UHWXUQ ORVV LQ '6;ðì DSSOLFDWLRQVñ XVH äïì Ω UHVLVð WRUV LQ VHULHV ZLWK D ìãëïê WUDQVPLW WUDQVIRUPHUï ëïíéå 0ESV SXOVHV FDQ GULYH FRD[LDO RU VKLHOGHG WZLVWHGð SDLU OLQHVï )RU (ì V\VWHPVñ D ìãë WUDQVPLW WUDQVIRUPHU DQG VHULHV UHVLVWRUV DUH UHFRPPHQGHGï 7KLV GHVLJQ PHHWV RU H[FHHGV DOO ,78 DQG (76, VSHFLILFDWLRQV IRU WUDQVPLW DQG UHFHLYH UHWXUQ ORVVï $ ìãì RU ìãìïëç WUDQVIRUPHU PD\ EH XVHG ZLWKRXW VHULHV UHVLVWRUVï 7UDQVPLWWHU 'DWD UHFHLYHG IRU WUDQVPLVVLRQ RQWR WKH OLQH LV FORFNHG VHULð DOO\ LQWR WKH GHYLFH DW 7326 DQG 71(*ï ,QSXW V\QFKURQLð ]DWLRQ LV VXSSOLHG E\ WKH WUDQVPLW FORFN õ7&/.ôï ,I 7&/. LV QRW VXSSOLHG WKH WUDQVPLWWHU UHPDLQV SRZHUHG GRZQñ H[FHSW GXULQJ UHPRWH ORRSEDFNï 5HIHU WR 7HVW 6SHFLILFDð WLRQV IRU PDVWHU DQG WUDQVPLW FORFN WLPLQJ FKDUDFWHULVWLFVï 7KH WUDQVPLWWHG SXOVH VKDSH LV GHWHUPLQHG E\ (TXDOL]HU &RQWURO VLJQDOV (&ì WKURXJK (&ê DV VKRZQ LQ 7DEOH ëï (TXDOL]HU &RQWURO VLJQDOV PD\ EH KDUGZLUHG LQ WKH +DUGð ZDUH PRGHñ RU LQSXW DV SDUW RI WKH VHULDO GDWD VWUHDP õ6',ô LQ WKH +RVW PRGHï 6KDSHG SXOVHV DUH DSSOLHG WR WKH $0, OLQH GULYHU IRU WUDQVPLVVLRQ RQWR WKH OLQH DW 77,3 DQG 75,1*ï 7KH OLQH GULYHU SURYLGHV D FRQVWDQW ORZ RXWSXW LPSHGDQFH RI ê Ω õW\SLFDOôï 7KLV ZHOO FRQWUROOHG RXWSXW LPSHGDQFH SURYLGHV H[FHOOHQW UHWXUQ ORVV õ! ìå G%ô ZKHQ XVHG ZLWK H[WHUQDO äïì Ω SUHFLVLRQ UHVLVWRUV õ‘ ìø DFFXð UDF\ô LQ VHULHV ZLWK D WUDQVPLW WUDQVIRUPHU ZLWK D WXUQV UDWLR RI ìãëïê õ‘ ëø DFFXUDF\ôï 6HULHV UHVLVWRUV DOVR SURYLGH LQFUHDVHG VXUJH SURWHFWLRQ DQG UHGXFH VKRUW FLUFXLW FXUUHQW IORZï 3XOVHV FDQ EH VKDSHG IRU HLWKHU ìïèéé RU ëïíéå 0ESV DSSOLð FDWLRQVï ìïèéé 0ESV SXOVHV IRU '6;ðì DSSOLFDWLRQV FDQ EH SURJUDPPHG WR PDWFK OLQH OHQJWKV IURP í WR çèè IHHW RI $%$0 FDEOHï 7KH /;7êíé$ DOVR PDWFKHV )&& DQG 7DEOH ëã (TXDOL]HU &RQWURO ,QSXWV (&ê í ì ì ì ì í í í (&ë ì í í ì ì í í ì (&ì ì í ì í ì í ì í /LQH /HQJWKì í a ìêê IW $%$0 ìêê a ëçç IW $%$0 ëçç a êää IW $%$0 êää a èêê IW $%$0 èêê a çèè IW $%$0 'ULYHU 3HUIRUPDQFH 0RQLWRU The transceiver incorporates a Driver Performance Monitor (DPM) in parallel with TTIP and TRING at the output transformer. The DPM output goes High upon detection of 63 consecutive zeros. It is reset when a one is detected on the transmit line, or when a reset command is received. /LQH &RGH The LXT304A transmits data as a 50% AMI line code as shown in Figure 2. The output driver maintains a constant low output impedance regardless of whether it is driving marks or spaces. 2SHUDWLQJ 0RGHV The LXT304A can be controlled through hard-wired pins (Hardware Mode) or by a microprocessor through a serial interface (Host Mode). The mode of operation is set by the MODE pin logic level. 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The Interrupt is cleared when the interrupt condition no longer exists, and the host processor enables the respective bit in the serial input data byte. Host Mode also allows control of the serial data and receive data output timing. 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VKRZQ LQ 7DEOH éï CLEAR INTERRUPTS INPUT DATA BYTE X=DON’T CARE SET LOOPBACKS OR RESET LOS D0 (LSB) DFM EC1 EC2 EC3 REMOTE LOCAL TAOS D7(MSB) ëðëå L1 )XQFWLRQDO 'HVFULSWLRQ 7DEOH èã /;7êíé$ &U\VWDO 6SHFLILFDWLRQV õ([WHUQDOô 3DUDPHWHU )UHTXHQF\ )UHTXHQF\ VWDELOLW\ 7ì (ì åïìäë 0+] ‘ ëí SSP # ëè ƒ& ‘ ëè SSP IURP ðéí ƒ& WR òåè ƒ& õ5HI ëè ƒ& UHDGLQJô &/ ìì S) WR ìåïæ S)ñ ò∆) äè WR ììè SSP &/ ìåïæ S) WR êé S)ñ ð∆) äè WR ììè SSP êí Ω 0D[LPXP $7 3DUDOOHO ëïí P: )XQGDPHQWDO +&éä õ5ê:ôñ &2 æ S) PD[LPXP &0 ìæ I) W\SLFDO çïìæç 0+] ‘ ëí SSP # ëè ƒ& ‘ ëè SSP IURP ðéí ƒ& WR åè ƒ& õ5HI ëè ƒ& UHDGLQJô 3XOODELOLW\ &/ ìì S) WR ìåïæ S)ñ ò∆) ìæè WR ìäè SSP &/ ìåïæ S) WR êé S)ñ ð∆) ìæè WR ìäè SSP (IIHFWLYH VHULHV UHVLVWDQFH éí Ω 0D[LPXP &U\VWDO FXW $7 5HVRQDQFH 3DUDOOHO 0D[LPXP GULYH OHYHO ëïí P: 0RGH RI RSHUDWLRQ )XQGDPHQWDO &U\VWDO KROGHU +&éä õ5ê:ôñ &2 æ S) PD[LPXP &0 ìæ I) W\SLFDO L1 ëðëä /;7êíé$ /RZð3RZHU 7ìî(ì 6KRUWð+DXO 7UDQVFHLYHU IUDPHU SURYLGLQJ WKH GLJLWDO LQWHUIDFH ZLWK WKH KRVW FRQWUROð OHUï %RWK GHYLFHV DUH FRQWUROOHG WKURXJK WKH VHULDO LQWHUIDFHï $Q /;3çíí$ &ORFN $GDSWHU õ&/$'ô SURYLGHV WKH ëïíéå 0+] V\VWHP EDFNSODQH FORFNñ ORFNHG WR WKH UHFRYHUHG ìïèéé 0+] FORFN VLJQDOï 7KH SRZHU VXSSO\ LQSXWV DUH WLHG WR D FRPPRQ EXV ZLWK DSSURSULDWH GHFRXSOLQJ FDSDFLWRUV LQVWDOOHG õçå “) RQ WKH WUDQVPLW VLGHñ ìïí “) DQG íïì “) RQ WKH UHFHLYH VLGHôï $33/,&$7,21 ,1)250$7,21 ìïèéé 0ESV 7ì ,QWHUIDFH $SSOLFDWLRQ )LJXUH é LV D W\SLFDO ìïèéé 0ESV 7ì DSSOLFDWLRQï 7KH /;7êíé$ LV VKRZQ LQ WKH +RVW 0RGH ZLWK D 7ìî(6) )LJXUH éã 7\SLFDO /;7êíé$ ìïèéé 0ESV 7ì $SSOLFDWLRQ õ+RVW 0RGHô òè9 0RGH 0&/. 6&/. CS INT 6', 6'2 75,1* µ3 6HULDO 3RUW &F 5W éæíì S) 5W 7U 7UDQVPLW /LQH &RQWURO DQG 0RQLWRU &/.( 0&/. /26 '30 /;7êíé$ 77,3 )UDPHU 7326 71(* 7&/. 5326 51(* 5&/. 05,1* 07,3 57,3 5U 5U 55,1* 5HFHLYH /LQH ë&7ãì /;3çíí$ ;7$/287 ;7$/,1 &/., CLKO FSI 2.048 MHz 5*1' 7*1' 59ò 79ò NOTE íïì µ) ìïí µ) òè9 çå µ) ìï 7\SLFDO YDOXH éæí S)ï $GMXVW IRU DFWXDO ERDUG SDUDVLWLFV WR REWDLQ RSWLð PXP UHWXUQ ORVVï ëðêí L1 $SSOLFDWLRQ ,QIRUPDWLRQ ëïíéå 0ESV (ì ,QWHUIDFH $SSOLFDWLRQV Figure 5 is a 2.048 Mbps E1 TWP application using 15 Ω Rt resistors in line with the transmit transformer to provide high return loss and surge protection. When high return loss is not a critical factor, a 1:1 or 1:1.26 transformer without in-line resistors provides maximum power savings. The LXT304A is shown in Hardware Mode with a typical E1/ CRC4 Framer. The hard-wired control lines for TAOS, LLOOP and RLOOP are individually controllable, and the LLOOP and RLOOP lines are also tied to a single control for the Reset function. This configuration is illustrated with a crystal in place to enable the LXT304A Jitter Attenuation Loop, and a single power supply bus. )LJXUH èã 7\SLFDO /;7êíé$ (ì ëïíéå 0ESV ìëí Ω $SSOLFDWLRQ õ+DUGZDUH 0RGHô 0RGH 0&/. (&ì EC2 EC2 /LQH /HQJWK VHWWLQJ &RQWURO DQG 0RQLWRU 7$26 5/223 //223 /26 '30 &F 77,3 /;7êíé$ 75,1* 07,3 05,1* 57,3 5W õìèΩô éæíì S) 5W õìèΩô 7U 7UDQVPLW /LQH )UDPHU 7326 71(* 7&/. 5326 51(* 5&/. 5U 5U 55,1* 5HFHLYH /LQH ë&7ãì /;3çíí$ ;7$/287 ;7$/,1 CLKO &/., FSI 1.544 MHz 5*1' 7*1' 59ò 79ò NOTE íïì µ) ìïí µ) òè9 çå µ) ìï 7\SLFDO YDOXH éæí S)ï $GMXVW IRU DFWXDO ERDUG SDUDVLWLFV WR REWDLQ RSWLð PXP UHWXUQ ORVVï L1 ëðêì /;7êíé$ /RZð3RZHU 7ìî(ì 6KRUWð+DXO 7UDQVFHLYHU 'é &KDQQHO %DQN $SSOLFDWLRQV Existing D4 Channel Bank architectures frequently employ: (1) a plug-in card for T1 pulse generation (6.0 V peak); and (2) a separate card for pulse shaping and Line Build-Out (LBO). The LXT304A integrates the functions of both cards on a single chip producing a DSX-1 compatible, 3.0 V peak output pulse with a standard transformer. In new designs, the LXT304A can replace two cards with one. However, the LXT304A is also compatible with ex7DEOH çã 7ìî(ì ,QSXWî2XWSXW &RQILJXUDWLRQV %LW 5DWH õ0ESVô ìïèéé õ7ìô &U\VWDO ;7$/ &DEOH õΩô 5Uë õ Ωô ëíí (&êîëîì isting dual-card architectures. With an appropriate output transformer, the LXT304A can produce full 6.0 V peak amplitude pulses suitable for D4 Channel Bank applications with separate pulse shaping/LBO cards. To achieve the 6.0 V peak output, the FCC Part 68-010 Equalizer Code setting is used. (EC = 010.) With the standard 1:1.15 transformer, this code produces a 3.0 V peak pulse. However, doubling the transformer turns ratio to 1:2.30 produces the desired 6.0 V peak pulse. 7UDQVPLW 7UDQVIRUPHUì õ7Uô ìãìïìè ìãë ìãëïê ìãëïê ìãìïëç ìãë ìãì ìãë ìãì ìãë ìãì ìãë 5Wë õ Ωô í äïì äïì í í äïì í ìïè í äïì ìí ìéïê 7\SLFDO 7; 5HWXUQ /RVVê õG%ô íïè ìå ìå íé íïè ìë íïè ìå íïè ìå è ìí &F õµ)ô íïéæ í í íïéæ íïéæ í íïéæ í íïéæ í í í /;&çìæç ìíí íîìîì ð ìîìîì íîìîíé ëïíéå õ(ìô /;&åìäë ìëí ëéí íîíîí íîíîí íîíîì íîíîì íîíîí íîíîí íîíîì íîíîì æè ìèí 1. Transformer turns ratio accuracy is ± 2%. 2. Rr and Rt values are ± 1%. 3. Typical return loss, 51 kHz to 3.072 MHz band. 4. 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Includes device and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load. 2. Functionality of pins 23 and 25 depends on mode. See Host/Hardware Mode descriptions. 3. Output drivers will output CMOS logic levels into CMOS loads. 4. Except MTIP and MRING ILL = ± 50 µA. L1 ëðêê /;7êíé$ /RZð3RZHU 7ìî(ì 6KRUWð+DXO 7UDQVFHLYHU 7DEOH äã (OHFWULFDO &KDUDFWHULVWLFV õ8QGHU 5HFRPPHQGHG 2SHUDWLQJ &RQGLWLRQVô ¤ FRQWLQXHG 3DUDPHWHU /RZ OHYHO RXWSXW YROWDJHëñê õSLQV çðåñ ììñ ìëñ ëêñ ëèô ,QSXW OHDNDJH FXUUHQW é ë 6\P 92/ ,// ,ê/ 0LQ ¤ ðìí ðìí 0D[ íïé òìí òìí 8QLWV 9 µ$ µ$ 7HVW &RQGLWLRQV ,287 ìïç P$ 7KUHHðVWDWH OHDNDJH FXUUHQW õSLQ ëèô ìï Power dissipation while driving 75 Ω load over operating temperature range. Includes device and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load. 2. Functionality of pins 23 and 25 depends on mode. See Host/Hardware Mode descriptions. 3. Output drivers will output CMOS logic levels into CMOS loads. 4. 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