LY6164DL

® LY6164 Rev. 1.2 8K X 8 BIT HIGH SPEED CMOS SRAM REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Description Initial Issue Revised STSOP Package Outline Dimension Revised Test Condition of ISB1/IDR Revised VTERM to VT1 and VT2 Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Added packing type in ORDERING INFORMATION Issue Date Aug.3.2005 Mar.26.2008 Apr.17.2009 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0 ® LY6164 Rev. 1.2 8K X 8 BIT HIGH SPEED CMOS SRAM GENERAL DESCRIPTION The LY6164 is a 65,536-bit high speed CMOS static random access memory organized as 8,192 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY6164 is well designed for high speed system applications, and particularly well suited for battery back-up nonvolatile memory application. The LY6164 operates from a single power supply of 5V and all inputs and outputs are fully TTL compatible FEATURES Fast access time : 8/10/12/15ns Low power consumption: Operating current : 110/100/90/80mA (TYP.) Standby current : 1mA (TYP.) Single 5V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data retention voltage : 2.0V (MIN.) Green package available Package : 28-pin 300 mil SOJ 28-pin 300 mil Skinny P-DIP 28-pin 8mm x 13.4mm STSOP PRODUCT FAMILY Product Family LY6164 LY6164(E) LY6164(I) Operating Temperature 0 ~ 70℃ -20 ~ 80℃ -40 ~ 85℃ Vcc Range 4.5 ~ 5.5V 4.5 ~ 5.5V 4.5 ~ 5.5V Speed 8/10/12/15ns 8/10/12/15ns 8/10/12/15ns Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 1mA 110/100/90/80mA 1mA 110/100/90/80mA 1mA 110/100/90/80mA FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION SYMBOL DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Inputs Write Enable Input Output Enable Input Power Supply Ground No Connection Vcc Vss A0 - A12 DQ0 – DQ7 DECODER 8Kx8 MEMORY ARRAY CE#, CE2 WE# OE# VCC VSS NC A0-A12 DQ0-DQ7 I/O DATA CIRCUIT COLUMN I/O CE# CE2 WE# OE# CONTROL CIRCUIT Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1 ® LY6164 Rev. 1.2 8K X 8 BIT HIGH SPEED CMOS SRAM PIN CONFIGURATION NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 Vss 1 2 3 4 5 28 27 26 25 24 Vcc WE# CE2 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 OE# A11 A9 A8 CE2 WE# Vcc NC A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 LY6164 Skinny PDIP/SOJ 6 7 8 9 10 11 12 13 14 23 22 21 20 19 18 17 16 15 LY6164 STSOP ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 TA TSTG PD IOUT RATING -0.5 to 6.5 -0.5 to VCC+0.5 0 to 70(C grade) -20 to 80(E grade) -40 to 85(I grade) -65 to 150 1 50 UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# H X L L L CE2 X L H H H OE# X X H L X WE# X X H H L I/O OPERATION High-Z High-Z High-Z DOUT DIN SUPPLY CURRENT ISB1 ISB1 ICC ICC ICC H = VIH, L = VIL, X = Don't care. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2 ® LY6164 Rev. 1.2 8K X 8 BIT HIGH SPEED CMOS SRAM DC ELECTRICAL CHARACTERISTICS SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL VCC ≧ VIN ≧ VSS Input Leakage Current ILI Output Leakage VCC ≧ VOUT ≧ VSS, ILO Current Output Disabled Output High Voltage VOH IOH = -1mA Output Low Voltage VOL IOL = 2mA -8 Cycle time = Min. Average Operating CE# = VIL and CE2 = VIH, -10 ICC Power supply Current II/O = 0mA -12 Other pins at VIH or VIL -15 Standby Power CE# ≧VCC-0.2V or CE2≦0.2V ISB1 Supply Current Other pins at 0.2V or VCC-0.2V Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ MIN. 4.5 2.4 - 0.5 -1 -1 2.4 - TYP. 5.0 - *4 MAX. 5.5 VCC+0.5 0.8 1 1 0.4 190 180 160 140 5 UNIT V V V µA µA V V mA mA mA mA mA 110 100 90 80 1 CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3 ® LY6164 Rev. 1.2 8K X 8 BIT HIGH SPEED CMOS SRAM AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH LY6164-8 LY6164-10 LY6164-12 LY6164-15 UNIT MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. 8 10 12 15 ns 8 10 12 15 ns 8 10 12 15 ns 4 5 6 7 ns 2 2 3 4 ns 0 0 0 0 ns 4 5 6 7 ns 4 5 6 7 ns 3 3 3 3 ns SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* LY6164-8 LY6164-10 LY6164-12 LY6164-15 UNIT MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. 8 10 12 15 ns 6.5 8 10 12 ns 6.5 8 10 12 ns 0 0 0 0 ns 6.5 8 9 10 ns 0 0 0 0 ns 5 6 7 8 ns 0 0 0 0 ns 1.5 2 3 4 ns 5 6 7 8 ns *These parameters are guaranteed by device characterization, but not production tested. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4 ® LY6164 Rev. 1.2 8K X 8 BIT HIGH SPEED CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout Previous Data Valid tOH Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 OE# tOE tOLZ tCLZ Dout High-Z tOH tOHZ tCHZ Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low., CE2 = high. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5 ® LY6164 Rev. 1.2 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW CE2 tAS WE# tWHZ Dout (4) High-Z tDW Din tDH TOW (4) tWP tWR 8K X 8 BIT HIGH SPEED CMOS SRAM Data Valid WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6) tWC Address tAW CE# tAS tCW CE2 tWP WE# tWHZ Dout (4) High-Z tDW Din tDH tWR Data Valid Notes : 1.WE#, CE# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#. 3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6 ® LY6164 Rev. 1.2 8K X 8 BIT HIGH SPEED CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time SYMBOL VDR IDR tCDR tR TEST CONDITION CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V VCC = 2.0V CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V Others at 0.2V or VCC-0.2V See Data Retention Waveforms (below) MIN. 2.0 0 tRC* TYP. 0.6 MAX. 5.5 3 UNIT V mA ns ns DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) VDR ≧ 2.0V Vcc Vcc(min.) tCDR CE# VIH CE# ≧ Vcc-0.2V Vcc(min.) tR VIH Low Vcc Data Retention Waveform (2) (CE2 controlled) VDR ≧ 2.0V Vcc Vcc(min.) tCDR CE2 CE2 ≦ 0.2V VIL VIL Vcc(min.) tR Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7 ® LY6164 Rev. 1.2 8K X 8 BIT HIGH SPEED CMOS SRAM PACKAGE OUTLINE DIMENSION 28 pin 300 mil PDIP Package Outline Dimension Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8 ® LY6164 Rev. 1.2 8K X 8 BIT HIGH SPEED CMOS SRAM 28-pin 300 mil SOJ Package Outline Dimension 28 15 1 14 A2 C L X XX UNIT SYM. INCH(REF) MM(BASE) A 0.140 (MAX) 3.556 (MAX) A1 0.026 (MIN) 0.660 (MIN) A2 0.100±0.005 2.540±0.127 B 0.018±0.003 0.457±0.076 B1 0.028 ±0.003 0.711±0.076 c 0.010±0.003 0.254±0.076 D 0.710±0.010 18.03±0.254 E 0.337±0.010 8.560±0.254 E1 0.300±0.005 7.620±0.127 e 0.050±0.003 1.270±0.076 L 0.087±0.010 2.210±0.254 S 0.030±0.004 0.762±0.102 Y 0.003 (MAX) 0.076 (MAX) Note : 1.S/E/D dimension is not including mold flash. 2.The end flash in package lengthwise is not more than 10 mils each side. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9 ® LY6164 Rev. 1.2 8K X 8 BIT HIGH SPEED CMOS SRAM 28 pin 8x13.4mm STSOP Package Outline Dimension HD c L 12° (2x) 1 28 12° (2x) e 14 15 "A" D Seating Plane b E y 12° (2X) 14 15 GAUGE PLANE A A2 c 0.254 0 A1 SEATING PLANE 12° (2X) L 1 28 "A" DATAIL VIEW L1 SYMBOLS A A1 A2 b c HD D E e L L1 Y Θ DIMENSIONS IN MILLIMETERS MIN NOM MAX 1.00 1.10 1.20 0.05 0.15 0.91 1.00 1.05 0.17 0.22 0.27 0.10 0.15 0.20 13.20 13.40 13.60 11.70 11.80 11.90 7.90 8.00 8.10 0.55 0.30 0.50 0.70 0.675 0.00 0.076 0° 3° 5° DIMENSIONS IN INCHES MIN NOM MAX 0.040 0.043 0.047 0.002 0.006 0.036 0.039 0.041 0.007 0.009 0.011 0.004 0.006 0.008 0.520 0.528 0.535 0.461 0.465 0.469 0.311 0.315 0.319 0.0216 0.012 0.020 0.028 0.027 0.000 0.003 0° 3° 5° Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10 ® LY6164 Rev. 1.2 8K X 8 BIT HIGH SPEED CMOS SRAM ORDERING INFORMATION LY6164 U V - WW Y Z Z : Packing Type Blank : Tube or Tray T : Tape Reel Y : Temperature Range Blank : (Commercial) 0°C ~ 70°C E : (Extended) -20°C ~ +80°C I : (Industrial) -40°C ~ +85°C WW : Access Time(Speed) V : Lead Information L : Green Package U : Package Type J : 28-pin 300 mil SOJ D : 28-pin 330 mil P-DIP R : 28-pin 8 mm x 13.4 mm STSOP Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 11 ® LY6164 Rev. 1.2 8K X 8 BIT HIGH SPEED CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 12