LY61L12816ML

® LY61L12816 Rev. 1.2 128K X 16 BIT HIGH SPEED CMOS SRAM REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Description Initial Issued Revised PACKAGE OUTLINE DIMENSION Revised VTERM to VT1 and VT2 Revised Test Condition of ICC/ISB1/IDR Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Added packing type in ORDERING INFORMATION Issue Date May.26.2008 Aug.26.2009 Aug.27.2009 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0 ® LY61L12816 Rev. 1.2 128K X 16 BIT HIGH SPEED CMOS SRAM GENERAL DESCRIPTION The LY61L12816 is a 2,087,152-bit low power CMOS static random access memory organized as 131,072 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY61L12816 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The LY61L12816 operates from a single power supply of 3.3V and all inputs and outputs are fully TTL compatible FEATURES Fast access time : 10/12/15/20/25ns Very low power consumption: Operating current(Normal version): 200/180/150/110/90mA(TYP.) Operating current(15/20/25ns LL version): 45/40/35mA(TYP.) Standby current(Normal version): 0.5mA(TYP.) Standby current(15/20/25ns LL version): 20µA(TYP.) Single 3.3V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 2.0V (MIN.) Green package available Package : 44-pin 400 mil TSOP-II PRODUCT FAMILY Product Family LY61L12816 LY61L12816 LY61L12816(LL) Operating Temperature 0 ~ 70℃ 0 ~ 70℃ 0 ~ 70℃ Vcc Range 3.15 ~ 3.6V 3.0 ~ 3.6V 3.0 ~ 3.6V Speed 10/12ns 15/20/25ns 15/20/25ns Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 0.5mA 200/180mA 0.5mA 150/110/90mA 20µA(LL) 45/40/35mA(LL) Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1 ® LY61L12816 Rev. 1.2 128K X 16 BIT HIGH SPEED CMOS SRAM PIN DESCRIPTION SYMBOL DESCRIPTION Address Inputs Chip Enable Input Write Enable Input Output Enable Input Lower Byte Control Upper Byte Control Power Supply Ground FUNCTIONAL BLOCK DIAGRAM Vcc Vss A0 - A16 CE# WE# OE# LB# UB# VCC VSS I/O DATA CIRCUIT COLUMN I/O DQ0 – DQ15 Data Inputs/Outputs DECODER 128Kx16 MEMORY ARRAY A0-A16 DQ0-DQ7 Lower Byte DQ8-DQ15 Upper Byte CE# WE# OE# LB# UB# CONTROL CIRCUIT Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2 ® LY61L12816 Rev. 1.2 128K X 16 BIT HIGH SPEED CMOS SRAM PIN CONFIGURATION A4 A3 A2 A1 A0 CE# DQ0 DQ1 DQ2 DQ3 Vcc Vss DQ4 DQ5 DQ6 DQ7 WE# A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 TSOP II 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE# UB# LB# DQ15 DQ14 DQ13 DQ12 Vss Vcc DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 NC ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 TA TSTG PD IOUT RATING -0.5 to 4.6 -0.5 to VCC+0.5 0 to 70(C grade) -65 to 150 1 50 UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3 LY61L12816 ® LY61L12816 Rev. 1.2 128K X 16 BIT HIGH SPEED CMOS SRAM TRUTH TABLE MODE Standby Output Disable Read CE# H L L L L L L L L OE# X H X L L L X X X WE# LB# X H X H H H L L L X X H L H L L H L UB# X X H H L L H L L I/O OPERATION DQ0-DQ7 DQ8-DQ15 High – Z High – Z High – Z High – Z High – Z High – Z DOUT High – Z High – Z DOUT DOUT DOUT DIN High – Z High – Z DIN DIN DIN SUPPLY CURRENT ISB1 ICC ICC Write Note: ICC H = VIH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS PARAMETER Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage SYMBOL VCC VIH *2 VIL ILI ILO VOH VOL *1 TEST CONDITION -10/12 -15/20/25 VCC ≧ VIN ≧ VSS VCC ≧ VOUT ≧ VSS, Output Disabled IOH = -4mA IOL = 8mA 10 12 15 20 25 15LL 20LL 25LL Normal 15/20/25LL MIN. 3.15 3.0 2.2 - 0.3 -1 -1 2.4 - TYP. 3.3 3.3 - *4 MAX. 3.6 3.6 VCC+0.3 0.6 1 1 0.4 250 220 200 150 115 60 50 45 5* 5 6 UNIT V V V V µA µA V V mA mA mA mA mA mA mA mA mA µA Average Operating Power supply Current ICC Cycle time = Min. CE# = VIL , II/O = 0mA Others at VIL or VIH 200 180 150 110 90 45 40 35 0.5 10 Standby Power Supply Current ISB1 CE# ≧VCC - 0.2V Others at 0.2V or VCC - 0.2V 50* Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ 5. 1mA for special request 6. 20µA for special request Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4 ® LY61L12816 Rev. 1.2 128K X 16 BIT HIGH SPEED CMOS SRAM CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 8 10 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -8mA/16mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LB#, UB# Access Time LB#, UB# to High-Z Output LB#, UB# to Low-Z Output LY61L12816 LY61L12816 LY61L12816 LY61L12816 LY61L12816 UNIT -10 -12 -15 -20 -25 SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ* tBLZ* MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. 10 12 15 20 25 ns 10 12 15 20 25 ns 10 12 15 20 25 ns 5 6 7 8 9 ns 2 3 4 4 4 ns 0 0 0 0 0 ns 5 6 7 8 9 ns 5 6 7 8 9 ns 3 3 3 3 3 ns 5 6 7 8 9 ns 5 6 7 8 9 ns 2 3 4 4 4 ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* tBW LY61L12816 LY61L12816 LY61L12816 LY61L12816 LY61L12816 UNIT -10 -12 -15 -20 -25 MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. 10 12 15 20 25 8 10 12 16 20 8 10 12 16 20 0 0 0 0 0 8 9 10 11 12 0 0 0 0 0 6 7 8 9 10 0 0 0 0 0 2 3 4 5 6 6 7 8 9 10 8 10 12 16 20 - ns ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5 ® LY61L12816 Rev. 1.2 128K X 16 BIT HIGH SPEED CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout Previous Data Valid tOH Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE LB#,UB# tBA OE# tOE tOLZ tBLZ tCLZ Dout High-Z tOH tOHZ tBHZ tCHZ Data Valid High-Z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6 ® LY61L12816 Rev. 1.2 128K X 16 BIT HIGH SPEED CMOS SRAM WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW tBW LB#,UB# tAS WE# tWHZ Dout (4) High-Z tDW Din tDH TOW (4) tWP tWR Data Valid WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address tAW CE# tAS tCW tBW LB#,UB# tWP WE# tWHZ Dout (4) High-Z tDW Din tDH tWR Data Valid Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7 ® LY61L12816 Rev. 1.2 WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6) tWC Address tAW CE# tAS LB#,UB# tWP WE# tWHZ Dout (4) High-Z tDW Din tDH tCW tBW tWR 128K X 16 BIT HIGH SPEED CMOS SRAM Data Valid Notes : 1.WE#,CE#, LB#, UB# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8 ® LY61L12816 Rev. 1.2 128K X 16 BIT HIGH SPEED CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. VCC for Data Retention VDR CE# ≧ VCC - 0.2V 2.0 VCC = 2.0V Normal CE# ≧ VCC - 0.2V Data Retention Current IDR Others at 0.2V or 15/20/25(LL) VCC - 0.2V Chip Disable to Data See Data Retention tCDR 0 Retention Time Waveforms (below) Recovery Time tR tRC* tRC* = Read Cycle Time TYP. 0.3 5 MAX. 3.6 1 30 UNIT V mA µA ns ns DATA RETENTION WAVEFORM VDR ≧ 2.0V Vcc Vcc(min.) tCDR CE# VIH CE# ≧ Vcc-0.2V Vcc(min.) tR VIH Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9 ® LY61L12816 Rev. 1.2 128K X 16 BIT HIGH SPEED CMOS SRAM PACKAGE OUTLINE DIMENSION 44-pin 400mil TSOP-Ⅱ Package Outline Dimension SYMBOLS A A1 A2 b c D E E1 e L ZD y Θ DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 o o o 3 6 0 DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.3 11.8 17.7 4.7 8.3 717 725 733 453 463 473 392 400 408 31.5 15.7 19.7 23.6 31.7 3 o o o 0 3 6 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10 θ ® LY61L12816 Rev. 1.2 128K X 16 BIT HIGH SPEED CMOS SRAM ORDERING INFORMATION LY61L12816 U V - WW XX Y Z Z : Packing Type Blank : Tube or Tray T : Tape Reel Y : Temperature Range Blank : (Commercial) 0°C ~ 70°C XX : Power Type LL : Low Power WW : Access Time(Speed) V : Lead Information L : Green Package U : Package Type M : 44-pin 400 mil TSOP-II Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 11 ® LY61L12816 Rev. 1.2 128K X 16 BIT HIGH SPEED CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 12