LY62L20488MV

® LY62L20488 Rev. 0.3 2048K X 8 BIT LOW POWER CMOS SRAM REVISION HISTORY Revision Rev. 0.1 Rev. 0.2 Rev. 0.3 Description Initial Issue Revised the typo in page 1 Added SL grade Added ISB1/IDR values when TA = 25℃ and TA = 40℃ Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Added packing type in ORDERING INFORMATION Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Issue Date Jan.8.2007 Sep.17.2008 Mar.30.2009 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0 ® LY62L20488 Rev. 0.3 2048K X 8 BIT LOW POWER CMOS SRAM GENERAL DESCRIPTION The LY62L20488 is a 16,777,216-bit low power CMOS static random access memory organized as 2,097,152 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY62L20488 is well designed for very low power system applications, and particularly well suited for battery back-up nonvolatile memory application. The LY62L20488 operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TTL compatible FEATURES Fast access time : 55/70ns Low power consumption: Operating current : 45/30mA (TYP.) Standby current : 10μA (TYP.) LL-version 4μA (TYP.) SL-version Single 2.7V ~ 3.6V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data retention voltage : 1.2V (MIN.) Green package available Package : 44-pin 400 mil TSOP-II PRODUCT FAMILY Product Family LY62L20488 LY62L20488(E) LY62L20488(I) Operating Temperature 0 ~ 70℃ -20 ~ 80℃ -40 ~ 85℃ Vcc Range 2.7 ~ 3.6V 2.7 ~ 3.6V 2.7 ~ 3.6V Speed 55/70ns 55/70ns 55/70ns Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 10µA(LL)/4µA(SL) 45/30mA 10µA(LL)/4µA(SL) 45/30mA 10µA(LL)/4µA(SL) 45/30mA FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION SYMBOL DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Inputs Write Enable Input Output Enable Input Power Supply Ground No Connection Vcc Vss A0 – A20 DQ0 – DQ7 DECODER 2048Kx8 MEMORY ARRAY CE#, CE2 WE# OE# VCC VSS NC A0-A20 DQ0-DQ7 I/O DATA CIRCUIT COLUMN I/O CE# CE2 WE# OE# CONTROL CIRCUIT Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1 ® LY62L20488 Rev. 0.3 2048K X 8 BIT LOW POWER CMOS SRAM PIN CONFIGURATION A4 A3 A2 A1 A0 CE# NC NC DQ0 DQ1 Vcc Vss DQ2 DQ3 NC A20 WE# A19 A18 A17 A16 A15 1 2 3 4 5 6 7 44 43 42 41 40 39 38 A5 A6 A7 OE# CE2 A8 NC NC DQ7 DQ6 Vss Vcc DQ5 DQ4 NC NC A9 A10 A11 A12 A13 A14 LY62L20488 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 TSOP-II Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2 ® LY62L20488 Rev. 0.3 2048K X 8 BIT LOW POWER CMOS SRAM ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 TA TSTG PD IOUT RATING -0.5 to 4.6 -0.5 to VCC+0.5 0 to 70(C grade) -20 to 80(E grade) -40 to 85(I grade) -65 to 150 1 50 UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# H X L L L CE2 X L H H H OE# X X H L X WE# X X H H L I/O OPERATION High-Z High-Z High-Z DOUT DIN SUPPLY CURRENT ISB,ISB1 ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 H = VIH, L = VIL, X = Don't care. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3 ® LY62L20488 Rev. 0.3 2048K X 8 BIT LOW POWER CMOS SRAM DC ELECTRICAL CHARACTERISTICS SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VCC ≧ VIN ≧ VSS Output Leakage VCC ≧ VOUT ≧ VSS, ILO Current Output Disabled Output High Voltage VOH IOH = -1mA Output Low Voltage VOL IOL = 2mA Cycle time = Min. - 55 CE# = VIL and CE2 = VIH ICC II/O = 0mA - 70 Other pins at VIL or VIH Average Operating Power supply Current Cycle time = 1µs CE#≦0.2V and CE2≧VCC-0.2V ICC1 II/O = 0mA other pins at 0.2V or VCC-0.2V CE# = VIH or CE2 = VIL ISB Other pins at VIL or VIH LL LLE LLI CE# ≧VCC-0.2V Standby Power *5 SL 25 ℃ Supply Current or CE2≦0.2V *5 SLE ISB1 Other pins at 0.2V *5 40℃ SLI or VCC-0.2V SL SLE SLI Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25℃ 5. This parameter is measured at VCC = 3.0V MIN. 2.7 2.2 - 0.2 -1 -1 2.2 - TYP. 3.0 2.7 45 30 *4 MAX. 3.6 VCC+0.3 0.6 1 1 0.4 60 45 UNIT V V V µA µA V V mA mA - 8 16 mA - 0.3 10 10 10 4 4 4 4 4 2 60 80 100 6 6 30 30 40 mA µA µA µA µA µA µA µA µA Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4 ® LY62L20488 Rev. 0.3 2048K X 8 BIT LOW POWER CMOS SRAM CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH LY62L20488-55 MIN. MAX. 55 55 55 30 10 5 20 20 10 LY62L20488-70 MIN. MAX. 70 70 70 35 10 5 25 25 10 UNIT ns ns ns ns ns ns ns ns ns SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* LY62L20488-55 MIN. MAX. 55 50 50 0 45 0 25 0 5 20 LY62L20488-70 MIN. MAX. 70 60 60 0 55 0 30 0 5 25 UNIT ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5 ® LY62L20488 Rev. 0.3 2048K X 8 BIT LOW POWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout Previous Data Valid tOH Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 OE# tOE tOLZ tCLZ Dout High-Z tOH tOHZ tCHZ Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low., CE2 = high. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6 ® LY62L20488 Rev. 0.3 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW CE2 tAS WE# tWHZ Dout (4) High-Z tDW Din tDH TOW (4) tWP tWR 2048K X 8 BIT LOW POWER CMOS SRAM Data Valid WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6) tWC Address tAW CE# tAS tCW CE2 tWP WE# tWHZ Dout (4) High-Z tDW Din tDH tWR Data Valid Notes : 1.WE#, CE# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#. 3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7 ® LY62L20488 Rev. 0.3 2048K X 8 BIT LOW POWER CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION VCC for Data Retention VDR CE#≧VCC - 0.2V or CE2≦0.2V LL LLE LLI VCC = 1.2V SL 25℃ CE# ≧VCC-0.2V or CE2≦0.2V SLE other pins at 0.2V or VCC-0.2V SLI 40℃ SL/SLE SLI See Data Retention Waveforms (below) MIN. 1.2 0 tRC* TYP. 4 4 4 2.5 2.5 2.5 2.5 MAX. 3.6 50 60 80 5 5 30 40 UNIT V µA µA µA µA µA µA µA ns ns Data Retention Current IDR Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time tCDR tR DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) VDR ≧ 1.2V Vcc Vcc(min.) tCDR CE# VIH CE# ≧ Vcc-0.2V Vcc(min.) tR VIH Low Vcc Data Retention Waveform (2) (CE2 controlled) VDR ≧ 1.2V Vcc Vcc(min.) tCDR CE2 CE2 ≦ 0.2V VIL VIL Vcc(min.) tR Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8 ® LY62L20488 Rev. 0.3 2048K X 8 BIT LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION 44-pin 400mil TSOP-II Package Outline Dimension SYMBOLS A A1 A2 b c D E E1 e L ZD y Θ DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 o o o 3 6 0 DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.3 11.8 17.7 4.7 8.3 717 725 733 453 463 473 392 400 408 31.5 15.7 19.7 23.6 31.7 3 o o o 0 3 6 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9 θ ® LY62L20488 Rev. 0.3 2048K X 8 BIT LOW POWER CMOS SRAM ORDERING INFORMATION LY62L20488 U V - WW XX Y Z Z : Packing Type Blank : Tube or Tray T : Tape Reel Y : Temperature Range Blank : (Commercial) 0°C ~ 70°C E : (Extended) -20°C ~ +80°C I : (Industrial) -40°C ~ +85°C XX : Power Type LL : Ultra Low Power SL : Special Ultra Low Power WW : Access Time(Speed) V : Lead Information L : Green Package U : Package Type M : 44-pin 400 mil TSOP-II Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10 ® LY62L20488 Rev. 0.3 2048K X 8 BIT LOW POWER CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 11