LY62L51316I

® LY62L51316 Rev. 1.4 512K X 16 BIT LOW POWER CMOS SRAM REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Description Initial Issue Revised 48-ball 6mm × 8mm TFBGA Package Outline Dimension Added ISB Spec. Added SL Spec. Added ISB1/IDR values when TA = 25℃ and TA = 40℃ Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Added packing type in ORDERING INFORMATION Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Issue Date Apr.12.2007 May.28.2007 Feb.1.2008 Jul.2.2008 Mar.30.2009 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0 ® LY62L51316 Rev. 1.4 512K X 16 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION Fast access time : 55/70ns Low power consumption: Operating current : 30/20mA (TYP.) Standby current : 5μA (TYP.) LL-version 1.5μA (TYP.) SL-version Single 2.7V ~ 3.6V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 1.2V (MIN.) Green package available Package : 48-pin 12mm x 20mm TSOP-I 48-ball 6mm x 8mm TFBGA The LY62L51316 is a 8,388,608-bit low power CMOS static random access memory organized as 524,288 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY62L51316 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The LY62L51316 operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family LY62L51316 LY62L51316(E) LY62L51316(I) Operating Temperature 0 ~ 70℃ -20 ~ 80℃ -40 ~ 85℃ Vcc Range 2.7 ~ 3.6V 2.7 ~ 3.6V 2.7 ~ 3.6V Speed 55/70ns 55/70ns 55/70ns Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 5µA(LL)/1.5µA(SL) 30/20mA 5µA(LL)/1.5µA(SL) 30/20mA 5µA(LL)/1.5µA(SL) 30/20mA FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION SYMBOL DESCRIPTION Address Inputs Chip Enable Input Write Enable Input Output Enable Input Lower Byte Control Upper Byte Control Power Supply Ground Vcc Vss A0 - A18 CE#, CE2 WE# OE# LB# UB# VCC DQ0 – DQ15 Data Inputs/Outputs DECODER 512Kx16 MEMORY ARRAY A0-A18 DQ0-DQ7 Lower Byte DQ8-DQ15 Upper Byte VSS I/O DATA CIRCUIT COLUMN I/O CE# CE2 WE# OE# LB# UB# CONTROL CIRCUIT Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1 ® LY62L51316 Rev. 1.4 512K X 16 BIT LOW POWER CMOS SRAM PIN CONFIGURATION A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# CE2 NC UB# LB# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 NC Vss DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss CE# A0 LY62L51316 TSOP-I A B C D E F G H LB# OE# DQ8 UB# A0 A3 A1 A4 A6 A7 A2 CE2 CE# DQ0 DQ1 DQ2 DQ3 Vcc DQ9 DQ10 A5 Vss DQ11 A17 Vcc DQ12 NC DQ14 DQ13 A14 DQ15 NC A18 A8 A12 A9 A16 DQ4 Vss A15 DQ5 DQ6 A13 WE# DQ7 A10 A11 NC 1 2 3 4 TFBGA 5 6 ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 TA TSTG PD IOUT RATING -0.5 to 4.6 -0.5 to VCC+0.5 0 to 70(C grade) -20 to 80(E grade) -40 to 85(I grade) -65 to 150 1 50 UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2 ® LY62L51316 Rev. 1.4 512K X 16 BIT LOW POWER CMOS SRAM TRUTH TABLE MODE Standby Output Disable Read CE# H X X L L L L L L L L CE2 X L X H H H H H H H H OE# X X X H H L L L X X X WE# X X X H H H H H L L L LB# X X H L X L H L L H L UB# X X H X L H L L H L L I/O OPERATION SUPPLY CURRENT DQ0-DQ7 DQ8-DQ15 High – Z High – Z ISB,ISB1 High – Z High – Z High – Z High – Z High – Z High – Z ICC,ICC1 High – Z High – Z DOUT High – Z ICC,ICC1 High – Z DOUT DOUT DOUT DIN High – Z ICC,ICC1 High – Z DIN DIN DIN Write Note: H = VIH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VCC ≧ VIN ≧ VSS Output Leakage VCC ≧ VOUT ≧ VSS, ILO Current Output Disabled Output High Voltage VOH IOH = -1mA Output Low Voltage VOL IOL = 2mA Cycle time = Min. - 55 CE# = VIL and CE2 = VIH ICC II/O = 0mA - 70 Other pins at VIL or VIH Average Operating Power supply Current Cycle time = 1µs CE#≦0.2V and CE2≧VCC-0.2V ICC1 II/O = 0mA other pins at 0.2V or VCC-0.2V CE# = VIH or CE2 = VIL ISB Other pins at VIL or VIH LL LLE LLI CE# ≧VCC-0.2V Standby Power *5 SL 25 ℃ Supply Current or CE2≦0.2V *5 SLE ISB1 Other pins at 0.2V *5 40℃ SLI or VCC-0.2V SL SLE SLI Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. MIN. 2.7 2.2 - 0.2 -1 -1 2.2 - TYP. 3.0 2.7 30 20 *4 MAX. 3.6 VCC+0.3 0.6 1 1 0.4 40 30 UNIT V V V µA µA V V mA mA - 4 8 mA - 0.15 5 5 5 1.5 1.5 1.5 1.5 1.5 1 30 40 50 5 5 15 15 20 mA µA µA µA µA µA µA µA µA Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3 ® LY62L51316 Rev. 1.4 512K X 16 BIT LOW POWER CMOS SRAM 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25℃ 5. This parameter is measured at VCC = 3.0V CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LB#, UB# Access Time LB#, UB# to High-Z Output LB#, UB# to Low-Z Output (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ* tBLZ* LY62L51316-55 MIN. MAX. 55 55 55 30 10 5 20 20 10 55 25 10 LY62L51316-70 MIN. MAX. 70 70 70 35 10 5 25 25 10 70 30 10 UNIT ns ns ns ns ns ns ns ns ns ns ns ns SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* tBW LY62L51316-55 MIN. MAX. 55 50 50 0 45 0 25 0 5 20 45 - LY62L51316-70 MIN. MAX. 70 60 60 0 55 0 30 0 5 25 60 - UNIT ns ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4 ® LY62L51316 Rev. 1.4 512K X 16 BIT LOW POWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout Previous Data Valid tOH Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 LB#,UB# tBA OE# tOE tOLZ tBLZ tCLZ Dout High-Z tOH tOHZ tBHZ tCHZ Data Valid High-Z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, CE2 = high, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5 ® LY62L51316 Rev. 1.4 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW CE2 tBW LB#,UB# tAS WE# tWHZ Dout (4) High-Z tDW Din tDH TOW (4) tWP tWR 512K X 16 BIT LOW POWER CMOS SRAM Data Valid WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6) tWC Address tAW CE# tAS tCW CE2 tBW LB#,UB# tWP WE# tWHZ Dout (4) High-Z tDW Din tDH tWR Data Valid Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6 ® LY62L51316 Rev. 1.4 WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6) tWC Address tAW CE# tAS CE2 tBW LB#,UB# tWP WE# tWHZ Dout (4) High-Z tDW Din tDH tCW tWR 512K X 16 BIT LOW POWER CMOS SRAM Data Valid Notes : 1.WE#,CE#, LB#, UB# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7 ® LY62L51316 Rev. 1.4 512K X 16 BIT LOW POWER CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. VCC for Data Retention VDR 1.2 ≦0.2V CE# ≧ VCC - 0.2V or CE2 LL LLE LLI VCC = 1.2V SL 25℃ Data Retention Current IDR CE# ≧VCC-0.2V or CE2≦0.2V SLE other pins at 0.2V or VCC-0.2V SLI 40℃ SL/SLE SLI Chip Disable to Data See Data Retention tCDR 0 Retention Time Waveforms (below) Recovery Time tR tRC* tRC* = Read Cycle Time TYP. 2 2 2 1 1 1 1 MAX. 3.6 25 30 40 3 3 15 20 UNIT V µA µA µA µA µA µA µA ns ns DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) VDR ≧ 1.2V Vcc Vcc(min.) tCDR CE# VIH CE# ≧ Vcc-0.2V Vcc(min.) tR VIH Low Vcc Data Retention Waveform (2) (CE2 controlled) VDR ≧ 1.2V Vcc Vcc(min.) tCDR CE2 CE2 ≦ 0.2V VIL VIL Vcc(min.) tR Low Vcc Data Retention Waveform (3) (LB#, UB# controlled) VDR ≧ 1.2V Vcc Vcc(min.) tCDR LB#,UB# VIH LB#,UB# ≧ Vcc-0.2V Vcc(min.) tR VIH Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8 ® LY62L51316 Rev. 1.4 512K X 16 BIT LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION 48-pin 12mm x 20mm TSOP-I Package Outline Dimension Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9 ® LY62L51316 Rev. 1.4 512K X 16 BIT LOW POWER CMOS SRAM 48-ball 6mm × 8mm TFBGA Package Outline Dimension Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10 ® LY62L51316 Rev. 1.4 512K X 16 BIT LOW POWER CMOS SRAM ORDERING INFORMATION LY62L51316 U V - WW XX Y Z Z : Packing Type Blank : Tube or Tray T : Tape Reel Y : Temperature Range Blank : (Commercial) 0°C ~ 70°C E : (Extended) -20°C ~ +80°C I : (Industrial) -40°C ~ +85°C XX : Power Type LL : Ultra Low Power SL : Special Ultra Low Power WW : Access Time(Speed) V : Lead Information L : Green Package U : Package Type L : 48-pin 12 mm x 20 mm TSOP-I G : 48-ball 6 mm x 8 mm TFBGA Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 11 ® LY62L51316 Rev. 1.4 512K X 16 BIT LOW POWER CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 12