LY62W1024SV

® LY62W1024 Rev. 1.4 128K X 8 BIT LOW POWER CMOS SRAM REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Description Initial Issue Revised ISB1 LL/LLI-LLE(max)= 50/100 μA => 20/50 μA IDR LL/LLI-LLE(max)= 20/40 μA => 12/30 μA Added SL Spec. Revised typos in FEATURES Revised ISB1/IDR(MAX.) Added ISB1/IDR values when TA = 25℃ and TA = 40℃ Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Added packing type in ORDERING INFORMATION Revised VTERM to VT1 and VT2 Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Issue Date Aug.28.2005 Mar.30.2006 Nov.2.2007 May.6.2008 Mar.30.2009 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0 ® LY62W1024 Rev. 1.4 128K X 8 BIT LOW POWER CMOS SRAM GENERAL DESCRIPTION The LY62W1024 is a 1,048,576-bit low power CMOS static random access memory organized as 131,072 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY62W1024 is well designed for very low power system applications, and particularly well suited for battery back-up nonvolatile memory application. The LY62W1024 operates from a single power supply of 2.7V ~ 5.5V and all inputs and outputs are fully TTL compatible FEATURES Fast access time : 35/55/70ns Low power consumption: Operating current : 12/10/7mA (TYP.) Standby current : 1μA (TYP.) LL-version 0.8μA (TYP.) SL-version Single 2.7V ~ 5.5V power supply All outputs TTL compatible Fully static operation Tri-state output Data retention voltage : 1.5V (MIN.) Green package available Package : 32-pin 450 mil SOP 32-pin 600 mil P-DIP 32-pin 8mm x 20mm TSOP-I 32-pin 8mm x 13.4mm STSOP 36-ball 6mm x 8mm TFBGA PRODUCT FAMILY Product Family LY62W1024 LY62W1024(E) LY62W1024(I) Operating Temperature 0 ~ 70℃ -20 ~ 80℃ -40 ~ 85℃ Vcc Range 2.7 ~ 5.5V 2.7 ~ 5.5V 2.7 ~ 5.5V Speed 35/55/70ns 35/55/70ns 35/55/70ns FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION SYMBOL DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Inputs Write Enable Input Output Enable Input Power Supply Ground No Connection Vcc Vss A0 - A16 DQ0 – DQ7 DECODER 128Kx8 MEMORY ARRAY CE#, CE2 WE# OE# VCC VSS NC A0-A16 DQ0-DQ7 I/O DATA CIRCUIT COLUMN I/O CE# CE2 WE# OE# CONTROL CIRCUIT Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1 ® LY62W1024 Rev. 1.4 128K X 8 BIT LOW POWER CMOS SRAM PIN CONFIGURATION NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SOP/P-DIP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A15 CE2 WE# A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 A11 A9 A8 A13 WE# CE2 A15 Vcc NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A3 LY62W1024 LY62W1024 TSOP-I/STSOP A B C D E F G H A0 DQ4 DQ5 Vss Vcc DQ6 A1 A2 CE2 WE# NC A3 A4 A5 A6 A7 A8 DQ0 DQ1 Vcc Vss NC NC DQ2 A15 DQ3 A13 A14 DQ7 OE# CE# A16 A9 A10 A11 A12 1 2 3 4 TFBGA 5 6 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2 ® LY62W1024 Rev. 1.4 128K X 8 BIT LOW POWER CMOS SRAM ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 TA TSTG PD IOUT RATING -0.5 to 6.5 -0.5 to VCC+0.5 0 to 70(C grade) -20 to 80(E grade) -40 to 85(I grade) -65 to 150 1 50 UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# H X L L L CE2 X L H H H OE# X X H L X WE# X X H H L I/O OPERATION High-Z High-Z High-Z DOUT DIN SUPPLY CURRENT ISB1 ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 H = VIH, L = VIL, X = Don't care. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3 ® LY62W1024 Rev. 1.4 128K X 8 BIT LOW POWER CMOS SRAM DC ELECTRICAL CHARACTERISTICS SYMBOL TEST CONDITION MIN. PARAMETER Supply Voltage VCC 2.7 *1 Input High Voltage VIH 0.7*Vcc *2 Input Low Voltage VIL - 0.2 Input Leakage Current ILI VCC ≧ VIN ≧ VSS -1 Output Leakage VCC ≧ VOUT ≧ VSS, ILO -1 Current Output Disabled Output High Voltage VOH IOH = -1mA 2.2 Output Low Voltage VOL IOL = 2mA Cycle time = Min. - 35 CE# = VIL and CE2 = VIH , ICC - 55 II/O = 0mA - 70 Other pins at VIL or VIH Average Operating Power supply Current Cycle time = 1µs CE# = 0.2V and CE2≧VCC-0.2V, ICC1 II/O = 0mA Other pins at 0.2V or VCC - 0.2V LL LLE/LLI CE# ≧VCC-0.2V *5 SL 25 ℃ Standby Power or CE2≦0.2V *5 ISB1 SLE Supply Current Others at 0.2V or *5 40℃ SLI VCC - 0.2V SL SLE/SLI Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25℃ 5. This parameter is measured at VCC = 3.0V TYP. 3.0 2.7 12 10 7 1 1 1 0.8 1 0.8 0.8 *4 MAX. 5.5 VCC+0.3 0.6 1 1 0.4 80 60 50 10 15 30 2 2 7 10 UNIT V V V µA µA V V mA mA mA mA µA µA µA µA µA µA Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4 ® LY62W1024 Rev. 1.4 128K X 8 BIT LOW POWER CMOS SRAM CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 50pF + 1TTL, IOH/IOL = -1mA/2mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. LY62W1024-35 LY62W1024-55 LY62W1024-70 UNIT MIN. MAX. MIN. MAX. MIN. MAX. tRC 35 55 70 ns tAA 35 55 70 ns tACE 35 55 70 ns tOE 25 30 35 ns tCLZ* 10 10 10 ns tOLZ* 5 5 5 ns tCHZ* 15 20 25 ns tOHZ* 15 20 25 ns tOH 10 10 10 ns SYM. LY62W1024-35 LY62W1024-55 LY62W1024-70 MIN. MAX. MIN. MAX. MIN. MAX. tWC 35 55 70 tAW 30 50 60 tCW 30 50 60 tAS 0 0 0 tWP 25 45 55 tWR 0 0 0 tDW 20 25 30 tDH 0 0 0 tOW* 5 5 5 tWHZ* 15 20 25 UNIT ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5 ® LY62W1024 Rev. 1.4 128K X 8 BIT LOW POWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout Previous Data Valid tOH Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 OE# tOE tOLZ tCLZ Dout High-Z tOH tOHZ tCHZ Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low., CE2 = high. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6 ® LY62W1024 Rev. 1.4 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW CE2 tAS WE# tWHZ Dout (4) High-Z tDW Din tDH TOW (4) tWP tWR 128K X 8 BIT LOW POWER CMOS SRAM Data Valid WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6) tWC Address tAW CE# tAS tCW CE2 tWP WE# tWHZ Dout (4) High-Z tDW Din tDH tWR Data Valid Notes : 1.WE#, CE# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#. 3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7 ® LY62W1024 Rev. 1.4 128K X 8 BIT LOW POWER CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention SYMBOL TEST CONDITION MIN. VDR CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V 1.5 LL LLE/LLI VCC = 1.5V SL 25℃ CE# ≧ VCC - 0.2V IDR SLE or CE2 ≦ 0.2V 40℃ Other pins at 0.2V or VCC-0.2V SLI SL SLE/SLI See Data Retention tCDR 0 Waveforms (below) tR tRC* TYP. 0.5 0.5 0.4 0.5 0.4 0.4 MAX. 5.5 12 30 2 2 5 8 UNIT V µA µA µA µA µA µA ns ns Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) VDR ≧ 1.5V Vcc Vcc(min.) tCDR CE# VIH CE# ≧ Vcc-0.2V Vcc(min.) tR VIH Low Vcc Data Retention Waveform (2) (CE2 controlled) VDR ≧ 1.5V Vcc Vcc(min.) tCDR CE2 CE2 ≦ 0.2V VIL VIL Vcc(min.) tR Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8 ® LY62W1024 Rev. 1.4 128K X 8 BIT LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION 32 pin 450 mil SOP Package Outline Dimension UNIT SYM. INCH.(BASE) 0.118 (MAX) 0.004(MIN) 0.111(MAX) 0.016(TYP) 0.008(TYP) 0.817(MAX) 0.445 ±0.005 0.555 ±0.012 0.050(TYP) 0.0347 ±0.008 0.055 ±0.008 0.026(MAX) 0.004(MAX) o o 0 -10 MM(REF) 2.997 (MAX) 0.102(MIN) 2.82(MAX) 0.406(TYP) 0.203(TYP) 20.75(MAX) 11.303 ±0.127 14.097 ±0.305 1.270(TYP) 0.881 ±0.203 1.397 ±0.203 0.660 (MAX) 0.101(MAX) o o 0 -10 A A1 A2 b c D E E1 e L L1 S y Θ Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9 ® LY62W1024 Rev. 1.4 128K X 8 BIT LOW POWER CMOS SRAM 32 pin 600 mil P-DIP Package Outline Dimension UNIT SYM. INCH(BASE) 0.001 (MIN) 0.150 ± 0.005 0.018 ± 0.005 1.650 ± 0.005 0.600 ± 0.010 0.544 ± 0.004 0.100 (TYP) 0.640 ± 0.020 0.130 ± 0.010 0.075 ± 0.010 0.070 ± 0.005 MM(REF) 0.254 (MIN) 3.810 ± 0.127 0.457 ± 0.127 41.910 ± 0.127 15.240 ± 0.254 13.818 ± 0.102 2.540 (TYP) 16.256 ± 0.508. 3.302 ± 0.254 1.905 ± 0.254 1.778 ± 0.127 A1 A2 B D E E1 e eB L S Q1 Note : D/E1/S dimension do not include mold flash. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10 ® LY62W1024 Rev. 1.4 128K X 8 BIT LOW POWER CMOS SRAM 32 pin 8mm x 20mm TSOP-I Package Outline Dimension UNIT SYM. INCH(BASE) 0.047 (MAX) 0.004 ±0.002 0.039 ±0.002 0.008 + 0.002 - 0.001 0.005 (TYP) 0.724 ±0.004 0.315 ±0.004 0.020 (TYP) 0.787 ±0.008 0.0197 ±0.004 0.0315 ±0.004 0.003 (MAX) o o 0 ～5 MM(REF) 1.20 (MAX) 0.10 ±0.05 1.00 ±0.05 0.20 + 0.05 -0.03 0.127 (TYP) 18.40 ±0.10 8.00 ±0.10 0.50 (TYP) 20.00 ±0.20 0.50 ±0.10 0.08 ±0.10 0.076 (MAX) o o 0 ～5 A A1 A2 b c D E e HD L L1 y Θ Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 11 ® LY62W1024 Rev. 1.4 128K X 8 BIT LOW POWER CMOS SRAM 32 pin 8mm x 13.4mm STSOP Package Outline Dimension HD c L 12° (2x) 1 32 12° (2x) e 16 17 "A" D Seating Plane b E y 12° (2X) 16 17 GAUGE PLANE A A2 c 0.254 0 A1 SEATING PLANE 12° (2X) L1 L "A" DATAIL VIEW 1 32 UNIT SYM. INCH(BASE) 0.049 (MAX) 0.005 ±0.002 0.039 ±0.002 0.008 ±0.01 0.005 (TYP) 0.465 ±0.004 0.315 ±0.004 0.020 (TYP) 0.528±0.008 0.0197 ±0.004 0.0315 ±0.004 0.003 (MAX) o o 0 ～5 MM(REF) 1.25 (MAX) 0.130 ±0.05 1.00 ±0.05 0.20±0.025 0.127 (TYP) 11.80 ±0.10 8.00 ±0.10 0.50 (TYP) 13.40 ±0.20. 0.50 ±0.10 0.8 ±0.10 0.076 (MAX) o o 0 ～5 A A1 A2 b c D E e HD L L1 y Θ Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 12 ® LY62W1024 Rev. 1.4 128K X 8 BIT LOW POWER CMOS SRAM 36 ball 6mm × 8mm TFBGA Package Outline Dimension Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 13 ® LY62W1024 Rev. 1.4 128K X 8 BIT LOW POWER CMOS SRAM ORDERING INFORMATION LY62W1024 U V - WW XX Y Z Z : Packing Type Blank : Tube or Tray T : Tape Reel Y : Temperature Range Blank : (Commercial) 0°C ~ 70°C E : (Extended) -20°C ~ +80°C I : (Industrial) -40°C ~ +85°C XX : Power Type LL : Ultra Low Power SL : Special Ultra Low Power WW : Access Time(Speed) V : Lead Information L : Green Package U : Package Type S : 32-pin 450 mil SOP P : 32-pin 600 mil P-DIP L : 32-pin 8 mm x 20 mm TSOP-I R : 32-pin 8 mm x 13.4 mm STSOP G : 36-ball 6 mm x 8 mm TFBGA Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 14 ® LY62W1024 Rev. 1.4 128K X 8 BIT LOW POWER CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 15