MRF136

SEMICONDUCTOR TECHNICAL DATA Order this document by MRF136/D The RF MOSFET Line RF Power Field-Effect Transistors MRF136 N-Channel Enhancement-Mode MOSFET Designed for wideband large–signal amplifier and oscillator applications up to 400 MHz range, in single ended configuration. • Guaranteed 28 Volt, 150 MHz Performance Output Power = 15 Watts Narrowband Gain = 16 dB (Typ) Efficiency = 60% (Typical) • Small–Signal and Large–Signal Characterization • 100% Tested For Load Mismatch At All Phase Angles With 30:1 VSWR • Excellent Thermal Stability, Ideally Suited For Class A Operation • Facilitates Manual Gain Control, ALC and Modulation Techniques G S D 15 W, to 400 MHz N–CHANNEL MOS BROADBAND RF POWER FET CASE 211–07, STYLE 2 MAXIMUM RATINGS Rating Drain–Source Voltage Drain–Gate Voltage (RGS = 1.0 MΩ) Gate–Source Voltage Drain Current — Continuous Total Device Dissipation @ TC = 25°C Derate above 25°C Storage Temperature Range Operating Junction Temperature Symbol VDSS VDGR VGS ID PD Tstg TJ Value 65 65 ± 40 2.5 55 0.314 – 65 to +150 200 Unit Vdc Vdc Vdc Adc Watts W/°C °C °C THERMAL CHARACTERISTICS Characteristic Thermal Resistance, Junction to Case Symbol RθJC Max 3.2 Unit °C/W NOTE – CAUTION – MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and packaging MOS devices should be observed. REV 7 1 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS (1) Drain–Source Breakdown Voltage (VGS = 0, ID = 5.0 mA) Zero–Gate Voltage Drain Current (VDS = 28 V, VGS = 0) Gate–Source Leakage Current (VGS = 40 V, VDS = 0) V(BR)DSS IDSS IGSS 65 — — — — — — 2.0 1.0 Vdc mAdc µAdc ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = 10 V, ID = 25 mA) Forward Transconductance (VDS = 10 V, ID = 250 mA) VGS(th) gfs 1.0 250 3.0 400 6.0 — Vdc mmhos DYNAMIC CHARACTERISTICS (1) Input Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz) Output Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz) Reverse Transfer Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz) Ciss Coss Crss — — — 24 27 5.5 — — — pF pF pF FUNCTIONAL CHARACTERISTICS Noise Figure (VDS = 28 Vdc, ID = 500 mA, f = 150 MHz) Common Source Power Gain (Figure 1) (VDD = 28 Vdc, Pout = 15 W, f = 150 MHz, IDQ = 25 mA) Drain Efficiency (Figure 1) (VDD = 28 Vdc, Pout = 15 W, f = 150 MHz, IDQ = 25 mA) Electrical Ruggedness (Figure 1) (VDD = 28 Vdc, Pout = 15 W, f = 150 MHz, IDQ = 25 mA, VSWR 30:1 at all Phase Angles) NOTES: 1. Each side measured separately. NF Gps η ψ No Degradation in Output Power — 13 50 1.0 16 60 — — — dB dB % REV 7 2 R4 + – RFC1 C10 RFC2 C11 VDD = + 28 V BIAS ADJUST R3 R2 D1 C8 C9 C7 R1 C1 RF INPUT C2 DUT L1 L2 L3 C6 RF OUTPUT C4 C3 C5 C1, C2 — Arco 406, 15 – 115 pF or Equivalent C3 — Arco 404, 8 – 60 pF or Equivalent C4 — 43 pF Mini–Unelco or Equivalent C5 — 24 pF Mini–Unelco or Equivalent C6 — 680 pF, 100 Mils Chip C7 — 0.01 µF Ceramic C8 — 100 µF, 40 V C9 — 0.1 µF Ceramic C10, C11 — 680 pF Feedthru D1 — 1N5925A Motorola Zener L1 — 2 Turns, 0.29″ ID, #18 AWG, 0.10″ Long L2 — 2 Turns, 0.23″ ID, #18 AWG, 0.10″ Long L3 — 2–1/4 Turns, 0.29″ ID, #18 AWG, 0.125″ Long RFC1 — 20 Turns, 0.30″ ID, #20 AWG Enamel Closewound RFC2 — Ferroxcube VK–200 — 19/4B R1 — 27 Ω, 1 W Thin Film R2 — 10 kΩ, 1/4 W R3 — 10 Turns, 10 kΩ R4 — 1.8 kΩ, 1/2 W Board Material — 0.062″ G10, 1 oz. Cu Clad, Double Sided Figure 1. 150 MHz Test Circuit REV 7 3 TYPICAL CHARACTERISTICS 20 18 Pout , OUTPUT POWER (WATTS) 16 14 12 10 8 6 4 2 0 0 200 600 800 400 Pin, INPUT POWER (MILLWATTS) 1000 VDD = 28 V IDQ = 25 mA Pout , OUTPUT POWER (WATTS) f = 100 MHz 150 MHz 200 MHz 10 9 8 7 6 5 4 3 2 1 0 0 200 400 600 800 Pin, INPUT POWER (MILLWATTS) 1000 VDD = 13.5 V IDQ = 25 mA 200 MHz 150 MHz f = 100 MHz Figure 2. Output Power versus Input Power Figure 3. Output Power versus Input Power 20 18 Pout , OUTPUT POWER (WATTS) 16 14 12 10 8 6 4 2 0 0 1 2 Pin, INPUT POWER (WATTS) 3 4 VDD = 13.5 V f = 400 MHz IDQ = 25 mA Pout , OUTPUT POWER (WATTS) VDD = 28 V 24 21 18 15 400 mW 12 9 6 3 0 12 14 IDQ = 25 mA f = 100 MHz 16 20 24 18 22 VDD, SUPPLY VOLTAGE (VOLTS) 26 28 200 mW Pin = 600 mW Figure 4. Output Power versus Input Power Figure 5. Output Power versus Supply Voltage 24 Pin = 900 mW Pout , OUTPUT POWER (WATTS) Pout , OUTPUT POWER (WATTS) 21 18 600 mW 15 12 9 6 3 0 12 14 300 mW 24 21 18 15 0.7 W 12 9 6 3 26 28 0 12 14 0.4 W IDQ = 25 mA f = 200 MHz 16 18 20 22 24 VDD, SUPPLY VOLTAGE (VOLTS) 26 28 Pin = 1 W IDQ = 25 mA f = 150 MHz 16 20 24 18 22 VDD, SUPPLY VOLTAGE (VOLTS) Figure 6. Output Power versus Supply Voltage Figure 7. Output Power versus Supply Voltage REV 7 4 TYPICAL CHARACTERISTICS 20 Pout , OUTPUT POWER (WATTS) Pout , OUTPUT POWER (WATTS) 18 16 14 12 10 8 6 4 2 0 12 14 16 18 20 22 24 VDD, SUPPLY VOLTAGE (VOLTS) 26 28 1W IDQ = 25 mA f = 400 MHz Pin = 3 W 2W 16 14 12 10 8 6 4 2 0 –7 –6 –5 –4 –3 –2 –1 0 1 VGS, GATE–SOURCE VOLTAGE (VOLTS) 2 3 TYPICAL DEVICE SHOWN, VGS(th) = 3 V 400 MHz 150 MHz VDD = 28 V IDQ = 25 mA Pin = CONSTANT 400 MHz Figure 8. Output Power versus Supply Voltage Figure 9. Output Power versus Gate Voltage 2 I D, DRAIN CURRENT (MILLAMPS) 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 VDS, GATE–SOURCE VOLTAGE (VOLTS) 6 7 VDS = 10 V TYPICAL DEVICE SHOWN, VGS(th) = 3 V VGS, GATE-SOURCE VOLTAGE (NORMALIZED) 1.04 1.03 1.02 1.01 1 0.99 0.98 0.97 0.96 0.95 0.94 – 25 0 VDS = 28 V ID = 750 mA 500 mA 250 mA 25 mA 25 75 125 50 100 TC, CASE TEMPERATURE (°C) 150 175 Figure 10. Drain Current versus Gate Voltage (Transfer Characteristics) Figure 11. Gate–Source Voltage versus Case Temperature 100 VGS = 0 V f = 1 MHz Coss 10 5 3 2 1 TC = 25°C 180 C, CAPACITANCE (pF) 60 40 Ciss Crss I D, DRAIN CURRENT (AMPS) 28 20 0 0.3 0.2 0.1 0 4 16 20 24 8 12 VDS, DRAIN–SOURCE VOLTAGE (VOLTS) 1 2 10 3 5 20 30 50 70 VDS, DRAIN–SOURCE VOLTAGE (VOLTS) 100 Figure 12. Capacitance versus Drain–Source Voltage Figure 13. DC Safe Operating Area REV 7 5 TYPICAL CHARACTERISTICS TYPICAL 400 MHz PERFORMANCE 40 Pout , OUTPUT POWER (WATTS) Pout , OUTPUT POWER (WATTS) 35 30 25 20 15 10 5 0 0 0.5 1 2.5 1.5 2 Pin, INPUT POWER (WATTS) 3 3.5 VDD = 28 V IDQ = 100 mA f = 400 MHz 40 35 30 25 20 15 10 5 0 –4 –3 –2 0 2 –1 1 VGS, GATE–SOURCE VOLTAGE (VOLTS) 3 4 f = 400 MHz VDD = 28 V IDQ = 100 mA Pin = CONSTANT TYPICAL DEVICE SHOWN, VGS(th) = 3 V Figure 14. Output Power versus Input Power Figure 15. Output Power versus Gate Voltage REV 7 6 400 200 Zin{ 150 200 f = 100 MHz ZOL* 150 VDD = 28 V, IDQ = 25 mA, Pout = 15 W f MHz 100 150 200 400 Zin{ OHMS 7.5 – j9.73 4.11 – j7.56 2.66 – j6.39 2.39 – j2.18 f = 100 MHz 400 VDD = 28 V, IDQ = 25 mA, Pout = 15 W f MHz 100 150 200 400 ZOL* OHMS 13.7 – j16.8 9.08 – j15.38 4.74 – j8.92 4.28 – j4.17 {27 Ω Shunt Resistor Gate–to–Ground ZOL* = Conjugate of the optimum load impedance into which the device operates at a given output power, voltage and frequency. Figure 16. Large–Signal Series Equivalent Input Impedance, Zin† Figure 17. Large–Signal Series Equivalent Output Impedance, ZOL* 400 225 Zin & ZOL* are given from drain–to–drain and gate–to–gate respectively. 400 Zin 150 225 ZOL* 150 100 100 50 f = 30 MHz f MHz 30 50 100 150 225 400 VDD = 28 V, IDQ = 100 mA, Pout = 30 W Zin{ Ohms 59.3 – j24 48 – j33.5 20.5 – j34.2 4.77 – j25.4 3 – j9.5 2.34 – j3.31 ZOL* Ohms 40.1 – j8.52 37 – j11.9 29 – j16.5 20.6 – j19 13 – j16.7 10.2 – j14.3 50 f = 30 MHz Feedback loops: 560 ohms in series with 0.1 µF Drain to gate, each side of push–pull FET ZOL* = Conjugate of the optimum load impedance into which the device operates at a given output power, voltage and frequency. Figure 18. Input and Outut Impedance REV 7 7 f (MHz) 2.0 5.0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 225 250 275 300 325 350 375 400 425 450 475 500 525 550 575 600 625 650 675 700 725 750 775 800 S11 |S11| 0.988 0.970 0.923 0.837 0.784 0.751 0.733 0.720 0.709 0.707 0.706 0.708 0.711 0.714 0.717 0.720 0.723 0.727 0.732 0.735 0.738 0.740 0.746 0.742 0.744 0.751 0.757 0.760 0.762 0.774 0.775 0.781 0.787 0.792 0.797 0.801 0.810 0.816 0.818 0.825 0.834 0.837 0.836 0.841 0.844 0.846 φ – 11 – 27 – 52 – 88 – 111 – 125 – 135 – 1 42 – 147 – 152 – 155 – 157 – 159 – 161 – 163 – 164 – 165 – 166 – 167 – 168 – 169 – 170 – 171 – 172 – 173 – 174 – 175 – 176 – 177 – 179 – 179 + 179 + 177 + 176 + 175 + 175 + 174 + 173 + 171 + 170 + 169 + 168 + 167 + 166 + 165 + 163 |S21| 41.19 40.07 35.94 27.23 20.75 16.49 13.41 11.43 9.871 8.663 7.784 7.008 6.435 5.899 5.439 5.068 4.709 4.455 4.200 3.967 3.756 3.545 3.140 2.783 2.540 2.323 2.140 1.963 1.838 1.696 1.590 1.493 1.415 1.332 1.259 1.185 1.145 1.091 1.041 0.994 0.962 0.922 0.879 0.838 0.824 0.785 S21 φ 173 164 149 129 117 108 103 99 96 93 91 88 86 85 82 80 80 78 77 75 74 73 69 67 64 60 58 54 52 50 48 46 43 40 38 37 36 34 32 30 29 27 25 25 24 21 |S12| 0.006 0.014 0.026 0.040 0.046 0.048 0.050 0.050 0.050 0.051 0.051 0.051 0.051 0.051 0.052 0.052 0.052 0.052 0.052 0.052 0.052 0.052 0.053 0.053 0.054 0.055 0.058 0.059 0.062 0.065 0.068 0.071 0.074 0.079 0.083 0.088 0.094 0.101 0.106 0.112 0.119 0.127 0.133 0.140 0.148 0.154 S12 φ 67 62 54 36 27 22 19 16 14 13 13 13 14 15 16 17 18 18 18 19 19 20 22 25 27 29 32 35 38 41 43 46 47 48 50 51 52 52 53 53 53 53 52 53 52 50 |S22| 0.729 0.720 0.714 0.690 0.684 0.680 0.679 0.678 0.679 0.683 0.682 0.680 0.681 0.682 0.684 0.684 0.686 0.690 0.694 0.699 0.703 0.706 0.717 0.724 0.724 0.736 0.749 0.758 0.768 0.783 0.793 0.805 0.813 0.825 0.831 0.843 0.855 0.869 0.871 0.884 0.890 0.906 0.909 0.917 0.933 0.941 S22 φ – 12 – 31 – 58 – 96 – 118 – 131 – 139 – 145 – 149 – 153 – 155 – 157 – 158 – 159 – 160 – 161 – 161 – 161 – 162 – 162 – 163 – 163 – 163 – 163 – 163 – 163 – 163 – 163 – 163 – 163 – 163 – 163 – 164 – 164 – 164 – 164 – 164 – 165 – 165 – 165 – 165 – 166 – 167 – 167 – 167 – 168 Table 1. Common Source Scattering Parameters VDS = 28 V, ID = 0.5 A REV 7 8 +j50 +j25 +j100 +j150 +j10 f = 800 MHz 0 10 25 50 100 150 250 500 +90° +120° +60° f = 800 MHz S12 +30° 600 400 180° – j500 0.18 0.14 0.10 0.06 0.02 +150° +j250 +j500 70 400 150 0.16 0.12 0.08 0.04 0° – j10 70 S11 – j250 – j150 –150° – 60° –90° – 30° – j25 – j50 – j100 –120° Figure 19. S11, Input Reflection Coefficient versus Frequency VDS = 28 V ID = 0.5 A Figure 20. S12, Reverse Transmission Coefficient versus Frequency VDS = 28 V ID = 0.5 A +90° +120° 70 100 +150° S21 150 400 f = 800 MHz +30° +j10 +60° +j25 +j50 +j100 +j150 +j250 +j500 0° f = 800 MHz 150 400 70 – j10 S22 – j25 – j50 0 10 25 50 100 150 250 500 180° 8 6 4 2 – j500 – j250 – j150 – j100 –150° – 60° – 90° – 30° –120° Figure 21. S21, Forward Transmission Coefficient versus Frequency VDS = 28 V ID = 0.5 A Figure 22. S22, Output Reflection Coefficient versus Frequency VDS = 28 V ID = 0.5 A REV 7 9 DESIGN CONSIDERATIONS The MRF136 is an RF power N–Channel enhancement mode field–effect transistor (FET) designed especially for HF and VHF power amplifier applications. M/A-COM RF MOS FETs feature planar design for optimum manufacturability. M/A-COM Application Note AN211A, FETs in Theory and Practice, is suggested reading for those not familiar with the construction and characteristics of FETs. The major advantages of RF power FETs include high gain, low noise, simple bias systems, relative immunity from thermal runaway, and the ability to withstand severely mismatched loads without suffering damage. Power output can be varied over a wide range with a low power dc control signal, thus facilitating manual gain control, ALC and modulation. DC BIAS The MRF136 is an enhancement mode FET and, therefore, does not conduct when drain voltage is applied without gate bias. A positive gate voltage causes drain current to flow (see Figure 10). RF power FETs require forward bias for optimum gain and power output. A Class AB condition with quiescent drain current (IDQ) in the 25 –100 mA range is sufficient for many applications. For special requirements such as linear amplification, IDQ may have to be adjusted to optimize the critical parameters. The MOS gate is a dc open circuit. Since the gate bias circuit does not have to deliver any current to the FET, a simple resistive divider arrangement may sometimes suffice for this function. Special applications may require more elaborate gate bias systems. GAIN CONTROL Power output of the MRF136 may be controlled from rated values down to the milliwatt region (>20 dB reduction in power output with constant input power) by varying the dc gate voltage. This feature, not available in bipolar RF power devices, facilitates the incorporation of manual gain control, AGC/ALC and modulation schemes into system designs. A full range of power output control may require dc gate voltage excursions into the negative region. AMPLIFIER DESIGN Impedance matching networks similar to those used with bipolar transistors are suitable for MRF136. See M/A-COM Application Note AN721, Impedance Matching Networks Applied to RF Power Transistors. Both small signal scattering parameters and large signal impedance parameters are provided. Large signal impedances should be used for network designs wherever possible. While the s parameters will not produce an exact design solution for high power operation, they do yield a good first approximation. This is particularly useful at frequencies outside those presented in the large signal impedance plots. RF power FETs are triode devices and are therefore not unilateral. This, coupled with the very high gain, yields a device capable of self oscillation. Stability may be achieved using techniques such as drain loading, input shunt resistive loading, or feedback. S parameter stability analysis can provide useful information in the selection of loading and/or feedback to insure stable operation. The MRF136 was characterized with a 27 ohm input shunt loading resistor. For further discussion of RF amplifier stability and the use of two port parameters in RF amplifier design, see M/A-COM Application Note AN215A. LOW NOISE OPERATION Input resistive loading will degrade noise performance, and noise figure may vary significantly with gate driving impedance. A low loss input matching network with its gate impedance optimized for lowest noise is recommended. REV 7 10 PACKAGE DIMENSIONS A U M Q 1 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. M DIM A B C D E H J K M Q R S U STYLE 2: PIN 1. 2. 3. 4. SEATING PLANE SOURCE GATE SOURCE DRAIN R 2 3 B S D K INCHES MIN MAX 0.960 0.990 0.370 0.390 0.229 0.281 0.215 0.235 0.085 0.105 0.150 0.108 0.004 0.006 0.395 0.405 40 _ 50 _ 0.113 0.130 0.245 0.255 0.790 0.810 0.720 0.730 MILLIMETERS MIN MAX 24.39 25.14 9.40 9.90 5.82 7.13 5.47 5.96 2.16 2.66 3.81 4.57 0.11 0.15 10.04 10.28 40 _ 50 _ 2.88 3.30 6.23 6.47 20.07 20.57 18.29 18.54 J H C E CASE 211–07 ISSUE N Specifications subject to change without notice. n North America: Tel. (800) 366-2266, Fax (800) 618-8883 n Asia/Pacific: Tel.+81-44-844-8296, Fax +81-44-844-8298 n Europe: Tel. +44 (1344) 869 595, Fax+44 (1344) 300 020 Visit www.macom.com for additional data sheets and product information. REV 7 11