MRF137

SEMICONDUCTOR TECHNICAL DATA Order this document by MRF137/D The RF MOSFET Line RF Power Field-Effect Transistor N–Channel Enhancement–Mode . . . designed for wideband large–signal output and driver stages up to 400 MHz range. • Guaranteed 28 Volt, 150 MHz Performance Output Power = 30 Watts Minimum Gain = 13 dB Efficiency — 60% (Typical) • Small–Signal and Large–Signal Characterization • Typical Performance at 400 MHz, 28 Vdc, 30 W Output = 7.7 dB Gain • 100% Tested For Load Mismatch At All Phase Angles With 30:1 VSWR • Low Noise Figure — 1.5 dB (Typ) at 1.0 A, 150 MHz • Excellent Thermal Stability, Ideally Suited For Class A Operation • Facilitates Manual Gain Control, ALC and Modulation Techniques D MRF137 30 W, to 400 MHz N–CHANNEL MOS BROADBAND RF POWER FET G CASE 211–07, STYLE 2 S Rating Drain–Source Voltage Drain–Gate Voltage (RGS = 1.0 MΩ) Gate–Source Voltage Drain Current — Continuous Total Device Dissipation @ TC = 25°C Derate above 25°C Storage Temperature Range Operating Junction Temperature Symbol VDSS VDGR VGS ID PD Tstg TJ Value 65 65 ±40 5.0 100 0.571 –65 to +150 200 Unit Vdc Vdc Vdc Adc Watts W/°C °C °C MAXIMUM RATINGS THERMAL CHARACTERISTICS Characteristic Thermal Resistance, Junction to Case Symbol RθJC Max 1.75 Unit °C/W Handling and Packaging — MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and packaging MOS devices should be observed. REV 6 1 MRF137 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain–Source Breakdown Voltage (VGS = 0, ID = 10 mA) Zero Gate Voltage Drain Current (VDS = 28 V, VGS = 0) Gate–Source Leakage Current (VGS = 20 V, VDS = 0) V(BR)DSS IDSS IGSS 65 — — — — — — 4.0 1.0 Vdc mAdc µAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = 10 V, ID = 25 mA) Forward Transconductance (VDS = 10 V, ID = 500 mA) VGS(th) gfs 1.0 500 3.0 750 6.0 — Vdc mmhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz) Output Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz) Reverse Transfer Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz) Ciss Coss Crss — — — 48 54 11 — — — pF pF pF FUNCTIONAL CHARACTERISTICS Noise Figure (VDS = 28 Vdc, ID = 1.0 A, f = 150 MHz) Common Source Power Gain (VDD = 28 Vdc, Pout = 30 W, IDQ = 25 mA) f = 150 MHz (Figure 1) f = 400 MHz (Figure 14) η ψ No Degradation in Output Power NF Gps 13 — 50 16 7.7 60 — — — % — 1.5 — dB dB Drain Efficiency (Figure 1) (VDD = 28 Vdc, Pout = 30 W, f = 150 MHz, IDQ = 25 mA) Electrical Ruggedness (Figure 1) (VDD = 28 Vdc, Pout = 30 W, f = 150 MHz, IDQ = 25 mA, VSWR 30:1 at All Phase Angles) R4 BIAS ADJUST + - RFC2 C9 C10 + VDD = 28 V R3 D1 C7 C8 RFC1 R2 C6 RF INPUT C1 L1 R1 C5 L2 DUT L3 RF OUTPUT C2 C3 C4 C1 — Arco 403, 3.0–35 pF, or equivalent C2 — Arco 406, 15–115 pF, or equivalent C3 — 56 pF Mini–Unelco, or equivalent C4 — Arco 404, 8.0–60 pF, or equivalent C5 — 680 pF, 100 Mils Chip C6 — 0.01 µF, 100 V, Disc Ceramic C7 — 100 µF, 40 V C8 — 0.1 µF, 50 V, Disc Ceramic C9, C10 — 680 pF Feedthru D1 — 1N5925A Motorola Zener L1 — 2 Turns, 0.29″ ID, #18 AWG Enamel, Closewound L2 — 1–1/4 Turns, 0.2″ ID, #18 AWG Enamel, Closewound L3 — 2 Turns, 0.2″ ID, #18 AWG Enamel, Closewound RFC1 — 20 Turns, 0.30″ ID, #20 AWG Enamel, Closewound RFC2 — Ferroxcube VK–200 — 19/4B R1 — 10 kΩ, 1/2 W Thin Film R2 — 10 kΩ, 1/4 W R3 — 10 Turns, 10 kΩ R4 — 1.8 kΩ, 1/2 W Board — G10, 62 Mils Figure 1. 150 MHz Test Circuit REV 6 2 50 Pout , OUTPUT POWER (WATTS) 40 30 20 10 0 f = 100 MHz Pout , OUTPUT POWER (WATTS) 150 MHz 200 MHz 20 f = 100 MHz 15 150 MHz 200 MHz 10 VDD = 28 V IDQ = 25 mA 5 VDD = 13.5 V IDQ = 25 mA 0 0.5 1 1.5 Pin, INPUT POWER (WATTS) 2 0 0 1 2 Pin, INPUT POWER (WATTS) 3 4 Figure 2. Output Power versus Input Power Figure 3. Output Power versus Input Power 40 Pout , OUTPUT POWER (WATTS) Pout , OUTPUT POWER (WATTS) f = 400 MHz IDQ = 25 mA 30 VDD = 28 V 50 40 30 20 10 0 Pin = 1 W 0.5 W 0.25 W 20 VDD = 13.5 V 10 0 IDQ = 25 mA f = 100 MHz 12 20 24 16 VDD, SUPPLY VOLTAGE (VOLTS) 28 0 2 4 6 Pin, INPUT POWER (WATTS) 8 10 Figure 4. Output Power versus Input Power Figure 5. Output Power versus Supply Voltage 50 Pout , OUTPUT POWER (WATTS) Pout , OUTPUT POWER (WATTS) 40 30 20 10 0 12 Pin = 1.5 W 50 40 30 20 10 0 12 Pin = 2 W 1.5 W 0.75 W 0.75 W 0.5 W IDQ = 25 mA f = 150 MHz 20 24 16 VDD, SUPPLY VOLTAGE (VOLTS) 28 IDQ = 25 mA f = 200 MHz 16 20 24 VDD, SUPPLY VOLTAGE (VOLTS) 28 Figure 6. Output Power versus Supply Voltage Figure 7. Output Power versus Supply Voltage REV 6 3 50 Pout , OUTPUT POWER (WATTS) 40 30 20 2W 10 0 12 IDQ = 25 mA f = 400 MHz 20 24 16 VDD, SUPPLY VOLTAGE (VOLTS) 28 Pout , OUTPUT POWER (WATTS) 30 25 20 15 10 5 0 -9 -8 -6 -4 -2 0 VGS, GATE-SOURCE VOLTAGE (VOLTS) 1 2 3 TYPICAL DEVICE SHOWN, VGS(th) = 3 V VDD = 28 V IDQ = 25 mA Pin = CONSTANT Pin = 8 W 5W 400 MHz 150 MHz Figure 8. Output Power versus Supply Voltage Figure 9. Output Power versus Gate Voltage VGS, GATE SOURCE VOLTAGE (NORMALIZED) 3 I D, DRAIN CURRENT (AMPS) TYPICAL DEVICE SHOWN, VGS(th) = 3 V 2 1.02 1 0.98 0.96 0.94 0.92 -25 VDS = 28 V ID = 1.25 A 1A 750 mA 1 VDS = 10 V 500 mA 25 mA 200 mA 0 1 2 3 4 5 6 VGS, GATE-SOURCE VOLTAGE (VOLTS) 7 0 25 50 75 100 125 TC, CASE TEMPERATURE (°C) 150 175 Figure 10. Drain Current versus Gate Voltage (Transfer Characteristics) Figure 11. Gate Source Voltage versus Case Temperature 200 180 140 120 100 80 60 40 20 0 0 4 8 12 16 20 VDS, DRAIN-SOURCE VOLTAGE (VOLTS) 24 28 Ciss Crss Coss I D, DRAIN CURRENT (AMPS) 160 C, CAPACITANCE (pF) VGS = 0 V f = 1 MHz 10 5 2 1 0.5 TC = 25°C 0.1 1 2 5 10 20 VDS, DRAIN-SOURCE VOLTAGE (VOLTS) 60 100 Figure 12. Capacitance versus Drain–Source Voltage Figure 13. DC Safe Operating Area REV 6 4 R4 BIAS ADJUST R3 D1 C9 R2 R1 RF INPUT Z1 C5 C1 C6 C2 Z2 Z3 DUT RFC1 C10 + - C11 RFC2 VDD = 28 V C12 C13 C8 Z4 Z5 Z6 RF OUTPUT C7 C3 C4 C1, C2, C3, C4 — 0–20 pF Johanson, or equivalent C5, C8 — 270 pF, 100 Mil Chip C6, C7 — 24 pF Mini–Unelco, or equivalent C9 — 0.01 µF, 100 V, Disc Ceramic C10 — 100 µF, 40 V C11 — 0.1 µF, 50 V, Disc Ceramic C12, C13 — 680 pF Feedthru D1 — 1N5925A Motorola Zener R1, R2 — 10 kΩ, 1/4 W R3 — 10 Turns, 10 kΩ R4 — 1.8 kΩ, 1/2 W Z1 — 2.9″ x 0.166″ Microstrip Z2, Z4 — 0.35″ x 0.166″ Microstrip Z3 — 0.40″ x 0.166″ Microstrip Z5 — 1.05″ x 0.166″ Microstrip Z6 — 1.9″ x 0.166″ Microstrip RFC1 — 6 Turns, 0.300″ ID, #20 AWG Enamel, Closewound RFC2 — Ferroxcube VK–200 — 19/4B Board — Glass Teflon, 62 Mils Figure 14. 400 MHz Test Circuit Zin 150 200 200 400 150 f = 100 MHz ZOL* 400 f = 100 MHz VDD = 28 V, IDQ = 25 mA, Pout = 30 W f MHz 100 150 200 400 Zin{ Ohms 2.11 - j11.07 1.77 - j7.64 1.85 - j3.75 1.74 + j3.62 ZOL* Ohms 8.02 - j2.89 5.75 - j3.02 3.52 - j2.67 2.88 - j1.52 ZOL* = Conjugate of the optimum load impedance into which the device output operates at a given out put power, voltage and frequency. Figure 15. Large–Signal Series Equivalent Input and Output Impedance, Zin, ZOL* REV 6 5 f (MHz) 2.0 5.0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 225 250 275 300 325 350 375 400 425 450 475 500 525 550 575 600 625 650 675 700 725 750 775 800 S11 |S11| 0.977 0.919 0.852 0.817 0.814 0.811 0.812 0.813 0.815 0.816 0.817 0.817 0.818 0.820 0.821 0.822 0.823 0.824 0.825 0.827 0.829 0.831 0.836 0.846 0.853 0.853 0.856 0.857 0.861 0.865 0.875 0.881 0.886 0.887 0.888 0.896 0.907 0.910 0.910 0.920 0.938 0.943 0.934 0.940 0.953 0.959 ∠φ –32 –70 –109 –140 –153 –159 –164 –166 –168 –170 –171 –172 –173 –173 –173 –174 –175 –175 –176 –176 –177 –177 –178 –178 –179 –179 –179 +179 +179 +178 +178 +178 +177 +177 +176 +176 +175 +175 +174 +174 +173 +171 +170 +170 +169 +168 |S21| 59.48 48.67 33.50 19.05 13.11 9.88 7.98 6.66 5.708 5.003 4.560 4.170 3.670 3.420 3.170 2.980 2.826 2.650 2.438 2.325 2.175 2.084 1.824 1.621 1.462 1.319 1.194 1.089 1.014 0.927 0.876 0.810 0.755 0.694 0.677 0.625 0.603 0.585 0.563 0.543 0.533 0.515 0.491 0.475 0.477 0.467 S21 ∠φ 163 142 122 106 99 95 92 89 86 84 83 81 80 79 79 78 77 76 75 73 72 71 69 66 64 61 59 56 54 51 49 46 44 41 39 36 34 32 30 28 26 24 22 22 21 17 |S12| 0.011 0.024 0.032 0.037 0.038 0.038 0.038 0.038 0.038 0.038 0.038 0.039 0.039 0.039 0.039 0.039 0.039 0.039 0.039 0.039 0.039 0.039 0.039 0.039 0.039 0.040 0.040 0.040 0.042 0.043 0.045 0.046 0.046 0.051 0.052 0.055 0.058 0.061 0.065 0.069 0.074 0.078 0.079 0.084 0.090 0.093 S12 ∠φ 67 44 29 16 14 13 12 12 11 11 12 13 13 13 13 13 14 14 14 15 16 16 18 21 23 25 27 30 32 35 37 40 43 43 43 45 45 45 45 46 47 47 46 48 48 48 |S22| 0.661 0.692 0.747 0.768 0.774 0.782 0.787 0.787 0.787 0.787 0.787 0.787 0.788 0.788 0.788 0.788 0.788 0.790 0.792 0.793 0.796 0.799 0.805 0.816 0.822 0.833 0.828 0.842 0.849 0.856 0.866 0.870 0.875 0.888 0.890 0.898 0.913 0.918 0.945 0.952 0.974 0.958 0.953 0.943 0.957 0.957 S22 ∠φ –36 –78 –117 –146 –157 –162 –165 –168 –169 –170 –171 –172 –172 –173 –173 –173 –173 –174 –174 –174 –174 –174 –174 –174 –174 –174 –174 –174 –174 –174 –174 –174 –174 –174 –174 –174 –174 –174 –174 –174 –174 –176 –177 –177 –177 –179 Table 1. Common Source Scattering Parameters 50 Ω System VDS = 28 V, ID = 0.75 A REV 6 6 +j50 +j25 +j100 +j150 +j10 800 400 +j250 +j500 10 25 50 100 150 250 500 +90° +120° +60° 800 +150° 600 400 180° 0.1 -j500 -j250 -150° S12 -30° .08 .06 .04 .02 +30° 0 f = 50 MHz 150 f = 50 MHz 0° -j10 S11 -j25 -j50 -j100 -j150 -120° -60° -90° Figure 16. S11, Input Reflection Coefficient versus Frequency VDS = 28 V ID = 0.75 A Figure 17. S12, Reverse Transmission Coefficient versus Frequency VDS = 28 V ID = 0.75 A +90° +120° f = 50 MHz +60° +j25 +j50 +j100 +j150 +30° +j10 +j250 +j500 0° 0 800 25 50 100 150 250 500 +150° 150 180° 10 8 6 4 2 400 800 400 150 f = 50 MHz -j500 -j250 S22 -j150 -j100 -j50 -150° S21 -30° -j10 -120° -60° -90° -j25 Figure 18. S21, Forward Transmission Coefficient versus Frequency VDS = 28 V ID = 0.75 A Figure 19. S22, Output Reflection Coefficient versus Frequency VDS = 28 V ID = 0.75 A REV 6 7 DESIGN CONSIDERATIONS The MRF137 is a RF power N–Channel enhancement mode field–effect transistor (FET) designed especially for VHF power amplifier applications. M/A-COM RF MOS FETs feature a vertical structure with a planar design, thus avoiding the processing difficulties associated with V–groove vertical power FETs. M/A-COM Application Note AN211A, FETs in Theory and Practice, is suggested reading for those not familiar with the construction and characteristics of FETs. The major advantages of RF power FETs include high gain, low noise, simple bias systems, relative immunity from thermal runaway, and the ability to withstand severely mismatched loads without suffering damage. Power output can be varied over a wide range with a low power dc control signal, thus facilitating manual gain control, ALC and modulation. DC BIAS The MRF137 is an enhancement mode FET and, therefore, does not conduct when drain voltage is applied. Drain current flows when a positive voltage is applied to the gate. See Figure 10 for a typical plot of drain current versus gate voltage. RF power FETs require forward bias for optimum performance. The value of quiescent drain current (IDQ) is not critical for many applications. The MRF137 was characterized at IDQ = 25 mA, which is the suggested minimum value of IDQ. For special applications such as linear amplification, IDQ may have to be selected to optimize the critical parameters. The gate is a dc open circuit and draws no current. Therefore, the gate bias circuit may generally be just a simple resistive divider network. Some special applications may require a more elaborate bias system. GAIN CONTROL Power output of the MRF137 may be controlled from its rated value down to zero (negative gain) by varying the dc gate voltage. This feature facilitates the design of manual gain control, AGC/ALC and modulation systems. (See Figure 9.) AMPLIFIER DESIGN Impedance matching networks similar to those used with bipolar VHF transistors are suitable for MRF137. See M/A-COM Application Note AN721, Impedance Matching Networks Applied to RF Power Transistors. The higher input impedance of RF MOS FETs helps ease the task of broadband network design. Both small signal scattering parameters and large signal impedances are provided. While the s–parameters will not produce an exact design solution for high power operation, they do yield a good first approximation. This is an additional advantage of RF MOS power FETs. RF power FETs are triode devices and, therefore, not unilateral. This, coupled with the very high gain of the MRF137, yields a device capable of self oscillation. Stability may be achieved by techniques such as drain loading, input shunt resistive loading, or output to input feedback. Two port parameter stability analysis with the MRF137 s–parameters provides a useful tool for selection of loading or feedback circuitry to assure stable operation. See M/A-COM Application Note AN215A for a discussion of two port network theory and stability. REV 6 8 PACKAGE DIMENSIONS A U M Q 1 4 M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E H J K M Q R S U INCHES MIN MAX 0.960 0.990 0.370 0.390 0.229 0.281 0.215 0.235 0.085 0.105 0.150 0.108 0.004 0.006 0.395 0.405 40 _ 50 _ 0.113 0.130 0.245 0.255 0.790 0.810 0.720 0.730 MILLIMETERS MIN MAX 24.39 25.14 9.40 9.90 5.82 7.13 5.47 5.96 2.16 2.66 3.81 4.57 0.11 0.15 10.04 10.28 40 _ 50 _ 2.88 3.30 6.23 6.47 20.07 20.57 18.29 18.54 SOURCE GATE SOURCE DRAIN R 2 3 B S D K J H C E SEATING PLANE STYLE 2: PIN 1. 2. 3. 4. CASE 211–07 ISSUE N Specifications subject to change without notice. n North America: Tel. (800) 366-2266, Fax (800) 618-8883 n Asia/Pacific: Tel.+81-44-844-8296, Fax +81-44-844-8298 n Europe: Tel. +44 (1344) 869 595, Fax+44 (1344) 300 020 Visit www.macom.com for additional data sheets and product information. REV 6 9