TB62778FNG

TENTATIVE TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic TB62778FNG TB62778FNG 8-Channel Constant-Current LED Driver of the 3.3-V and 5-V Power Supply Voltage Operation The TB62778FNG is comprised of constant-current drivers designed for LEDs and LED panel displays. The regulated current sources are designed to provide a constant current, which is adjustable through one external resistor. The TB62778FNG incorporates eight channels of shift registers, latches, AND gates and constant-current outputs. Fabricated using the Bi-CMOS process, the TB62778FNG satisfies the system requirement of high-speed data transmission. The TB62778FNG is RoHS. Weight: 0.07 g (typ.) Features • • • • • Power supply voltages: VDD = 3.3 V/5 V Output drive capability and output count: 50 mA × 8 channels Constant-current output range: 5 to 40 mA Voltage applied to constant-current output terminals: 0.4 V (IOUT = 5 to 40 mA) Current adjustment (via 7-bit serial data): The MSB, or the HC bit, selects the output current range: 25% to 50% range when HC = 0 or 50% to 100% range when HC = 1 The six LSB bits are used to adjust the current in 64 steps within the selected range. Designed for common-anode LEDs Thermal shutdown (TSD) Power on reset (POR) Output-open detection (OOD) and output-short detection (OSD) Input signal voltage level: 3.3-V and 5-V CMOS interfaces (Schmitt trigger input) Maximum output voltage: 25V Serial data transfer rate: 25 MHz (max) @cascade connection Operating temperature range: Topr = −40 to 85°C Package: SSOP-P-225-0.65B Constant-current accuracy Output Voltage 0.4 V to 4 V Current accuracy Between Channels ±3% Current Accuracy Between ICs ±6% Output Current 15 mA • • • • • • • • • • 1 (Ver.0.0) 08-02-07 TENTATIVE Pin Assignment (top view) GND SERIAL-IN CLOCK LATCH OUT0 OUT1 OUT2 OUT3 VDD R-EXT SERIAL-OUT ENABLE OUT7 OUT6 OUT5 OUT4 TB62778FNG Block Diagram OUT0 OUT1 OUT7 R-EXT I-REG Error detection TSD VDD POR ENABLE Q ST R D LATCH Q ST R D Q ST R D GND Special mode SERIAL-IN D0 Q0 Q1 Q7 8-bit shift register D0 to D7 R CLOCK SERIAL-OUT D Q CK R Truth Table CLOCK LATCH ENABLE SERIAL-IN OUT0 … OUT5 … OUT7 Dn … Dn − 5 … Dn − 7 No Change Dn + 2 … Dn − 3 … Dn − 5 OFF OFF SERIAL-OUT No change No change No change No change Dn −4 H L H X X L L L H H Dn Dn + 1 Dn + 2 Dn + 3 Dn + 3 Note 1: OUT0 to OUT7 = On when Dn = H; OUT0 to OUT7 = Off when Dn = L. 2 (Ver.0.0) 08-02-07 TENTATIVE Timing Diagram n=0 CLOCK 1 2 3 4 5 6 7 TB62778FNG H L H SERIAL-IN L H LATCH L H ENABLE L ON OUT0 OFF ON OUT1 OFF ON OUT2 OFF ON OUT7 OFF H SERIAL-OUT Data applied when n = 0 L Note 1: Latches are level-sensitive, not edge-triggered. Note 2: The TB62778FNG can be used at 3.3 V or 5.0 V. However, the VDD supply voltage must be equal to the input voltage. Note 3: Serial data is shifted out of SERIAL-OUT on the falling edge of CLOCK. Note 4: The latches hold data while the LATCH terminal is held Low. When the LATCH terminal is High, the latches do not hold data and pass it transparently. When the ENABLE terminal is Low, OUT0 to OUT7 toggle between ON and OFF according to the data. When the ENABLE terminal is High, OUT0 to OUT7 are forced OFF. 3 (Ver.0.0) 08-02-07 TENTATIVE Terminal Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name GND SERIAL-IN CLOCK LATCH TB62778FNG Function GND terminal Serial data input terminal Serial clock input terminal Latch input terminal Constant-current output terminal Constant-current output terminal Constant-current output terminal Constant-current output terminal Constant-current output terminal Constant-current output terminal Constant-current output terminal Constant-current output terminal Output enable input terminal All outputs ( OUT0 to OUT7 ) are disabled when the ENABLE terminal is driven High, and enabled when it is driven Low. Serial data output terminal. Serial data is clocked out on the falling edge of CLOCK. An external resistor is connected between this terminal and ground. OUT0 to OUT7 are adjusted to the same current value. Power supply terminal OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 ENABLE SERIAL-OUT R-EXT VDD Equivalent Circuits for Inputs and Outputs 1. ENABLE Terminal VDD R (UP) 2. LATCH Terminal VDD ENABLE LATCH GND GND R (DOWN) 3. CLOCK and SERIAL-IN Terminals VDD 4. SERIAL-OUT Terminal VDD CLOCK, SERIAL-IN SERIAL-OUT GND GND 5. OUT0 to OUT7 Terminals OUT0 to OUT7 GND 4 (Ver.0.0) 08-02-07 TENTATIVE Absolute Maximum Ratings (Ta = 25°C) Characteristics Supply voltage Input voltage Output current Output voltage Power dissipation Thermal resistance Operating temperature range Storage temperature range Maximum junction temperature Symbol VDD VIN IOUT VOUT Pd Rth (j-a) Topr Tstg Tj Rating 6.0 −0.3 to VDD + 0.3 (Note 1) TB62778FNG Unit V V mA/ch V W °C/W °C °C °C 55 0.3 to 25 1.02 (Notes 2 and 3) 122 −40 to 85 −55 to 150 (Note 2) 150 Note 1: However, do not exceed 6.0 V. Note 2: When mounted on a PCB (76.2 × 114.3 × 1.6 mm; Cu = 30%; 35-µm-thick; SEMI-compliant) Note 3: Power dissipation is reduced by 1/Rth (j-a) for each °C above 25°C ambient. Operating Ranges (unless otherwise specified, Ta = −40°C to 85°C) Characteristics Supply voltage Output voltage Symbol VDD VOUT IOUT Output current IOH IOL VIH Input voltage VIL Clock frequency LATCH pulse width Test Condition ⎯ Min 3 0.4 5 ⎯ ⎯ Typ. ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max 5.5 4 40 −5 Unit V V mA/ch mA OUT0 to OUT 7 OUT0 to OUT 7 SERIAL-OUT SERIAL-OUT SERIAL-IN/CLOCK/ LATCH / ENABLE Cascade connection (Note 2) (Note 2) IOUT ≥ 20 mA 5 mA ≤ IOUT ≤ 20 mA (Note 2) (Note 2) 5 VDD 0.3 × VDD 25 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.7 × VDD GND ⎯ V fCLK twLAT twCLK twENA tSETUP1 MHz ns 20 20 2 3 5 5 5 5 CLOCK pulse width ENABLE pulse width µs Setup time tSETUP2 tSETUP3 tSETUP4 tHOLD1 (Note 2) ns 5 5 10 10 ⎯ Hold time tHOLD2 tHOLD3 tHOLD4 Maximum clock rise time Maximum clock fall time tr tf 5 5 Single operation (Notes 1 and 2) ⎯ µs Note 1: For cascade operation, the CLOCK waveform might become ambiguous, causing the tr and tf values to be large. Then it may not be possible to meet the timing requirement for data transfer. Please consider the timing carefully. Note 2: Please see the timing waveform on page 13. 5 (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Electrical Characteristics (Unless otherwise specified, Ta = 25°C, VDD = 4.5 to 5.5 V) Characteristics Output current Output current error between ICs Output current error between channels Output leakage current Symbol IOUT1 ∆IOUT1 ∆IOUT2 Test Circuit 5 5 5 5 ⎯ ⎯ Test Condition VOUT = 0.4 V, R-EXT = 1.2 kΩ VDD = 5 V, VG = 1 VOUT = 0.4 V, R-EXT = 1.2 kΩ All channels ON VDD = 5 V, VG = 1 VOUT = 0.4 V, R-EXT = 1.2 kΩ All channels ON VDD = 5 V, VG = 1 VOUT = 25 V SERIAL-IN/CLOCK/ LATCH / ENABLE SERIAL-IN/CLOCK/ LATCH / ENABLE VIN = VDD CLOCK/SERIAL-IN/ ENABLE VIN = GND CLOCK/SERIAL-IN/ LATCH IOL = 5.0 mA, VDD = 5 V IOH = −5.0 mA, VDD = 5 V 5 to 40 mA 5 to 40 mA VDD = 3 V to 5.5 V ENABLE LATCH R-EXT = OPEN, VOUT = 25.0 V R-EXT = 1.2 kΩ, VOUT = 25.0 V, All channels OFF R-EXT = 1.2 kΩ, VOUT = 0.4 V, All channels ON Min ― ― ⎯ ⎯ Typ. 15 ±3 ±1 ⎯ ⎯ ⎯ ― ― ⎯ ⎯ Max ― ±6 ±3 Unit mA ％ % µA IOZ VIH 1 VDD 0.7 × VDD GND ― ― ⎯ Input voltage VIL IIH Input current IIL VOL SERIAL-OUT output voltage VOH OOD detection voltage OSD detection voltage Changes in constant output current dependent on VDD Pull-up resistor Pull-down resistor VOOD VOSD %/VDD R (Up) R (Down) IDD (OFF) 1 Supply current IDD (OFF) 2 IDD (ON) 1 7 7 5 3 2 4 4 4 4.7 0.2 0.9 × VDD ⎯ ⎯ V 0.3 × VDD 1 µA −1 2 3 1 0.3 V 0.3 0.95 × VDD 1 200 200 ⎯ ⎯ ⎯ 0.4 VDD 2 240 240 1 5 9 V V % kΩ kΩ 160 160 ⎯ ⎯ ⎯ mA 6 (Ver.0.0) 08-02-07 TENTATIVE Test Circuit 6 TB62778FNG Switching Characteristics (Unless otherwise specified, Ta = 25°C, VDD = 4.5 to 5.5V) Characteristics Symbol tpLH1 tpLH2 tpLH3 tpLH tpHL1 tpHL2 tpHL3 tpHL Output rise time Output fall time tor tof Test Condition (Note 1) Min ⎯ ⎯ ⎯ Typ. 20 Max 300 Unit CLK- OUTn , LATCH = “H”, ENABLE = “L” LATCH − OUTn , 6 ENABLE = “L” ENABLE − OUTn , LATCH = “H” CLK-SERIAL OUT CLK- OUTn , LATCH = “H”, ENABLE = “L” LATCH − OUTn , 20 300 6 6 6 20 10 30 300 14 340 ns Propagation delay time 2 ⎯ ⎯ ⎯ 6 ENABLE = “L” ENABLE − OUTn , LATCH = “H” CLK-SERIAL OUT 10% to 90% points of OUT0 to OUT7 voltage waveforms 90% to 10% points of OUT0 to OUT7 voltage waveforms 70 340 6 6 6 6 70 10 20 125 340 14 150 300 2 ― ― Note 1: Topr = 25°C, VDD = VIH = 5 V, VIL = 0 V, REXT = 1.2 kΩ, IOUT = 15mA, VL = 5.0 V, CL = 10.5pF (see test circuit 6.) 7 (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Electrical Characteristics (Unless otherwise specified, Ta = 25°C, VDD = 3 to 3.6 V) Characteristics Output current Symbol IOUT1 ∆IOUT1 Test Circuit 5 Test Condition VOUT = 0.4 V, R-EXT = 1.2 kΩ VDD = 3.3 V, VG = 1 VOUT = 0.4 V, R-EXT = 1.2 kΩ All channels ON VDD = 3.3 V, VG = 1 VOUT = 0.4 V, R-EXT = 1.2 kΩ All channels ON VDD = 3.3 V, VG = 1 VOUT = 25 V SERIAL-IN/CLOCK/ LATCH / ENABLE SERIAL-IN/CLOCK/ LATCH / ENABLE VIN = VDD CLOCK/SERIAL-IN/ LATCH / ENABLE VIN = GND CLOCK/SERIAL-IN/ LATCH / ENABLE Min ― Typ. 15 ±3 Max ― Unit mA Output current error between ICs 5 ― ±6 % Output current error between channels Output leakage current ∆IOUT2 5 5 ⎯ ⎯ ⎯ ⎯ ±1 ⎯ ⎯ ⎯ ±3 % µA IOZ VIH 1 VDD 0.7 × VDD GND Input voltage VIL 0.3 × VDD 1 V IIH Input current IIL 2 ― ― µA ― ― −1 3 VOL SERIAL-OUT output voltage VOH OOD detection voltage OSD detection voltage Changes in constant output current dependent on VDD Pull-up resistor Pull-down resistor VOOD VOSD %/VDD R (Up) R (Down) IDD (OFF) 1 Supply current IDD (OFF) 2 IDD (ON) 1 1 7 7 5 3 2 4 4 4 IOL = 5.0 mA, VDD = 3.3 V IOH = −5.0 mA, VDD = 3.3 V 5 to 40 mA 5 to 40 mA VDD = 3 V to 5.5 V ENABLE LATCH R-EXT = OPEN, VOUT = 25.0 V R-EXT = 1.2 kΩ, VOUT = 25.0 V, All channels OFF R-EXT = 1.2 kΩ, VOUT = 0.4 V, All channels ON ⎯ ⎯ ⎯ 0.3 V ⎯ 3.0 0.2 0.9 × VDD ⎯ 0.3 0.95 × VDD 1 200 200 ⎯ ⎯ ⎯ 0.4 VDD 2 240 240 1 5 9 V V % kΩ kΩ 160 160 ⎯ ⎯ ⎯ mA 8 (Ver.0.0) 08-02-07 TENTATIVE Test Circuit 6 TB62778FNG Switching Characteristics (Unless otherwise specified, Ta = 25°C, VDD = 3 to 3.6 V) Characteristics Symbol tpLH1 tpLH2 tpLH3 tpLH tpHL1 tpHL2 tpHL3 tpHL Output rise time Output fall time tor tof Test Condition (Note 1) Min ⎯ ⎯ ⎯ Typ. ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max 300 Unit CLK- OUTn , LATCH = “H”, ENABLE = “L” LATCH - OUTn , 6 ENABLE = “L” ENABLE - OUTn , LATCH = “H” CLK-SERIAL OUT CLK- OUTn , LATCH = “H”, ENABLE = “L” LATCH - OUTn , 300 6 6 6 300 14 340 ns Propagation delay time 2 ⎯ ⎯ ⎯ 6 ENABLE = “L” ENABLE - OUTn , LATCH = “H” CLK-SERIAL OUT 10% to 90% points of OUT0 to OUT7 voltage waveforms 90% to 10% points of OUT0 to OUT7 voltage waveforms 340 6 6 6 6 340 14 150 300 2 ⎯ ⎯ Note 1: Topr = 25°C, VDD = VIH = 3.3 V, VIL = 0 V, REXT = 1.2 kΩ, IOUT = 15mA, VL = 5.0 V, CL = 10.5pF (see test circuit 6.) 9 (Ver.0.0) 08-02-07 TENTATIVE Test Circuits Test Circuit 1: High-Level and Low-Level Input Voltages (VIH/VIL) VDD TB62778FNG ENABLE F.G CLOCK LATCH OUT0 SERIAL-IN OUT7 IO = −5 mA to 5 mA CL = 10.5 pF V Test Circuit 2: High-Level Input Current (IIH) VIN = VDD VDD A A A ENABLE CLOCK LATCH OUT0 A SERIAL-IN OUT7 VDD = 4.5 to 5.5 V、3 to 3.6V R-EXT GND SERIAL-OUT CL = 10.5 pF Test Circuit 3: Low-Level Input Current (IIL) A A A A ENABLE CLOCK LATCH SERIAL-IN VDD REXT OUT0 OUT7 VDD = 4 5 to 5 5 V、3 to 3 6V R-EXT GND SERIAL-OUT CL = 10.5 pF REXT 10 (Ver.0.0) 08-02-07 VDD = 5 V、3.3V REXT VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) R-EXT GND SERIAL-OUT TENTATIVE Test Circuit 4: Supply Current TB62778FNG ENABLE F.G CLOCK LATCH OUT0 SERIAL-IN OUT7 VDD = 4.5 to 5.5 V、3 to 3.6V REXT = 1.2 kΩ Note: The output terminal is based on the power supply current conditions on page 6 and 7. Test Circuit 5: Output Current (IOUT1), Output Leakage Current (IOZ) Output Current Variations (∆IOUT1/∆IOUT2), Current Variation with VDD (%/VDD) ENABLE CLOCK F.G LATCH VDD CL = 10.5 pF VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) A R-EXT GND SERIAL-OUT OUT0 A SERIAL-IN OUT7 A VDD = 4.5 to 5.5 V、3 to 3.6V VDD = 4.5 to 5.5 V、3 to 3.6V A VOUT = 0.4 V, 25 V REXT = 1.2 kΩ Theoretical output current = 1.13 V/REXT × 16 (VG=1) Test Circuit 6: Switching Characteristics ENABLE CLOCK F.G LATCH SERIAL-IN OUT7 CL = 10.5 pF VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) R-EXT REXT = 12 kΩ CL = 10.5 pF VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) R-EXT GND SERIAL-OUT VDD RL=300Ω OUT0 CL IOUT GND SERIAL-OUT CL = 10.5 pF VL = 5 V 11 (Ver.0.0) 08-02-07 TENTATIVE Test Circuit 7: ODD and OSD Characteristics TB62778FNG F.G CLOCK SERIAL-IN VDD OUT0 V LATCH ENABLE V OUT7 VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) VDD = 4.5 V to 5.5 V、3 to 3.6V V REXT REXT = ?? kΩ GND SOUT CL = 10.5 pF VOUT1 = ?V 12 (Ver.0.0) 08-02-07 VOUT2 = ?V TENTATIVE Timing Waveforms 1. CLOCK, SERIAL-IN, SERIAL-OUT twCLK CLOCK 50% tSETUP1 SERIAL-IN 50% tHOLD1 SERIAL-OUT 50% tpLH/tpHL 50% 50% 90% 10% tr tf 90% 10% TB62778FNG 2. CLOCK, SERIAL-IN, LATCH , ENABLE , OUTn CLOCK 50% 50% SERIAL-IN tHOLD2 LATCH 50% twLAT ENABLE 50% tSETUP2 50% twENA twENA 50% 50% OUTn tpHL1/LH1 tpHL2/LH2 50% 50% tpHL3/LH3 3. OUTn 90% 90% OFF OUTn 10% tof 10% tor ON 4. Special Mode twCLK CLOCK 50% tSETUP3 tHOLD3 50% 50% tSETUP4 tHOLD4 50% 50% LATCH 50% 50% Note: The timing chart waveform may be simplified to explain a function and operation. Timing conditions must be taken care enough. 13 (Ver.0.0) 08-02-07 TENTATIVE Special Mode Sequence for Switching to Special Mode 1 CLOCK ENABLE H L L L H L H H H L 2 3 4 5 TB62778FNG LATCH Only the above signal sequence puts the TB62778FNG in special mode. In this mode, two sub-modes are available: total brightness adjustment mode and error detection (OOD/OSD) mode. While switching to special mode, data is not latched by LATCH . After power-on, the TB62778FNG defaults to normal mode. Total Brightness Adjustment Mode Writing a brightness code 0 CLOCK ENABLE H H L Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 2 3 4 5 6 7 LATCH SERIAL-IN Brightness code In total brightness adjustment mode, when LATCH is High, a brightness code in the shift register is latched into the brightness adjustment register instead of the output latches. Once latched into the brightness adjustment register, the brightness code is held until the TB62778FNG is powered off or it is overwritten with a new code. Adjusting the total brightness Bit definition of the brightness code Bit 0 Reserved Default 1 Bit 1 HC 1 Bit 2 AG5 1 Bit 3 AG4 1 Bit 4 AG3 1 Bit 5 AG2 1 Bit 6 AG1 1 Bit 7 AG0 1 The 8-bit brightness code is shifted in from the SERIAL-IN terminal, with bit 7 first. Bits 1 to 7 of the code determine the voltage applied to the R-EXT terminal (VG). Bit 1, HC, divides the voltage range into 25% to 50% (HC = 0) or 50% to 100% (HC = 1), and bits 2 to 7 are used to adjust the voltage in 64 steps within the range selected by bit 1. After on power, total brightness adjustment code becomes the above-mentioned default value. 14 (Ver.0.0) 08-02-07 TENTATIVE Theoretical Current Settings (preliminary) Current = 1.13 V × VG ÷ R-EXT × 16 1.2 1 0.8 VG 0.6 0.4 0.2 0 [０,１１１１１１] [1,００００００] [1,００１１１１] [1,０１１１１１] [1,１０１１１１] [０,００００００] [０,００１１１１] [０,１０１１１１] [1,１１１１１１] TB62778FNG 0 16 32 48 64 80 96 11 12 28 Brightness code (HC, AG[0:5]) 全輝度調整コード（HC,AG[0：5]） Note) After setting up total luminance, it must be paid attention because the operation moves to the error detection mode (OOD) when five clocks are taken during the setting current output ( ENABLE = L period). (Please see the error detection mode on page 15.) Error Detection Mode 1 (OOD Detection) 3.5 µs min 1 CLOCK ENABLE SOUT Bit 7 Input source of the shift register SERIAL-IN Error detection H L L L L L L H H H H H H 2 3 4 5 6 [０,０１１１１１] Error status code Bit Bit Bit Bit Bit 65432 SERIAL-IN In special mode, the TB62778FNG not only enables the outputs but also performs error detection, and if any error is detected, loads an error status code into the shift register. For ODD detection, five Low bits must be shifted in. Immediately following the fifth Low bit, the input source of the shift register switches from the SERIAL-IN terminal to the 8-bit parallel error status code register. An error status code is generated at least 3.5µs from the fifth rising edge of CLOCK after ENABLE is set Low. If any Low bit occurs thereafter, the detected error status code is saved in the shift register. Therefore, while ENABLE is Low, serial data can not be shifted into the TB62778FNG via the SERIAL-IN terminal. Setting ENABLE high changes the input source of the shift register to the SERIAL-IN terminal, disables the outputs and terminates error detection. Thereupon, new serial data is shifted into the TB62778FNG via the SERIAL-IN terminal while the error code in the shift register is shifted out from the SERIAL-OUT terminal on the falling edge of CLOCK. The output is Hi-Z when the output is turning off before OOD detection. So please execute the OOD detection after the output is turning on. Error Status Code in OOD Detection Mode Error Status Code VOOD ≥ VO VOOD < VO 0 1 Output Terminal State Open Normal 15 (Ver.0.0) 08-02-07 TENTATIVE Error Detection Mode 2 (OSD Detection) 3.5 µs min 1 CLOCK ENABLE SOUT Bit 7 Input source of the shift register SERIAL-IN Error detection H L L H L L L H H H H H H 2 3 4 5 6 TB62778FNG Error status code Bit Bit Bit Bit Bit 65432 SERIAL-IN In special mode, the TB62778FNG not only enables the outputs but also performs error detection, and if any error is detected, loads an error status code into the shift register. For OSD detection, an L-L-H-L-L sequence must be shifted in. Immediately following the fifth Low bit, the input source of the shift register switches from the SERIAL-IN terminal to the 8-bit parallel error status code register. An error status code is generated at least 3.5 µs from the fifth rising edge of CLOCK after ENABLE is set Low. If any Low bit occurs thereafter, the detected error status code is saved in the shift register. Therefore, while ENABLE is Low, serial data can not be shifted into the TB62778FNG via the SERIAL-IN terminal. Setting ENABLE high changes the input source of the shift register to the SERIAL-IN terminal, disables the outputs and terminates error detection. Thereupon, new serial data is shifted into the TB62778FNG via the SERIAL-IN terminal while the error code in the shift register is shifted out from the SERIAL-OUT terminal on the falling edge of CLOCK. TB62777FNG is over the power dissipation when OSD detection. So please execute the OSD detection after the output is turning off. Error Status Code in OSD Detection Mode Error Status Code VOOD ≤ VO VOOD > VO 0 1 Output Terminal State Shorted Normal Note) The output current at the error detection mode is 25% of a set current (total brightness adjustment code（LSB） : minimum current setting). Sequence for Switching to Normal Mode 1 CLOCK ENABLE H L L L H L H L H L Low level 2 3 4 5 LATCH Only in the case of this signal sequence, it changes to the normal mode. Data is reset(0) when the mode is changes from the specified mode to the normal mode. POR Characteristic VDD 2.8Ｖ or less 0.5Ｖ or less POR Release 16 (Ver.0.0) 08-02-07 TENTATIVE Output current vs. Dirating (lighting rate) graph PCB Conditions: 76.2 × 114.3 × 1.6 mm, Cu = 30%, 35-µm Thick, SEMI-Compliant IOUT − Duty ON PCB 100 90 80 70 IOUT (mA) TB62778FNG Pd-Ta 1.4 1.2 1.0 Pd(W) 60 50 40 30 20 10 0 0 20 40 60 80 100 Duty − Turn-ON rate (%) ON PCB All outputs ON Ta = 85°C VDD = 5.0 V VOUT = 1.0 V 0.8 0.6 0.4 0.2 0.0 0 50 Ta (°C) 100 150 Output Current vs. External Resistor (typ.) 50 45 40 35 IOUT (mA) IOUT − REXT IOUT - REXT IOUT (mA) 30 25 20 15 10 5 0 100 1000 REXT (Ω ) 10000 All outputs ON Ta = 25°C VOUT = 0.7 V The above graphs are presented merely as a guide and does not constitute any guarantee as to the performance or characteristics of the device. Each product design should be fully evaluated in the real-world environment. 17 (Ver.0.0) 08-02-07 TENTATIVE Application Circuit: General Composition for Dynamic Lighting of LEDs In the following diagram, it is recommended that the LED supply voltage (VLED) be equal to or greater than the sum of Vf (max) of all LEDs plus 0.7 V. TB62778FNG VLED O0 SERIAL-IN C.U. ENABLE LATCH CLOCK O1 O2 O5 O6 O7 SERIAL-OUT SERIAL-IN ENABLE LATCH CLOCK O0 O1 O2 O5 O6 O7 SERIAL-OUT TB62778FNG R-EXT GND TB62778FNG R-EXT GND 18 (Ver.0.0) 08-02-07 TENTATIVE Application Circuit: General Composition for Dynamic Lighting of LEDs In the following diagram, it is recommended that the LED supply voltage (VLED) be equal to or greater than the sum of Vf (max) of all LEDs plus 0.7 V. TB62778FNG Example) TD62M8600FG 8 bit multichip PNP transistor array. It is not necessary when lighting statically. VLED O0 SERIAL-IN C.U. ENABLE LATCH CLOCK O1 O6 O7 SERIAL-OUT SERIAL-IN ENABLE LATCH CLOCK SERIAL-OUT TB62778FNG R-EXT GND TB62778FNG R-EXT GND 19 (Ver.0.0) 08-02-07 TENTATIVE Package Dimensions TB62778FNG Weight: 0.07 g (typ.) 20 (Ver.0.0) 08-02-07 TENTATIVE Notes on Contents 1. Block Diagrams TB62778FNG Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. Equivalent Circuits The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. Timing Charts Timing charts may be simplified for explanatory purposes. 4. Application Circuits The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required, especially at the mass production design stage. Toshiba does not grant any license to any industrial property rights by providing these examples of application circuits. 5. Test Circuits Components in the test circuits are used only to obtain and confirm the device characteristics. These components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment. IC Usage Considerations Notes on handling of ICs (1) The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or IC failure. The IC will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. To minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power ON or the negative current resulting from the back electromotive force at power OFF. IC breakdown may cause injury, smoke or ignition. Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable, the protection function may not operate, causing IC breakdown. IC breakdown may cause injury, smoke or ignition. Do not insert devices in the wrong orientation or incorrectly. Make sure that the positive and negative terminals of power supplies are connected properly. Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. In addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time. (2) (3) (4) 21 (Ver.0.0) 08-02-07 TENTATIVE (5) TB62778FNG Carefully select external components (such as inputs and negative feedback capacitors) and load components (such as speakers), for example, power amp and regulator. If there is a large amount of leakage current such as input or negative feedback condenser, the IC output DC voltage will increase. If this output voltage is connected to a speaker with low input withstand voltage, overcurrent or IC failure can cause smoke or ignition. (The over current can cause smoke or ignition from the IC itself.) In particular, please pay attention when using a Bridge Tied Load (BTL) connection type IC that inputs output DC voltage to a speaker directly. Points to remember on handling of ICs (1) Over current Protection Circuit Over current protection circuits (referred to as current limiter circuits) do not necessarily protect ICs under all circumstances. If the Over current protection circuits operate against the over current, clear the over current status immediately. Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the over current protection circuit to not operate properly or IC breakdown before operation. In addition, depending on the method of use and usage conditions, if over current continues to flow for a long time after operation, the IC may generate heat resulting in breakdown. Back-EMF When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the motor’s power supply due to the effect of back-EMF. If the current sink capability of the power supply is small, the device’s motor power supply and output pins might be exposed to conditions beyond maximum ratings. To avoid this problem, take the effect of back-EMF into consideration in system design. (2) 22 (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG About solderability, following conditions were confirmed • Solderability (1) Use of Sn-37Pb solder Bath · solder bath temperature = 230°C · dipping time = 5 seconds · the number of times = once · use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath · solder bath temperature = 245°C · dipping time = 5 seconds · the number of times = once · use of R-type flux RESTRICTIONS ON PRODUCT USE • The information contained herein is subject to change without notice. 021023_D 070122EBA • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 021023_B • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C • The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E 23 (Ver.0.0) 08-02-07