Marvell® Alaska®
88E2010/88E2040L
Single and Quad 10/100/1000/2.5G/5GBASE-T Ethernet Transceiver
Datasheet - Public
Doc. No. MV-S111597-U0 Rev. D
Copyright © 2020 Marvell
Document Classification: Public
Cover
Marvell 88E2010/88E2040L
Datasheet - Public
THIS DOCUMENT AND THE INFORMATION FURNISHED IN THIS DOCUMENT ARE PROVIDED “AS IS” WITHOUT ANY WARRANTY. MARVELL
AND ITS AFFILIATES EXPRESSLY DISCLAIM AND MAKE NO WARRANTIES OR GUARANTEES, WHETHER EXPRESS, ORAL, IMPLIED,
STATUTORY, ARISING BY OPERATION OF LAW, OR AS A RESULT OF USAGE OF TRADE, COURSE OF DEALING, OR COURSE OF
PERFORMANCE, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NON-INFRINGEMENT.
This document, including any software or firmware referenced in this document, is owned by Marvell or Marvell's licensors, and is protected by
intellectual property laws. No license, express or implied, to any Marvell intellectual property rights is granted by this document. The information
furnished in this document is provided for reference purposes only for use with Marvell products. It is the user's own responsibility to design or build
products with this information. Marvell products are not authorized for use as critical components in medical devices, military systems, life or critical
support devices, or related systems. Marvell is not liable, in whole or in part, and the user will indemnify and hold Marvell harmless for any claim,
damage, or other liability related to any such use of Marvell products.
Marvell assumes no responsibility for the consequences of use of such information or for any infringement of patents or other rights of third parties that
may result from its use. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning
the Marvell products disclosed herein. Marvell and the Marvell logo are registered trademarks of Marvell or its affiliates. Please visit www.marvell.com
for a complete list of Marvell trademarks and guidelines for use of such trademarks. Other names and brands may be claimed as the property of
others.
Copyright
Copyright © 2020. Marvell and/or its affiliates. All rights reserved.
Document Classification: Public
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Page 2
Copyright © 2020 Marvell
Alaska M 88E2010/88E2040L
Single and Quad 10/100/1000/2.5G/5GBASE-T Ethernet
Transceiver
Datasheet - Public
PRODUCT OVERVIEW
The Marvell® Alaska® M 88E2010/88E2040L is a family of fully
IEEE 802.3bz-compliant 1-port (88E2010) or 4-port (88E2040L)
physical layer (PHY) devices. The devices support a wide
variety of host-side interfaces including 5GBASE-R,
2500BASE-X, and SGMII to support full backward-compatibility
with lower speed legacy Ethernet rates including: 1 Gbps,
100 Mbps, and 10 Mbps.
The flexibility of this device family enables extremely low power
across all structured wiring cable lengths, enabling dense
5 Gbps applications. The device supports Category 6-type
(screened or unscreened), Category 6A-type (Augmented),
Category 7-type cables, and Category 5e-type cables for
distances up to 100 meters.
Features
•
•
•
•
•
•
•
•
•
1- or 4-port, five-speed PHY. Operates at 10M, 100M, 1G,
2.5G, or 5G data rates on UTP copper lines.
Compliant with IEEE 802.3bz specifications for 2.5G and
5G modes
5GBASE-R, 2500BASE-X, and SGMII system-side
interfaces on all devices
Allows dense multi-port 2.5G/5G applications
BER better than 1E-15
100m reach on CAT 5e for 2.5G and 5G modes
Clause 45 MDC/MDIO management interface
Small 10 mm × 12 mm HFCBGA package for 88E2010
single-port applications;
23 mm × 23 mm HFCBGA package for 88E2040L
quad-port applications
Available in commercial and industrial grades
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 3
Alaska M 88E2010/88E2040L
Datasheet - Public
Figure 1: 88E2010 Top-level Block Diagram
Doc. No. MV-S111597-U0 Rev. D
Page 4
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Product Overview
Features
Figure 2: 88E2040L Top-level Block Diagram
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 5
Alaska M 88E2010/88E2040L
Datasheet - Public
Table of Contents
1
General Chip Description.................................................................................................................13
2
Signal Description ............................................................................................................................17
2.1
Pin Maps .............................................................................................................................................................. 18
2.1.1
88E2010 Device Pin Map ...................................................................................................................... 18
2.1.2
88E2040L Device Pin Map .................................................................................................................... 19
2.2
Pin Description ..................................................................................................................................................... 21
2.3
Pin Assignment Lists............................................................................................................................................ 39
2.3.1
88E2010 Device Pin Assignment List.................................................................................................... 39
2.3.2
88E2040L Device Pin Assignment List.................................................................................................. 45
3
Functional Description.....................................................................................................................62
3.1
Buffering............................................................................................................................................................... 62
3.1.1
EEE Buffering ........................................................................................................................................ 62
3.2
Link Interrupt ........................................................................................................................................................ 62
3.3
Loopback ............................................................................................................................................................. 63
3.3.1
MAC Loopback ...................................................................................................................................... 64
3.3.2
Line Loopback ....................................................................................................................................... 65
3.4
Configuration and Resets..................................................................................................................................... 65
3.4.1
Hardware and Software Resets............................................................................................................. 65
3.4.2
Hardware Configuration......................................................................................................................... 65
3.4.3
Reference Clock Selection .................................................................................................................... 70
3.5
MDC/MDIO Register Access................................................................................................................................ 71
3.5.1
Clause 45 MDIO Framing ...................................................................................................................... 72
3.5.2
30 MHz High-Speed MDC/MDIO Management Interface Protocol........................................................ 72
3.5.3
Independent MDC/MDIO Support.......................................................................................................... 72
3.6
Firmware Loading ................................................................................................................................................ 73
3.6.1
Flash Memory Interface ......................................................................................................................... 73
3.6.2
Firmware Download to RAM.................................................................................................................. 73
3.7
Power Management ............................................................................................................................................. 73
3.7.1
Manual Power Down.............................................................................................................................. 73
3.7.2
MAC Interface Power Down .................................................................................................................. 74
3.7.3
Controlling and Sensing......................................................................................................................... 74
3.8
LED ...................................................................................................................................................................... 74
3.8.1
LED Polarity........................................................................................................................................... 74
3.8.2
Pulse Stretching and Blinking ................................................................................................................ 75
3.8.3
Bi-Color LED Mixing .............................................................................................................................. 75
3.8.4
Modes of Operation ............................................................................................................................... 76
3.8.5
Speed Blink............................................................................................................................................ 77
3.8.6
Combo LED Modes ............................................................................................................................... 78
3.9
Interrupt................................................................................................................................................................ 81
3.10 IEEE 1149.1 and 1149.6 Controller ..................................................................................................................... 82
3.10.1 BYPASS Instruction............................................................................................................................... 82
3.10.2 SAMPLE/PRELOAD Instruction ............................................................................................................ 83
3.10.3 EXTEST Instruction ............................................................................................................................... 93
3.10.4 CLAMP Instruction................................................................................................................................. 93
3.10.5 HIGH-Z Instruction................................................................................................................................. 93
Doc. No. MV-S111597-U0 Rev. D
Page 6
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Table of Contents
3.10.6
3.10.7
3.10.8
3.10.9
ID CODE Instruction .............................................................................................................................. 93
EXTEST_PULSE Instruction ................................................................................................................. 93
PROG_HYST Instruction ....................................................................................................................... 94
AC-JTAG Fault Detection ...................................................................................................................... 94
3.11 Reference Clock................................................................................................................................................... 98
3.12 Power Supplies .................................................................................................................................................... 99
3.12.1 AVDDL................................................................................................................................................... 99
3.12.2 AVDDH .................................................................................................................................................. 99
3.12.3 AVDDT................................................................................................................................................... 99
3.12.4 AVDDC .................................................................................................................................................. 99
3.12.5 AVDDS .................................................................................................................................................. 99
3.12.6 AVDDR .................................................................................................................................................. 99
3.12.7 DVDD..................................................................................................................................................... 99
3.12.8 VDDO .................................................................................................................................................... 99
3.12.9 VHV ..................................................................................................................................................... 100
3.12.10 VDD09 ................................................................................................................................................. 100
4
Copper Unit (T Unit)........................................................................................................................101
4.1
Media Interface .................................................................................................................................................. 101
4.1.1
2.5GBASE-T and 5GBASE-T .............................................................................................................. 101
4.1.2
1000BASE-T........................................................................................................................................ 102
4.1.3
100BASE-TX ....................................................................................................................................... 102
4.1.4
10BASE-T............................................................................................................................................ 103
4.1.5
Taking Down the Link .......................................................................................................................... 103
4.2
Loopback ........................................................................................................................................................... 103
4.2.1
MAC Loopback .................................................................................................................................... 104
4.2.2
Line Loopback ..................................................................................................................................... 104
4.3
Power Management ........................................................................................................................................... 105
4.3.1
Manual Power Down............................................................................................................................ 105
4.3.2
Energy Detect ...................................................................................................................................... 105
4.4
Auto-Negotiation ............................................................................................................................................... 107
4.4.1
802.3 Clause 28, 40, and 55 Auto-Negotiation.................................................................................... 107
4.4.2
Exchange Complete — No Link Indicator............................................................................................ 108
4.5
Auto Downshift ................................................................................................................................................... 108
4.6
Auto MDI/MDIX Crossover................................................................................................................................. 109
4.7
Auto Polarity Correction ..................................................................................................................................... 110
5
Host Interface Unit (H Unit) ............................................................................................................111
5.1
Host Electrical Interface ..................................................................................................................................... 111
5.2
PCS.................................................................................................................................................................... 112
5.2.1
5GBASE-R/2500BASE-X .................................................................................................................... 112
5.2.2
5GBASE-R........................................................................................................................................... 112
5.2.3
2500BASE-X........................................................................................................................................ 113
5.2.4
SGMII (Media) ..................................................................................................................................... 113
5.3
Loopback ........................................................................................................................................................... 115
5.4
Power Management ........................................................................................................................................... 116
6
Electrical Specifications ................................................................................................................117
6.1
Absolute Maximum Ratings ............................................................................................................................... 117
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 7
Alaska M 88E2010/88E2040L
Datasheet - Public
6.2
Recommended Operating Conditions ................................................................................................................ 118
6.3
Package Thermal Information ............................................................................................................................ 119
6.3.1
Thermal Conditions for 88E2010, 168-pin, HFCBGA Package ........................................................... 119
6.3.2
Thermal Conditions for 88E2040L, 484-pin, HFCBGA Package ......................................................... 120
6.4
Digital I/O Electrical Specifications..................................................................................................................... 121
6.4.1
DC Operating Conditions..................................................................................................................... 121
6.4.2
Reset Timing........................................................................................................................................ 122
6.4.3
LED to CONFIG Timing ....................................................................................................................... 122
6.4.4
MDC/MDIO Management Interface Timing ......................................................................................... 123
6.4.5
JTAG Timing........................................................................................................................................ 125
6.4.6
SPI Interface Timing ............................................................................................................................ 126
6.5
Analog Electrical Specifications ......................................................................................................................... 127
6.5.1
SGMII Electrical Summary................................................................................................................... 127
6.5.2
2500BASE-X Electrical Summary........................................................................................................ 128
6.5.3
5GBASE-R Electrical Summary........................................................................................................... 129
6.5.4
10BASE-Te, 100BASE-TX, and 1000BASE-T Electrical Parameters ................................................. 130
6.5.5
IEEE DC Transceiver Parameters ....................................................................................................... 131
6.6
Reference Clock................................................................................................................................................. 132
6.6.1
CLKP/N Timing — 156.25 MHz ........................................................................................................... 132
6.6.2
CLKP/N Timing — 50 MHz .................................................................................................................. 133
6.6.3
XTAL Timing Data ............................................................................................................................... 134
6.7
Latency .............................................................................................................................................................. 135
7
Mechanical Drawing .......................................................................................................................137
7.1
168-pin 10 mm x 12 mm HFCBGA Package Mechanical Drawings .................................................................. 137
7.2
484-pin 23 mm x 23 mm HFCBGA Package Mechanical Drawings .................................................................. 140
8
Part Order Numbering/Package Marking......................................................................................143
8.1
Part Order Numbering........................................................................................................................................ 143
8.2
Package Marking ............................................................................................................................................... 145
8.2.1
Commercial Marking Examples ........................................................................................................... 145
8.2.2
Industrial Marking Examples................................................................................................................ 147
Doc. No. MV-S111597-U0 Rev. D
Page 8
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
List of Tables
List of Tables
Product Overview .......................................................................................................................................3
1
General Chip Description.................................................................................................................13
2
Signal Description ............................................................................................................................17
3
Table 1:
Pin Type Definitions ......................................................................................................................... 17
Table 2:
Media Dependent Interface.............................................................................................................. 21
Table 3:
SERDES Interface ........................................................................................................................... 23
Table 4:
Clock/Reset/Reference .................................................................................................................... 25
Table 5:
Management Interface ..................................................................................................................... 26
Table 6:
SPI Interface .................................................................................................................................... 27
Table 7:
LED .................................................................................................................................................. 28
Table 8:
Configuration.................................................................................................................................... 29
Table 9:
JTAG Interface................................................................................................................................. 29
Table 10:
Test Pins .......................................................................................................................................... 30
Table 11:
Power and Ground........................................................................................................................... 32
Table 12:
Power and Ground (Continued) ....................................................................................................... 33
Table 13:
88E2010 Pin List — Alphabetical by Signal Name .......................................................................... 39
Table 14:
88E2040L Pin List — Alphabetical by Signal Name ........................................................................ 45
Functional Description.....................................................................................................................62
Table 15:
Loopback Control............................................................................................................................. 63
Table 16:
88E2010 Device Configuration Mapping ......................................................................................... 66
Table 17:
88E2010 Three Bit Mapping ............................................................................................................ 66
Table 18:
88E2040L Device Configuration Mapping ....................................................................................... 66
Table 19:
88E2040L Device Three Bit Mapping .............................................................................................. 67
Table 20:
Configuration Bit Definition .............................................................................................................. 67
Table 21:
CLK_SEL[1:0] Selection .................................................................................................................. 70
Table 22:
Extensions for Management Frame Format for Indirect Access...................................................... 72
Table 23:
88E2040L Device MDC/MDIO Interface Mapping ........................................................................... 72
Table 24:
Dual LED Mode Behavior ................................................................................................................ 76
Table 25:
Basic LED Status ............................................................................................................................. 76
Table 26:
Compound LED Status .................................................................................................................... 76
Table 27:
Speed Blinking Sequence................................................................................................................ 77
Table 28:
Combo LED Modes.......................................................................................................................... 78
Table 29:
Combo Mode Timer Control............................................................................................................. 79
Table 30:
Combo LED Flash Mode.................................................................................................................. 80
Table 31:
TAP Controller Opcodes .................................................................................................................. 82
Table 32:
88E2010 Boundary Scan Chain Order ............................................................................................ 84
Table 33:
88E2010 Boundary Scan Exclusion List .......................................................................................... 86
Table 34:
88E2040L Boundary Scan Chain Order .......................................................................................... 87
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 9
Alaska M 88E2010/88E2040L
Datasheet - Public
4
Table 35:
88E2040L Boundary Scan Exclusion List ........................................................................................ 90
Table 36:
ID CODE Instruction ........................................................................................................................ 93
Table 37:
Test Receiver Hysteresis Setting..................................................................................................... 94
Table 38:
AC-Coupled Connection Fault Signature......................................................................................... 95
Table 39:
DC-Coupled Connection Fault Signature......................................................................................... 96
Table 40:
Reference Clock Options ................................................................................................................. 98
Table 41:
Signal Power Segment .................................................................................................................. 100
Copper Unit (T Unit)........................................................................................................................101
Table 42:
5
6
7
8
Media Dependent Interface Pin Mapping....................................................................................... 109
Host Interface Unit (H Unit) ............................................................................................................111
Table 43:
88E2010 Host Interface Configuration........................................................................................... 112
Table 44:
88E2040L Host Interface Configuration......................................................................................... 112
Electrical Specifications ................................................................................................................117
Table 45:
Absolute Maximum Rating ............................................................................................................ 117
Table 46:
Recommended Operating Conditions............................................................................................ 118
Table 47:
Thermal Conditions for 88E2010, 168-pin, HFCBGA Package ..................................................... 119
Table 48:
Thermal Conditions for 88E2040L, 484-pin, HFCBGA Package ................................................... 120
Table 49:
DC Operating Conditions ............................................................................................................... 121
Table 50:
Reset Timing.................................................................................................................................. 122
Table 51:
LED to CONFIG Timing ................................................................................................................. 122
Table 52:
MDC/MDIO Management Interface Timing.................................................................................... 123
Table 53:
JTAG Timing .................................................................................................................................. 125
Table 54:
SPI Interface Timing ..................................................................................................................... 126
Table 55:
SGMII Electrical Summary............................................................................................................. 127
Table 56:
2500BASE-X Electrical Summary.................................................................................................. 128
Table 57:
5GBASE-R Electrical Summary..................................................................................................... 129
Table 58:
IEEE DC Transceiver Parameters ................................................................................................. 130
Table 59:
IEEE DC Transceiver Parameters ................................................................................................. 131
Table 60:
CLKP/N Timing — 156.25 MHz ..................................................................................................... 132
Table 61:
CLKP/N Timing — 50 MHz ............................................................................................................ 133
Table 62:
XTAL Timing ................................................................................................................................. 134
Table 63:
Egress Path Latency
Data .......................................................................................................... 135
Table 64:
Ingress Path Latency
Data.......................................................................................................... 136
Mechanical Drawing .......................................................................................................................137
Table 65:
168-pin 10 mm x 12 mm HFCBGA Package Dimensions ............................................................. 139
Table 66:
484-pin 23 mm x 23 mm HFCBGA Package Dimensions ............................................................. 142
Part Order Numbering/Package Marking......................................................................................143
Table 67:
88E2010/88E2040L Commercial Part Order Options.................................................................... 143
Table 68:
88E2010/88E2040L Industrial Part Order Options ........................................................................ 144
Table 69:
Document Change History............................................................................................................. 149
Doc. No. MV-S111597-U0 Rev. D
Page 10
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
List of Figures
List of Figures
Product Overview .......................................................................................................................................3
1
Figure 1:
88E2010 Top-level Block Diagram .................................................................................................... 4
Figure 2:
88E2040L Top-level Block Diagram .................................................................................................. 5
General Chip Description................................................................................................................ 13
Figure 3:
88E2010 Device Functional Block Diagram..................................................................................... 14
Figure 4:
88E2040L Device Functional Block Diagram................................................................................... 15
2
Signal Description ........................................................................................................................... 17
3
Functional Description.................................................................................................................... 62
4
5
6
Figure 5:
Loopback Paths ............................................................................................................................... 64
Figure 6:
Typical MDC/MDIO Read Operation................................................................................................ 71
Figure 7:
Typical MDC/MDIO Write Operation................................................................................................ 71
Figure 8:
30 MHz MDC/MDIO Read Operation............................................................................................... 72
Figure 9:
SPI Read Array ................................................................................................................................ 73
Figure 10:
LED Chain........................................................................................................................................ 74
Figure 11:
Various LED Hookup Configurations ............................................................................................... 75
Figure 12:
AC-Coupled Connection .................................................................................................................. 95
Figure 13:
DC-Coupled Connection .................................................................................................................. 96
Copper Unit (T Unit)....................................................................................................................... 101
Figure 14:
2.5GBASE-T and 5GBASE-T Data Path ....................................................................................... 101
Figure 15:
1000BASE-T Data Path ................................................................................................................. 102
Figure 16:
100BASE-TX Data Path................................................................................................................. 102
Figure 17:
10BASE-T Data Path ..................................................................................................................... 103
Figure 18:
MAC Interface Loopback Diagram — Copper Media Interface...................................................... 104
Figure 19:
Line Loopback Diagram — Copper Media Interface...................................................................... 105
Host Interface Unit (H Unit) ........................................................................................................... 111
Figure 20:
Shallow Host Loopback ................................................................................................................. 115
Figure 21:
Deep Line Loopback, No Ingress Blocking .................................................................................... 115
Figure 22:
Deep Line Loopback, Ingress Blocking.......................................................................................... 115
Electrical Specifications ............................................................................................................... 117
Figure 23:
Reset Timing.................................................................................................................................. 122
Figure 24:
LED to CONFIG Timing ................................................................................................................. 122
Figure 25:
MDC/MDIO Management Interface Timing.................................................................................... 123
Figure 26:
MDC/MDIO Input Hysteresis.......................................................................................................... 123
Figure 27:
MDC Read Turnaround Delay ....................................................................................................... 124
Figure 28:
JTAG Timing .................................................................................................................................. 125
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 11
Alaska M 88E2010/88E2040L
Datasheet - Public
7
8
Figure 29:
SPI Interface Timing ...................................................................................................................... 126
Figure 30:
XTAL Timing .................................................................................................................................. 134
Mechanical Drawing ...................................................................................................................... 137
Figure 31:
168-pin 10 mm x 12 mm HFCBGA Top and Side View ................................................................. 137
Figure 32:
168-pin 10 mm x 12 mm HFCBGA Bottom View ........................................................................... 138
Figure 33:
484-pin 23 mm x 23 mm HFCBGA Top and Side View ................................................................. 140
Figure 34:
484-pin 23 mm x 23 mm HFCBGA Bottom View ........................................................................... 141
Part Order Numbering/Package Marking..................................................................................... 143
Figure 35:
Sample Part Number ..................................................................................................................... 143
Figure 36:
88E2010 Commercial Package Marking and Pin 1 Location......................................................... 145
Figure 37:
88E2040L Commercial Package Marking and Pin 1 Location....................................................... 146
Figure 38:
88E2010 Industrial Package Marking and Pin 1 Location ............................................................. 147
Figure 39:
88E2040L Industrial Package Marking and Pin 1 Location ........................................................... 148
Doc. No. MV-S111597-U0 Rev. D
Page 12
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
General Chip Description
1
General Chip Description
The 88E2010 and 88E2040L devices are a family of one- and four-port integrated multi-speed copper Ethernet
Transceivers.
The host interface to the MAC is via 5GBASE-R, 2500BASE-X, or SGMII interface.
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 13
Alaska M 88E2010/88E2040L
Datasheet - Public
Figure 3: 88E2010 Device Functional Block Diagram
Doc. No. MV-S111597-U0 Rev. D
Page 14
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
General Chip Description
Figure 4: 88E2040L Device Functional Block Diagram
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 15
Alaska M 88E2010/88E2040L
Datasheet - Public
The datasheet is divided as follows:
Section 1 describes the general function of the device.
Section 2 describes the pinout and pin definitions.
Section 3 describes the detailed device functions.
Section 4 describes the copper interface functions (T Unit).
Section 5 describes the MAC interface functions (H Unit).
Section 6 describes the electrical specifications.
Section 7 describes the package mechanical dimensions.
Section 8 describes the order information.
The conventions used in the datasheet are as follows.
All registers are specified per IEEE 802.3 section 45. The format is X.Y, X.Y.Z, or X.Y.Z1:Z2, where X is the
device address in decimal from 0 to 31, Y is the register address in hexadecimal from 0000 to FFFF, and Z is the
bit in decimal from 0 to 15.
T Unit – 10/100/1000/2.5G/5GBASE-T interface.
H Unit – SGMII/2500BASE-X/5GBASE-R host interface.
Unless otherwise noted, all descriptions apply to the one-, two-, and four-port devices.
Note
Doc. No. MV-S111597-U0 Rev. D
Page 16
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Signal Description
2
Table 1:
Signal Description
Pin Type Definitions
Pin Type
Definition
H
Input with hysteresis
I/O
Input and output
I
Input only
O
Output only
PU
Internal pull-up
PD
Internal pull-down
D
Open drain output
Z
Tri-state output
mA
DC sink capability
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 17
Alaska M 88E2010/88E2040L
Datasheet - Public
2.1
Pin Maps
2.1.1
88E2010 Device Pin Map
(Top View)
Doc. No. MV-S111597-U0 Rev. D
Page 18
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Signal Description
Pin Maps
2.1.2
88E2040L Device Pin Map
Due to the large number of pins, the package is depicted graphically over two pages.
(Top View)
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 19
Alaska M 88E2010/88E2040L
Datasheet - Public
(Top View)
Doc. No. MV-S111597-U0 Rev. D
Page 20
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Signal Description
Pin Description
2.2
Pin Description
88E2010 device pin names are not prefixed with P0_.
Note
Table 2:
Media Dependent Interface
8 8E2010 Pin
#
88E2040L
Pin #
Pin Name
Pin
Ty pe
D e s c ri p t i o n
P9
N9
AB2
AA2
P0_MDIP[0]
P0_MDIN[0]
I/O
Media Dependent Interface[0], Port 0.
In 2.5G/5GBASE-T and 1000BASE-T modes in MDI
configuration, MDIP/N[0] correspond to BI_DA±.
In MDIX configuration, MDIP/N[0] correspond to BI_
DB±.
In 100BASE-TX and 10BASE-T modes in MDI
configuration, MDIP/N[0] are used for the transmit pair.
In MDIX configuration, MDIP/N[0] are used for the
receive pair.
MDIP/N[0] should be tied to ground if not used.
The device contains an internal 100Ω resistor between
the MDIP/N[0] pins.
N8
P8
AB3
AA3
P0_MDIP[1]
P0_MDIN[1]
I/O
Media Dependent Interface[1], Port 0.
In 2.5G/5GGBASE-T and 1000BASE-T modes in MDIX
configuration, MDIP/N[1] correspond to BI_DA±.
In MDI configuration, MDIP/N[1] correspond to BI_DB±.
In 100BASE-TX and 10BASE-T modes in MDIX
configuration, MDIP/N[1] are used for the transmit pair.
In MDI configuration, MDIP/N[1] are used for the
receive pair.
MDIP/N[1] should be tied to ground if not used.
The device contains an internal 100Ω resistor between
the MDIP/N[1] pins.
P5
N5
AB4
AA4
P0_MDIP[2]
P0_MDIN[2]
I/O
Media Dependent Interface[2], Port 0.
In 2.5G/5GGBASE-T and 1000BASE-T modes in MDI
configuration, MDIP/N[2] correspond to BI_DC±.
In MDIX configuration, MDIP/N[2] correspond to BI_
DD±.
In 100BASE-TX and 10BASE-T modes, these pins are
floating.
MDIP/N[2] should be tied to ground if not used.
The device contains an internal 100Ω resistor between
the MDIP/N[2] pins.
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 21
Alaska M 88E2010/88E2040L
Datasheet - Public
Table 2:
Media Dependent Interface (Continued)
8 8E2010 Pin
#
88E2040L
Pin #
Pin Name
Pin
Ty pe
D e s c ri p t i o n
N4
P4
AB5
AA5
P0_MDIP[3]
P0_MDIN[3]
I/O
Media Dependent Interface[3], Port 0.
In 2.5G/5GBASE-T and 1000BASE-T modes in MDIX
configuration, MDIP/N[3] correspond to BI_DC±.
In MDI configuration, MDIP/N[3] correspond to BI_
DD±.
In 100BASE-TX and 10BASE-T modes these pins are
floating.
MDIP/N[3] should be tied to ground if not used.
The device contains an internal 100Ω resistor between
the MDIP/N[3] pins.
---
AB10
AA10
P1_MDIP[0]
P1_MDIN[0]
I/O
Media Dependent Interface[0], Port 1.
---
AB9
AA9
P1_MDIP[1]
P1_MDIN[1]
I/O
Media Dependent Interface[1], Port 1.
---
AB8
AA8
P1_MDIP[2]
P1_MDIN[2]
I/O
Media Dependent Interface[2], Port 1.
---
AB7
AA7
P1_MDIP[3]
P1_MDIN[3]
I/O
Media Dependent Interface[3], Port 1.
---
AB12
AA12
P2_MDIP[0]
P2_MDIN[0]
I/O
Media Dependent Interface[0], Port 2.
---
AB13
AA13
P2_MDIP[1]
P2_MDIN[1]
I/O
Media Dependent Interface[1], Port 2.
---
AB14
AA14
P2_MDIP[2]
P2_MDIN[2]
I/O
Media Dependent Interface[2], Port 2.
---
AB15
AA15
P2_MDIP[3]
P2_MDIN[3]
I/O
Media Dependent Interface[3], Port 2.
---
AB20
AA20
P3_MDIP[0]
P3_MDIN[0]
I/O
Media Dependent Interface[0], Port 3.
---
AB19
AA19
P3_MDIP[1]
P3_MDIN[1]
I/O
Media Dependent Interface[1], Port 3.
---
AB18
AA18
P3_MDIP[2]
P3_MDIN[2]
I/O
Media Dependent Interface[2], Port 3.
---
AB17
AA17
P3_MDIP[3]
P3_MDIN[3]
I/O
Media Dependent Interface[3], Port 3.
P7
N7
Y4
Y3
P0_CMP
P0_CMN
I
Media Dependent Interface, optional common mode
sense, Port 0
---
Y8
Y9
P1_CMP
P1_CMN
I
Media Dependent Interface, optional common mode
sense, Port 1
---
Y14
Y13
P2_CMP
P2_CMN
I
Media Dependent Interface, optional common mode
sense, Port 2
---
Y18
Y19
P3_CMP
P3_CMN
I
Media Dependent Interface, optional common mode
sense, Port 3
Doc. No. MV-S111597-U0 Rev. D
Page 22
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Signal Description
Pin Description
Table 3:
SERDES Interface
8 8E2010
Pin #
88E2040L
Pin #
Pin Nam e
Pin
Ty pe
D e s c ri pt i on
C10
D10
C1
D1
P0_SIP[0]
P0_SIN[0]
I
Host Interface Input Lane 0, Port 0
5GBASE-R, 2500BASE-X, SGMII
C8
D8
C3
D3
P0_SIP[1]
P0_SIN[1]
I
Host Interface Input Lane 1 Port 0
C6
D6
C4
D4
-----
SIP[2]
SIN[2]
SIP[3]
SIN[3]
I
Host Interface Input Lane 2 and 3.
---
C9
D9
P1_SIP[0]
P1_SIN[0]
I
Host Interface Input Lane 0, Port 1
5GBASE-R, 2500BASE-X, SGMII
---
C7
D7
P1_SIP[1]
P1_SIN[1]
I
Host Interface Input Lane 1, Port 1
---
C14
D14
P2_SIP[0]
P2_SIN[0]
I
Host Interface Input Lane 0, Port 2
5GBASE-R, 2500BASE-X, SGMII,
---
C16
D16
P2_SIP[1]
P2_SIN[1]
I
Host Interface Input Lane 1, Port 2
---
C22
D22
P3_SIP[0]
P3_SIN[0]
I
Host Interface Input Lane 0, Port 3
5GBASE-R, 2500BASE-X, SGMII
---
C20
D20
P3_SIP[1]
P3_SIN[1]
I
Host Interface Input Lane 1, Port 3
A9
B9
A2
B2
P0_SOP[0]
P0_SON[0]
O
Host Interface Output Lane 0, Port 0
5GBASE-R, 2500BASE-X, SGMII
A7
B7
A4
B4
P0_SOP[1]
P0_SON[1]
O
Host Interface Output Lane 1 Port 0
A5
B5
A3
B3
-----
SOP[2]
SON[2]
SOP[3]
SON[3]
O
Host Interface Output Lane 2 and 3.
---
A8
B8
P1_SOP[0]
P1_SON[0]
O
Host Interface Output Lane 0, Port 1
5GBASE-R, 2500BASE-X, SGMII
---
A6
B6
P1_SOP[1]
P1_SON[1]
O
Host Interface Output Lane 1, Port 1
---
A15
B15
P2_SOP[0]
P2_SON[0]
O
Host Interface Output Lane 0, Port 2
5GBASE-R, 2500BASE-X, SGMII, lane 0
---
A17
B17
P2_SOP[1]
P2_SON[1]
O
Host Interface Output Lane 1, Port 2
These signals can be configured as lane 1 host
interface.
---
A21
B21
P3_SOP[0]
P3_SON[0]
O
Host Interface Output Lane 0, Port 3
5GBASE-R, 2500BASE-X, SGMII, lane 0
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 23
Alaska M 88E2010/88E2040L
Datasheet - Public
Table 3:
SERDES Interface (Continued)
8 8E2010
Pin #
88E2040L
Pin #
Pin Nam e
Pin
Ty pe
D e s c ri pt i on
---
A19
B19
P3_SOP[1]
P3_SON[1]
O
Host Interface Output Lane 1, Port 3
These signals can be configured as lane 1 host
interface.
Doc. No. MV-S111597-U0 Rev. D
Page 24
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Signal Description
Pin Description
Table 4:
Clock/Reset/Reference
8 8E2010 Pin
#
88E2040L
Pin #
Pin Name
Pi n
Ty pe
D e s c ri pt i on
N12
Y22
CIREF
I
Analog Reference, Copper. This pin should be
connected via a 4.99 kΩ 1% resistor to VSS.
B12
E21
SIREF
I
Analog Reference, SERDES. This pin should be
connected via a 4.99 kΩ 1% resistor to VSS
K1
J1
P1
N1
CLKP
CLKN
I
156.25 MHz or 50 MHz Differential Reference Clock
Input. ±50 ppm tolerance.
M1
T1
XTAL1
I
50 MHz crystal input
NOTE: 50 MHz crystal operation is only supported for
commercial-grade devices.
L1
R1
XTAL2
O
50 MHz crystal output
NOTE: 50 MHz crystal operation is only supported for
commercial-grade devices.
H12
K22
RCLK0
O
Recovered Clock Output 0 to 25 MHz
G11
J22
RCLK1
O
Recovered Clock Output 1 to 25 MHz
D12
G22
RESETn
I
Reset
0 = Reset
1 = Normal
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 25
Alaska M 88E2010/88E2040L
Datasheet - Public
Table 5:
Management Interface
8 8E2010
Pin #
88E2040L
Pin #
Pin Name
Pi n
Ty p e
D e s c ri pt i on
B1
----
B11
A11
A12
B12
MDC[0]
MDC[1]
MDC[2]
MDC[3]
I
Management Clock pin.
MDC is the management data clock reference for the
serial management interface. A continuous clock
stream is not expected. The maximum continuous
frequency supported is 12.5 MHz. A 30 MHz
non-continuous mode is also supported.
88E2040L:
If the device is configured to shared MDC/MDIO
mode, then MDC[2]/MDIO[2] is used to access all four
ports.
If the device is configured to dual MDC/MDIO mode,
then MDC[1]/MDIO[1] is used to access Ports 0 and 1
while MDC[2]/MDIO[2] is used to access Ports 2 and
3.
If MDC[x] is unused, then it should be tied low.
C1
----
C11
A10
A13
C12
MDIO[0]
MDIO[1]
MDIO[2]
MDIO[3]
I/O
Management Data pin.
MDIO is the management data. MDIO transfers
management data in and out of the device
synchronously to MDC.
This pin requires a pull-up resistor in a range from
1.5 kΩ to 10 kΩ
If MDIO[x] is unused, then it should be left floating.
C2
D11
INTn
OD
Interrupt pin. (Polarity programmable)
Doc. No. MV-S111597-U0 Rev. D
Page 26
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Signal Description
Pin Description
Table 6:
SPI Interface
8 8E2010
Pin #
88E2040L
Pin #
Pin Name
Pi n
Ty p e
D e s c ri pt i on
D11
G21
SPI_SSn
O
SPI device enable
F12
K20
SPI_CLK
O
SPI clock
E11
G20
SPI_MOSI
O
SPI serial out
E12
J20
SPI_MISO
I
SPI serial in
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 27
Alaska M 88E2010/88E2040L
Datasheet - Public
Table 7:
LED
8 8E2010
Pin #
88E2040L
Pin #
Pin Name
Pi n
Ty p e
D e s c ri pt i on
E1
F1
G1
F2
K1
K2
K3
K4
P0_LED[0]
P0_LED[1]
P0_LED[2]
P0_LED[3]
I/O
LED Outputs, Port 0
-----
J1
J3
H3
J4
P1_LED[0]
P1_LED[1]
P1_LED[2]
P1_LED[3]
I/O
LED Outputs, Port 1
-----
G1
G2
H2
G4
P2_LED[0]
P2_LED[1]
P2_LED[2]
P2_LED[3]
I/O
LED Outputs, Port 2
-----
F1
F2
F3
F4
P3_LED[0]
P3_LED[1]
P3_LED[2]
P3_LED[3]
I/O
LED Outputs, Port 3
F10
G10
H10
L22
L20
H22
Reserved
Reserved
Reserved
–
Reserved
K10
H11
G12
----
Reserved
Reserved
Reserved
–
Reserved
----
M22
M20
H20
Reserved
Reserved
Reserved
–
Reserved
----
N22
M21
J21
Reserved
Reserved
Reserved
–
Reserved
----
P22
N21
K21
Reserved
Reserved
Reserved
–
Reserved
Doc. No. MV-S111597-U0 Rev. D
Page 28
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Signal Description
Pin Description
Table 8:
Configuration
8 8E2010
Pin #
88E2040L
Pin #
Pin Name
Pi n
Ty p e
D e s c ri pt i on
K2
L2
M3
M4
CLK_SEL[0]
CLK_SEL[1]
I, PD
Reference clock selection
00 = 50 MHz XTAL1/2
01 = 50 MHz CLKP/N
10 = 156.25 MHz CLKP/N
11 = Reserved
NOTE: 50 MHz crystal operation is only supported for
commercial-grade devices.
H1
D1
D2
E2
G2
H2
D3
H3
L1
L2
M2
L4
H1
H4
J5
G5
CONFIG[0]
CONFIG[1]
CONFIG[2]
CONFIG[3]
CONFIG[4]
CONFIG[5]
CONFIG[6]
CONFIG[7]
I
Hardware Configuration
K3
L5
VSEL_L
I
VDDOL Voltage Level Select
VSS = 2.5V/3.3V, VDDOL = 1.5V/1.8V
F3
E12
VSEL_M
I
VDDOM Voltage Level Select
VSS = 2.5V/3.3V, VDDOM = 1.2V/1.5V/1.8V
E10
H19
VSEL_R
I
VDDOR Voltage Level Select
VSS = 2.5V/3.3V, VDDOR = 1.5V/1.8V
H9
L19
VSEL_T
I
VDDOT Voltage Level Select
VSS = 2.5V/3.3V, VDDOT = 1.5V/1.8V
Pin Name
Pi n
Ty p e
D e s c ri pt i on
Table 9:
JTAG Interface
8 8E2010
Pin #
88E2040L
Pin #
K11
T21
TDI
I, PU
JTAG Data Input
J12
U21
TDO
O
JTAG Data Output
J11
V21
TMS
I, PU
JTAG Mode Select
K12
R21
TCK
I, PU
JTAG Clock
L12
R22
TRSTn
I, PU
JTAG Reset. TRSTn pin requires a 4.7 kΩ pull-down
externally for normal operation.
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 29
Alaska M 88E2010/88E2040L
Datasheet - Public
Table 10: Test Pins
8 8E2010
Pin #
88E2040L
Pin #
Pin Name
Pi n
Ty p e
D e s c ri pt i on
M3
L3
-------
W2
V2
W3
V3
W4
V4
W5
V5
P0_ATP[0]
P0_ATN[0]
P0_ATP[1]
P0_ATN[1]
P0_ATP[2]
P0_ATN[2]
P0_ATP[3]
P0_ATN[3]
O
Analog Test Port 0
---------
W10
V10
W9
V9
W8
V8
W7
V7
P1_ATP[0]
P1_ATN[0]
P1_ATP[1]
P1_ATN[1]
P1_ATP[2]
P1_ATN[2]
P1_ATP[3]
P1_ATN[3]
O
Analog Test Port 1
---------
W12
V12
W13
V13
W14
V14
W15
V15
P2_ATP[0]
P2_ATN[0]
P2_ATP[1]
P2_ATN[1]
P2_ATP[2]
P2_ATN[2]
P2_ATP[3]
P2_ATN[3]
O
Analog Test Port 2
---------
W20
V20
W19
V19
W18
V18
W17
V17
P3_ATP[0]
P3_ATN[0]
P3_ATP[1]
P3_ATN[1]
P3_ATP[2]
P3_ATN[2]
P3_ATP[3]
P3_ATN[3]
O
Analog Test Port 3
P11
N11
AB21
AA21
CHSDACP
CHSDACN
O
Copper AC Test
A11
B11
F19
F20
SHSDACP
SHSDACN
O
SERDES AC Test
M12
W22
CTSTPT
O
Copper DC Test
C12
F22
STSTPT
O
SERDES DC Test
L11
M11
U22
T22
TEST_CLKP
TEST_CLKN
I
Test clock input
Doc. No. MV-S111597-U0 Rev. D
Page 30
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Signal Description
Pin Description
Table 10: Test Pins (Continued)
8 8E2010
Pin #
88E2040L
Pin #
Pin Name
Pi n
Ty p e
D e s c ri pt i on
P2
N2
W1
V1
TSTCP
TSTCN
O
Test clock output
When using the 50 MHz XTAL option, the
(CLK_SEL[1:0] = 00), TSTCP/N output pins
must be AC coupled with a 0.1 F capacitor
and connected to CLK_P/N input pins on the
board (88E2040L devices only).
B2
D12
TEST
I, PD
Test Enable. This pin should be left floating if not
used.
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 31
Alaska M 88E2010/88E2040L
Datasheet - Public
Table 11: Power and Ground
8 8E2010
Pin #
88E2040L
Pin #
Pin Name
Pi n
Ty p e
D e s c ri pt i on
F9
----
F5
F11
F12
F18
P0_VHV
P1_VHV
P2_VHV
P3_VHV
Power
High Voltage Fuse Programming
L5
L7
L9
--
N2
N3
N4
N5
P0_AVDDH
Power
------
N7
N8
N9
N10
P1_AVDDH
Power
-----
N12
N13
N14
N15
P2_AVDDH
Power
-----
N17
N18
N19
N20
P3_AVDDH
Power
M4
M6
M8
N6
T2
T3
T4
T5
P0_AVDDT
Power
-----
T7
T8
T9
T10
P1_AVDDT
Power
-----
T12
T13
T14
T15
P2_AVDDT
Power
-----
T17
T18
T19
T20
P3_AVDDT
Power
These pins must be left floating.
1.8V or 2.0V analog power
2.5V or 2.3V analog power and center-tap power.
Doc. No. MV-S111597-U0 Rev. D
Page 32
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Signal Description
Pin Description
Table 12: Power and Ground (Continued)
8 8E2010
Pin #
88E2040L
Pin #
Pin Name
Pi n
Ty p e
D e s c ri pt i on
E9
M2
M10
--
F21
W21
Y1
Y21
AVDDC
Power
1.5V analog power
K4
K6
K8
---
R2
R3
R4
R5
P0_AVDDL
Power
1.5V analog power
------
R7
R8
R9
R10
P1_AVDDL
Power
-----
R12
R13
R14
R15
P2_AVDDL
Power
-----
R17
R18
R19
R20
P3_AVDDL
Power
D9
E3
D2
D4
P0_AVDDS
Power
---
D6
D8
P1_AVDDS
Power
---
D15
D17
P2_AVDDS
Power
---
D19
D21
P3_AVDDS
Power
E4
E8
---
E4
E6
E15
E17
P0_AVDDR
P1_AVDDR
P2_AVDDR
P3_AVDDR
Power
1.5V analog power
E6
----
E2
E8
E13
E19
P0_VDDR09
P1_VDDR09
P2_VDDR09
P3_VDDR09
Power
0.9V internally regulated power. This pin must be tied
to a capacitor. Do not connect this pin to external
power.
1.5V analog power
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 33
Alaska M 88E2010/88E2040L
Datasheet - Public
Table 12: Power and Ground (Continued)
8 8E2010
Pin #
88E2040L
Pin #
Pin Name
Pi n
Ty p e
D e s c ri pt i on
F5
F7
G5
G7
H5
H7
J5
J7
F7
F9
F13
F15
F17
G7
G9
G11
G13
G15
G17
H7
H9
H11
H13
H15
H17
J7
J9
J11
J13
J15
J17
K7
K9
K11
K13
K15
K17
L7
L9
L11
L13
L15
L17
DVDD
Power
Digital power
0.8V for C-grade
0.88V for I-grade
J3
H5
K5
VDDOL
Power
I/O power - LED, CONFIG, CLK_SEL
G3
E11
VDDOM
Power
I/O power - MDC, MDIO, INTn, TEST
G9
G19
J19
VDDOR
Power
I/O power - RESETn, SPI, RCLK0, RCLK1
J9
K19
VDDOT
Power
I/O power - JTAG
Doc. No. MV-S111597-U0 Rev. D
Page 34
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Signal Description
Pin Description
Table 12: Power and Ground (Continued)
8 8E2010
Pin #
88E2040L
Pin #
Pin Name
Pi n
Ty p e
D e s c ri pt i on
A2
A4
A6
A8
A10
A12
B4
B6
B8
B10
C3
C5
C7
C9
C11
D5
D7
E5
E7
K5
K7
K9
L4
L6
L8
L10
M5
M7
M9
N3
N10
P1
P3
P6
P10
P12
A1
A3
A5
A7
A9
A14
A16
A18
A20
A22
B1
B3
B5
B7
B9
B14
B16
B18
B20
B22
C2
C4
C5
C6
C8
C10
C13
C15
C17
C18
C19
C21
D5
D10
D13
D18
E1
E3
E5
E7
E9
E10
E14
E16
E18
E20
E22
M1
M5
M6
M7
M8
AVSS
Power
Analog Ground
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 35
Alaska M 88E2010/88E2040L
Datasheet - Public
Table 12: Power and Ground (Continued)
8 8E2010
Pin #
88E2040L
Pin #
Pin Name
Pi n
Ty p e
D e s c ri pt i on
--
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
N6
N11
N16
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
R6
R11
R16
T6
T11
T16
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
AVSS (cont.)
Power
Analog Ground
Doc. No. MV-S111597-U0 Rev. D
Page 36
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Signal Description
Pin Description
Table 12: Power and Ground (Continued)
8 8E2010
Pin #
88E2040L
Pin #
Pin Name
Pi n
Ty p e
D e s c ri pt i on
--
U15
U16
U17
U18
U19
U20
V6
V11
V16
V22
W6
W11
W16
Y2
Y5
Y6
Y7
Y10
Y11
Y12
Y15
Y16
Y17
Y20
AA1
AA6
AA11
AA16
AA22
AB1
AB6
AB11
AB16
AB22
AVSS (cont.)
Power
Analog Ground
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 37
Alaska M 88E2010/88E2040L
Datasheet - Public
Table 12: Power and Ground (Continued)
8 8E2010
Pin #
88E2040L
Pin #
Pin Name
Pi n
Ty p e
D e s c ri pt i on
N1
U1
AVSSC
Power
Analog Ground
This must be isolated from AVSS.
A1
F4
F6
F8
F11
G4
G6
G8
H4
H6
H8
J4
J6
J8
J10
B10
B13
F6
F8
F10
F14
F16
G3
G6
G8
G10
G12
G14
G16
G18
H6
H8
H10
H12
H14
H16
H18
H21
J2
J6
J8
J10
J12
J14
J16
J18
K6
K8
K10
K12
K14
K16
K18
L3
L6
L8
L10
L12
L14
L16
L18
L21
P21
VSS
Power
Ground
Doc. No. MV-S111597-U0 Rev. D
Page 38
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Pin Assignment Lists
2.3
Pin Assignment Lists
2.3.1
88E2010 Device Pin Assignment List
Table 13: 88E2010 Pin List — Alphabetical by Signal Name
Pin Number
Pin Nam e
L3
ATN
M3
ATP
K4
AVDDL
K6
AVDDL
K8
AVDDL
L5
AVDDH
L7
AVDDH
L9
AVDDH
M4
AVDDT
M6
AVDDT
M8
AVDDT
N6
AVDDT
E9
AVDDC
M2
AVDDC
M10
AVDDC
E4
AVDDR
E8
AVDDR
D9
AVDDS
E3
AVDDS
A2
AVSS
A4
AVSS
A6
AVSS
A8
AVSS
A10
AVSS
A12
AVSS
B4
AVSS
B6
AVSS
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 39
Alaska M 88E2010/88E2040L
Datasheet - Public
Pin Number
Pin Nam e
B8
AVSS
B10
AVSS
C3
AVSS
C5
AVSS
C7
AVSS
C9
AVSS
C11
AVSS
D5
AVSS
D7
AVSS
E5
AVSS
E7
AVSS
K5
AVSS
K7
AVSS
K9
AVSS
L4
AVSS
L6
AVSS
L8
AVSS
L10
AVSS
M5
AVSS
M7
AVSS
M9
AVSS
N3
AVSS
N10
AVSS
P1
AVSS
P3
AVSS
P6
AVSS
P10
AVSS
P12
AVSS
N1
AVSSC
N11
CHSDACN
Doc. No. MV-S111597-U0 Rev. D
Page 40
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Pin Assignment Lists
Pin Number
Pin Nam e
P11
CHSDACP
N12
CIREF
K2
CLK_SEL[0]
L2
CLK_SEL[1]
J1
CLKN
K1
CLKP
N7
CMN
P7
CMP
H1
CONFIG[0]
D1
CONFIG[1]
D2
CONFIG[2]
E2
CONFIG[3]
G2
CONFIG[4]
H2
CONFIG[5]
D3
CONFIG[6]
H3
CONFIG[7]
M12
CTSTPT
F5
DVDD
F7
DVDD
G5
DVDD
G7
DVDD
H5
DVDD
H7
DVDD
J5
DVDD
J7
DVDD
F10
–
G10
–
H10
–
K10
–
H11
–
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 41
Alaska M 88E2010/88E2040L
Datasheet - Public
Pin Number
Pin Nam e
G12
–
C2
INTn
E1
LED[0]
F1
LED[1]
G1
LED[2]
F2
LED[3]
B1
MDC
N9
MDIN[0]
P8
MDIN[1]
N5
MDIN[2]
P4
MDIN[3]
C1
MDIO
P9
MDIP[0]
N8
MDIP[1]
P5
MDIP[2]
N4
MDIP[3]
H12
RCLK0
G11
RCLK1
D12
RESETn
B11
SHSDACN
A11
SHSDACP
D10
SIN[0]
D8
SIN[1]
D6
SIN[2]
D4
SIN[3]
C10
SIP[0]
C8
SIP[1]
C6
SIP[2]
C4
SIP[3]
B12
SIREF
Doc. No. MV-S111597-U0 Rev. D
Page 42
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Pin Assignment Lists
Pin Number
Pin Nam e
B9
SON[0]
B7
SON[1]
B5
SON[2]
B3
SON[3]
A9
SOP[0]
A7
SOP[1]
A5
SOP[2]
A3
SOP[3]
F12
SPI_CLK
E12
SPI_MISO
E11
SPI_MOSI
D11
SPI_SSn
C12
STSTPT
K12
TCK
K11
TDI
J12
TDO
B2
TEST
M11
TEST_CLKN
L11
TEST_CLKP
J11
TMS
L12
TRSTn
N2
TSTCN
P2
TSTCP
J2
VDDCTRL
J3
VDDOL
G3
VDDOM
G9
VDDOR
J9
VDDOT
E6
VDDR09
F9
VHV
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 43
Alaska M 88E2010/88E2040L
Datasheet - Public
Pin Number
Pin Nam e
K3
VSEL_L
F3
VSEL_M
E10
VSEL_R
H9
VSEL_T
A1
VSS
F4
VSS
F6
VSS
F8
VSS
F11
VSS
G4
VSS
G6
VSS
G8
VSS
H4
VSS
H6
VSS
H8
VSS
J4
VSS
J6
VSS
J8
VSS
J10
VSS
M1
XTAL1
L1
XTAL2
Doc. No. MV-S111597-U0 Rev. D
Page 44
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Pin Assignment Lists
2.3.2
88E2040L Device Pin Assignment List
Table 14: 88E2040L Pin List — Alphabetical by Signal Name
P in N u m b e r
P in N a m e
F21
AVDDC
W21
AVDDC
Y1
AVDDC
Y21
AVDDC
A1
AVSS
A3
AVSS
A5
AVSS
A7
AVSS
A9
AVSS
A14
AVSS
A16
AVSS
A18
AVSS
A20
AVSS
A22
AVSS
B1
AVSS
B3
AVSS
B5
AVSS
B7
AVSS
B9
AVSS
B14
AVSS
B16
AVSS
B18
AVSS
B20
AVSS
B22
AVSS
C2
AVSS
C4
AVSS
C5
AVSS
C6
AVSS
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 45
Alaska M 88E2010/88E2040L
Datasheet - Public
P in N u m b e r
P in N a m e
C8
AVSS
C10
AVSS
C13
AVSS
C15
AVSS
C17
AVSS
C18
AVSS
C19
AVSS
C21
AVSS
D5
AVSS
D10
AVSS
D13
AVSS
D18
AVSS
E1
AVSS
E3
AVSS
E5
AVSS
E7
AVSS
E9
AVSS
E10
AVSS
E14
AVSS
E16
AVSS
E18
AVSS
E20
AVSS
E22
AVSS
M1
AVSS
M5
AVSS
M6
AVSS
M7
AVSS
M8
AVSS
M9
AVSS
M10
AVSS
Doc. No. MV-S111597-U0 Rev. D
Page 46
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Pin Assignment Lists
P in N u m b e r
P in N a m e
M11
AVSS
M12
AVSS
M13
AVSS
M14
AVSS
M15
AVSS
M16
AVSS
M17
AVSS
M18
AVSS
M19
AVSS
N6
AVSS
N11
AVSS
N16
AVSS
P2
AVSS
P3
AVSS
P4
AVSS
P5
AVSS
P6
AVSS
P7
AVSS
P8
AVSS
P9
AVSS
P10
AVSS
P11
AVSS
P12
AVSS
P13
AVSS
P14
AVSS
P15
AVSS
P16
AVSS
P17
AVSS
P18
AVSS
P19
AVSS
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 47
Alaska M 88E2010/88E2040L
Datasheet - Public
P in N u m b e r
P in N a m e
P20
AVSS
R6
AVSS
R11
AVSS
R16
AVSS
T6
AVSS
T11
AVSS
T16
AVSS
U2
AVSS
U3
AVSS
U4
AVSS
U5
AVSS
U6
AVSS
U7
AVSS
U8
AVSS
U9
AVSS
U10
AVSS
U11
AVSS
U12
AVSS
U13
AVSS
U14
AVSS
U15
AVSS
U16
AVSS
U17
AVSS
U18
AVSS
U19
AVSS
U20
AVSS
V6
AVSS
V11
AVSS
V16
AVSS
V22
AVSS
Doc. No. MV-S111597-U0 Rev. D
Page 48
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Pin Assignment Lists
P in N u m b e r
P in N a m e
W6
AVSS
W11
AVSS
W16
AVSS
Y2
AVSS
Y5
AVSS
Y6
AVSS
Y7
AVSS
Y10
AVSS
Y11
AVSS
Y12
AVSS
Y15
AVSS
Y16
AVSS
Y17
AVSS
Y20
AVSS
AA1
AVSS
AA6
AVSS
AA11
AVSS
AA16
AVSS
AA22
AVSS
AB1
AVSS
AB6
AVSS
AB11
AVSS
AB16
AVSS
AB22
AVSS
U1
AVSSC
AA21
CHSDACN
AB21
CHSDACP
Y22
CIREF
M3
CLK_SEL[0]
M4
CLK_SEL[1]
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 49
Alaska M 88E2010/88E2040L
Datasheet - Public
P in N u m b e r
P in N a m e
N1
CLKN
P1
CLKP
L1
CONFIG[0]
L2
CONFIG[1]
M2
CONFIG[2]
L4
CONFIG[3]
H1
CONFIG[4]
H4
CONFIG[5]
J5
CONFIG[6]
G5
CONFIG[7]
W22
CTSTPT
F7
DVDD
F9
DVDD
F13
DVDD
F15
DVDD
F17
DVDD
G7
DVDD
G9
DVDD
G11
DVDD
G13
DVDD
G15
DVDD
G17
DVDD
H7
DVDD
H9
DVDD
H11
DVDD
H13
DVDD
H15
DVDD
H17
DVDD
J7
DVDD
J9
DVDD
Doc. No. MV-S111597-U0 Rev. D
Page 50
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Pin Assignment Lists
P in N u m b e r
P in N a m e
J11
DVDD
J13
DVDD
J15
DVDD
J17
DVDD
K7
DVDD
K9
DVDD
K11
DVDD
K13
DVDD
K15
DVDD
K17
DVDD
L7
DVDD
L9
DVDD
L11
DVDD
L13
DVDD
L15
DVDD
L17
DVDD
D11
INTn
B11
MDC[0]
A11
MDC[1]
A12
MDC[2]
B12
MDC[3]
C11
MDIO[0]
A10
MDIO[1]
A13
MDIO[2]
C12
MDIO[3]
V2
P0_ATN[0]
V3
P0_ATN[1]
V4
P0_ATN[2]
V5
P0_ATN[3]
W2
P0_ATP[0]
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 51
Alaska M 88E2010/88E2040L
Datasheet - Public
P in N u m b e r
P in N a m e
W3
P0_ATP[1]
W4
P0_ATP[2]
W5
P0_ATP[3]
R2
P0_AVDDL
R3
P0_AVDDL
R4
P0_AVDDL
R5
P0_AVDDL
N2
P0_AVDDH
N3
P0_AVDDH
N4
P0_AVDDH
N5
P0_AVDDH
T2
P0_AVDDT
T3
P0_AVDDT
T4
P0_AVDDT
T5
P0_AVDDT
E4
P0_AVDDR
D2
P0_AVDDS
D4
P0_AVDDS
Y3
P0_CMN
Y4
P0_CMP
L22
P0_GPIO[0]
L20
P0_GPIO[1]
H22
P0_GPIO[2]
K1
P0_LED[0]
K2
P0_LED[1]
K3
P0_LED[2]
K4
P0_LED[3]
AA2
P0_MDIN[0]
AA3
P0_MDIN[1]
AA4
P0_MDIN[2]
Doc. No. MV-S111597-U0 Rev. D
Page 52
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Pin Assignment Lists
P in N u m b e r
P in N a m e
AA5
P0_MDIN[3]
AB2
P0_MDIP[0]
AB3
P0_MDIP[1]
AB4
P0_MDIP[2]
AB5
P0_MDIP[3]
D1
P0_SIN[0]
D3
P0_SIN[1]
C1
P0_SIP[0]
C3
P0_SIP[1]
B2
P0_SON[0]
B4
P0_SON[1]
A2
P0_SOP[0]
A4
P0_SOP[1]
E2
P0_VDDR09
F5
P0_VHV
V10
P1_ATN[0]
V9
P1_ATN[1]
V8
P1_ATN[2]
V7
P1_ATN[3]
W10
P1_ATP[0]
W9
P1_ATP[1]
W8
P1_ATP[2]
W7
P1_ATP[3]
R7
P1_AVDDL
R8
P1_AVDDL
R9
P1_AVDDL
R10
P1_AVDDL
N7
P1_AVDDH
N8
P1_AVDDH
N9
P1_AVDDH
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 53
Alaska M 88E2010/88E2040L
Datasheet - Public
P in N u m b e r
P in N a m e
N10
P1_AVDDH
T7
P1_AVDDT
T8
P1_AVDDT
T9
P1_AVDDT
T10
P1_AVDDT
E6
P1_AVDDR
D6
P1_AVDDS
D8
P1_AVDDS
Y9
P1_CMN
Y8
P1_CMP
M22
P1_GPIO[0]
M20
P1_GPIO[1]
H20
P1_GPIO[2]
J1
P1_LED[0]
J3
P1_LED[1]
H3
P1_LED[2]
J4
P1_LED[3]
AA10
P1_MDIN[0]
AA9
P1_MDIN[1]
AA8
P1_MDIN[2]
AA7
P1_MDIN[3]
AB10
P1_MDIP[0]
AB9
P1_MDIP[1]
AB8
P1_MDIP[2]
AB7
P1_MDIP[3]
D9
P1_SIN[0]
D7
P1_SIN[1]
C9
P1_SIP[0]
C7
P1_SIP[1]
B8
P1_SON[0]
Doc. No. MV-S111597-U0 Rev. D
Page 54
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Pin Assignment Lists
P in N u m b e r
P in N a m e
B6
P1_SON[1]
A8
P1_SOP[0]
A6
P1_SOP[1]
E8
P1_VDDR09
F11
P1_VHV
V12
P2_ATN[0]
V13
P2_ATN[1]
V14
P2_ATN[2]
V15
P2_ATN[3]
W12
P2_ATP[0]
W13
P2_ATP[1]
W14
P2_ATP[2]
W15
P2_ATP[3]
R12
P2_AVDDL
R13
P2_AVDDL
R14
P2_AVDDL
R15
P2_AVDDL
N12
P2_AVDDH
N13
P2_AVDDH
N14
P2_AVDDH
N15
P2_AVDDH
T12
P2_AVDDT
T13
P2_AVDDT
T14
P2_AVDDT
T15
P2_AVDDT
E15
P2_AVDDR
D15
P2_AVDDS
D17
P2_AVDDS
Y13
P2_CMN
Y14
P2_CMP
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 55
Alaska M 88E2010/88E2040L
Datasheet - Public
P in N u m b e r
P in N a m e
N22
P2_GPIO[0]
M21
P2_GPIO[1]
J21
P2_GPIO[2]
G1
P2_LED[0]
G2
P2_LED[1]
H2
P2_LED[2]
G4
P2_LED[3]
AA12
P2_MDIN[0]
AA13
P2_MDIN[1]
AA14
P2_MDIN[2]
AA15
P2_MDIN[3]
AB12
P2_MDIP[0]
AB13
P2_MDIP[1]
AB14
P2_MDIP[2]
AB15
P2_MDIP[3]
D14
P2_SIN[0]
D16
P2_SIN[1]
C14
P2_SIP[0]
C16
P2_SIP[1]
B15
P2_SON[0]
B17
P2_SON[1]
A15
P2_SOP[0]
A17
P2_SOP[1]
E13
P2_VDDR09
F12
P2_VHV
V20
P3_ATN[0]
V19
P3_ATN[1]
V18
P3_ATN[2]
V17
P3_ATN[3]
W20
P3_ATP[0]
Doc. No. MV-S111597-U0 Rev. D
Page 56
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Pin Assignment Lists
P in N u m b e r
P in N a m e
W19
P3_ATP[1]
W18
P3_ATP[2]
W17
P3_ATP[3]
R17
P3_AVDDL
R18
P3_AVDDL
R19
P3_AVDDL
R20
P3_AVDDL
N17
P3_AVDDH
N18
P3_AVDDH
N19
P3_AVDDH
N20
P3_AVDDH
T17
P3_AVDDT
T18
P3_AVDDT
T19
P3_AVDDT
T20
P3_AVDDT
E17
P3_AVDDR
D19
P3_AVDDS
D21
P3_AVDDS
Y19
P3_CMN
Y18
P3_CMP
P22
P3_GPIO[0]
N21
P3_GPIO[1]
K21
P3_GPIO[2]
F1
P3_LED[0]
F2
P3_LED[1]
F3
P3_LED[2]
F4
P3_LED[3]
AA20
P3_MDIN[0]
AA19
P3_MDIN[1]
AA18
P3_MDIN[2]
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 57
Alaska M 88E2010/88E2040L
Datasheet - Public
P in N u m b e r
P in N a m e
AA17
P3_MDIN[3]
AB20
P3_MDIP[0]
AB19
P3_MDIP[1]
AB18
P3_MDIP[2]
AB17
P3_MDIP[3]
D22
P3_SIN[0]
D20
P3_SIN[1]
C22
P3_SIP[0]
C20
P3_SIP[1]
B21
P3_SON[0]
B19
P3_SON[1]
A21
P3_SOP[0]
A19
P3_SOP[1]
E19
P3_VDDR09
F18
P3_VHV
K22
RCLK0
J22
RCLK1
G22
RESETn
F20
SHSDACN
F19
SHSDACP
E21
SIREF
K20
SPI_CLK
J20
SPI_MISO
G20
SPI_MOSI
G21
SPI_SSn
F22
STSTPT
R21
TCK
T21
TDI
U21
TDO
D12
TEST
Doc. No. MV-S111597-U0 Rev. D
Page 58
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Pin Assignment Lists
P in N u m b e r
P in N a m e
T22
TEST_CLKN
U22
TEST_CLKP
V21
TMS
R22
TRSTn
V1
TSTCN
W1
TSTCP
H5
VDDOL
K5
VDDOL
E11
VDDOM
G19
VDDOR
J19
VDDOR
K19
VDDOT
L5
VSEL_L
E12
VSEL_M
H19
VSEL_R
L19
VSEL_T
B10
VSS
B13
VSS
F6
VSS
F8
VSS
F10
VSS
F14
VSS
F16
VSS
G3
VSS
G6
VSS
G8
VSS
G10
VSS
G12
VSS
G14
VSS
G16
VSS
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 59
Alaska M 88E2010/88E2040L
Datasheet - Public
P in N u m b e r
P in N a m e
G18
VSS
H6
VSS
H8
VSS
H10
VSS
H12
VSS
H14
VSS
H16
VSS
H18
VSS
H21
VSS
J2
VSS
J6
VSS
J8
VSS
J10
VSS
J12
VSS
J14
VSS
J16
VSS
J18
VSS
K6
VSS
K8
VSS
K10
VSS
K12
VSS
K14
VSS
K16
VSS
K18
VSS
L3
VSS
L6
VSS
L8
VSS
L10
VSS
L12
VSS
L14
VSS
Doc. No. MV-S111597-U0 Rev. D
Page 60
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Pin Assignment Lists
P in N u m b e r
P in N a m e
L16
VSS
L18
VSS
L21
VSS
P21
VSS
T1
XTAL1
R1
XTAL2
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 61
Alaska M 88E2010/88E2040L
Datasheet - Public
3
Functional Description
This section describes the chip-level functionality.
3.1
Buffering
Packets may flow through some buffering. Buffering will occur for a variety of all the reasons described in this
section.
3.1.1
EEE Buffering
EEE PHY functionality to operate correctly, an EEE-compliant MAC is required to control the PHY as when to
enter and exit the low power idle (LPI) state and buffer packets to allow the PHY adequate time to exit the low
power idle state. The PHY should beset to transparent (slave) EEE mode when operating with an EEE-compliant
MAC (register 1.C033.0 = 0).
The device is able to support non-EEE compliant MACs by enabling the internal EEE buffering by setting register
1.C033.0 to 1. EEE buffering is automatically disabled when the device or its link partner is not capable of EEE
operation.
When the EEE buffer is empty for the amount of time specified by registers 1.C033.15:8, 31.F004.7:0,
31.F004.15:8 for 10 Gbps, 1000 Mbps, and 100 Mbps speeds, respectively (in units of 1 microsecond), the buffer
will indicate to the PHY that it wishes to enter the LPI state.
When the EEE buffer is not empty it will indicate to the PHY that it must exit the LPI state. The EEE buffer
ensures that no packets are lost by the PHY during the transition from LPI state to normal mode of operation.
When the media interface exits the LPI state, the data in the buffer is then released and transmitted to the line.
The amount of time the packet is held in the buffer prior to release can be programmed via registers
31.F005.15:8, 31.F006.7:0, and 31.F006.15:8 for 10 Gbps, 1000 Mbps, and 100 Mbps speeds, respectively. The
unit is in microseconds. The minimum IPG between packets as set in 31.F005.7:0 will be used to separate
packets until the EEE buffer is fully drained.
3.2
Link Interrupt
When the MACs are not bypassed, all local and remote faults received on the line or host will be terminated by
the MAC. For example, if a local fault is received on the line, then the MAC terminates the local fault and never
passes it upstream to the host. The MAC will transmit a remote fault back to the line.
Doc. No. MV-S111597-U0 Rev. D
Page 62
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Functional Description
Loopback
3.3
Loopback
The T, X, and H Units has the ability to perform MAC loopback and line loopback as shown in Figure 5. Each unit
can only be in MAC loopback or line loopback at any given time. If MAC loopback is engaged, then loopback
speed depends upon the media link speed. If the media link is down, then the MAC interface speed is dependent
upon the setting in 31.F000.7:6, Default MAC Interface Speed. A deep line loopback must not be enabled at the
same time as a MAC loopback or a closed internal bus loop will be created.
Table 15:
Loopback Control
Loopback
P o in t
R e g is te r
Function
S etting
A
3.0000.14
T Unit Deep MAC Loopback
1 = Loopback
0 = Normal operation
B
3.1000.14
3.2000.14
X Unit Deep MAC Loopback
1 = Loopback
0 = Normal operation
C
4.0000.14
4.1000.14
4.2000.14
H Unit Deep Line Loopback
1 = Loopback
0 = Normal operation
D
3.8002.5
T Unit Shallow Line Loopback
for 1000/100/10 mode
1 = Enable Line Loopback
0 = Normal operation
E
1.C000.11
T Unit Shallow Line Loopback
for 5G/2.5G mode
1 = Enable Line Loopback
0 = Normal operation
F
3.F003.12
X Unit Shallow Line Loopback
1 = Enable Line Loopback
0 = Normal operation
G
4.F003.12
H Unit Shallow MAC Loopback
1 = Enable Line Loopback
0 = Normal operation
–
31.F000.7:6
Default MAC Interface Speed
This is the MAC Interface
Speed during Link down.
00 = 10 Mbps
01 = 100 Mbps
10 = 1000 Mbps
11 = 10 Gbps
–
31.F0A8.1:0
Device Max Speed Limit
Control
This controls the link down
max speed.
00 = 10 Gbps
10 = 5 Gbps
11 = 2.5 Gbps
Port soft reset should be
followed.
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 63
Alaska M 88E2010/88E2040L
Datasheet - Public
Figure 5: Loopback Paths
3.3.1
MAC Loopback
MAC loopback is defined as taking data from the MAC interface and transmitting that data back towards the MAC
interface. For the loopback to occur, the unit must have control of the XGMII bus that it is outputting on, that is,
that unit must have control of the data path.
If the link is down, then the loopback speed will be determined by register 31.F000.7:6 and 31.F0A8.1:0. Only
host shallow MAC loopback is supported when the media link is down.
Doc. No. MV-S111597-U0 Rev. D
Page 64
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Functional Description
Configuration and Resets
3.3.2
Line Loopback
Line loopback is defined to be looping the data that is received on the network interface and transmitting that
data back onto the network interface.
The speed of the loopback is determined by the active link speed.
3.4
Configuration and Resets
The device can be configured in the following ways:
Hardware configuration strap options
MDC/MDIO register access
All hardware configuration options can be overwritten via the other methods except PHYADR and MDIO.
This section will discuss the hardware configuration.
3.4.1
Hardware and Software Resets
RESETn is the hardware reset pin for the entire chip. To ensure that the stopping of the hardware
configuration is correct, it is required that upon system power-up, a reset signal be applied to
RESETn or the RESETn pin be held low until all the power rails are settled down.
In addition to the hardware reset pin (RESETn), there are several software reset bits that reset various parts of
the chip.
A hardware reset will reset the entire chip and initialize all the registers to their hardware reset
default.
A software reset has a similar effect on the affected units as a hardware reset except all
Retain-type of will hold their value, and the Update-type registers will have the previously written
values take effect.
Register 31.F001.14 is a software bit that emulates the hardware reset. Setting the bit to 1 will reset
the entire chip (all ports) as if the RESETn pin is asserted. All ports have register 31.F001.14;
however, special care should be taken when selecting the specific port number to achieve entire
chip reset. The applicable register in Port 3 (88E2040L) and Port 0 (88E2010) should be
programmed. When triggered, registers are not accessible through the MDIO until the chip reset
completes.
Setting register 31.F001.15 to 1 software resets the entire port except for the T Unit. The T Unit will
briefly power down and Auto-Negotiation will restart.
Setting registers 31.F001.13, 1.0000.15, 3.0000.15, or 7.0000.15 to 1 software resets the T Unit
only.
Setting registers 4.0000.15, 4.1000.15, or 4.2000.15 to 1 software resets the H Unit only.
3.4.2
Hardware Configuration
After the deassertion of RESETn the device will be hardware configured through the CONFIG[7:0] pins. Each pin
is used to configure 3 bits. The 3-bit value is set depending on which LED pin or static level is connected to the
CONFIG pins at the deassertion of hardware reset.
The three configuration bits per pin mapping for the 88E2010 device is shown in Table 16.
The three bit mapping for the 88E2010 device during hardware configuration is shown in Table 17.
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 65
Alaska M 88E2010/88E2040L
Datasheet - Public
Table 16: 88E2010 Device Configuration Mapping
Pin Test
Bit 2
Bit 1
Bit 2
CONFIG[0]
PHYAD[4]
PHYAD[3]
PHYAD[2]
CONFIG[1]
ANEG_MS
PHYAD[1]
PDSTATE
CONFIG[2]
ANEG_SPD[2]
ANEG_SPD[1]
ANEG_SPD[0]
CONFIG[3]
MACTYPE[2]
MACTYPE[1]
MACTYPE[0]
CONFIG[4]
MEDIATYPE[2]
MEDIATYPE[1]
MEDIATYPE[0]
CONFIG[5]
SPI_CONFIG
RESERVED
RESERVED
CONFIG[7]
FACTORY_TEST
RESERVED
RESERVED
Table 17: 88E2010 Three Bit Mapping
Pin
Bit 2
VSS
000
LED[0]
001
LED[1]
010
LED[2]
011
LED[3]
100
Reserved
101
Reserved
110
VDDO
111
The three configuration bits per pin mapping for the 88E2040L device is shown in Table 18.
The three bit mapping for the 88E2040L device during hardware configuration is shown in Table 19.
Table 18: 88E2040L Device Configuration Mapping
Pin
Bit 2
Bit 1
Bit 0
CONFIG[0]
PHYAD[4]
PHYAD[3]
PHYAD[2]
CONFIG[1]
ANEG_MS
RESERVED
PDSTATE
CONFIG[2]
ANEG_SPD[2]
ANEG_SPD[1]
ANEG_SPD[0]
CONFIG[3]
MACTYPE[2]
MACTYPE[1]
MACTYPE[0]
CONFIG[4]
MEDIATYPE[2]
MEDIATYPE[1]
MEDIATYPE[0]
CONFIG[5]
SPI_CONFIG
RESERVED
RESERVED
CONFIG[7]
FACTORY_TEST
MDIO[1]
MDIO[0]
Doc. No. MV-S111597-U0 Rev. D
Page 66
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Functional Description
Configuration and Resets
Table 19: 88E2040L Device Three Bit Mapping
Pin
Bit 2:0
VSS
000
P3_LED[0]
001
P3_LED[1]
010
P2_LED[0]
011
P2_LED[1]
100
P1_LED[0]
101
P1_LED[1]
110
VDDO
111
The configuration bit definition is shown in Table 20.
Table 20: Configuration Bit Definition
Bits
Definition
D e s c ri pt i on
PHYAD[4:0]
PHY Address
88E2040L
PHYAD[1:0] is hardcoded as a function of REV_
PHYAD.
REV_PHYAD
88E2040L - Reverse PHYAD[1:0] order
88E2010 - N/A
88E2040L
PHYAD[1:0] corresponds to the following:
0 = 00 - Port 0
01 - Port 1
10 - Port 2
11 - Port 3
1 = 00 - Port 3
01 - Port 2
10 - Port 1
11 - Port 0
MDIO[1:0]
(88E2040L)
This determines whether the four ports are
accessed from a 1 MDIO, 2 ports per MDIO, or
1 MDIO per port.
00 = MDC[2]/MDIO[2] Access on all four ports
01 = MDC[1]/MDIO[1] Accesses Port 0 and
Port 1
MDC[2]/MDIO[2] Accesses Port 2 and
Port 3
10 = MDC[0]/MDIO[0] Accesses Port 0
MDC[1]/MDIO[1] Accesses Port 1
MDC[2]/MDIO[2] Accesses Port 2
MDC[3]/MDIO[3] Accesses Port 3
11 = Reserved
None
Copyright © 2020 Marvell
December 1, 2020
Doc. No. MV-S111597-U0 Rev. D
Document Classification: Public
Page 67
Alaska M 88E2010/88E2040L
Datasheet - Public
Table 20: Configuration Bit Definition (Continued)
Bits
Definition
D e s c ri pt i on
MACTYPE[2:0]
(88E2040L)
000 = Reserved
001 = Reserved
010 = Reserved
011 = Reserved
100 = 5GBASE-R/2500BASE-X/SGMII
Auto-Negotiation On
101 = 5GBASE-R/2500BASE-X/SGMII
Auto-Negotiation Off
110 = Reserved
111 = Reserved
C Unit
Host interface mode for 88E2040L
MACTYPE[2:0]
(88E2010)
000 = Reserved
001 = Reserved
010 = Reserved
011 = 5GBASE-R/2500BASE-X/SGMII
Auto-Negotiation On
100 = 5GBASE-R/2500BASE-X/SGMII
Auto-Negotiation On
101 = 5GBASE-R/2500BASE-X/SGMII SGMII
Auto-Negotiation Off
110 = Reserved
111 = Reserved
C Unit
Host interface mode for 88E2010
MEDIATYPE[2:0]
000 = Copper Only
001-111 = RESERVED
C Unit
Line-side interface
PDSTATE
0 = Start In Power Up State
1 = Start In Power Down State
T Unit
Copper power down state
ANEG_MS
0 = Prefer Slave
1 = Prefer Master
T Unit
Master and slave configuration
FACTORY_TEST
Factory Test Mode
0 = Normal mode (default)
1 = Test Mode (reserved for Marvell)
None
ANEG_SPD[2:0]
This sets the default for speed advertisement
during Auto-Negotiation.
000 = Reserved
001 = 5G, 2.5G, 1000 Mbps Full
010 = 5G, 2.5G, 1000 Mbps Full, 100 Mbps Full
011 = 5G, 2.5G, 1000 Mbps Full, 100 Mbps
Full, 10 Mbps Full
100 = 5G, 2.5G, 1000 Mbps Full, 100 Mbps
Full/Half
101 = 5G, 2.5G, 1000 Mbps Full, 100 Mbps
Full/Half, 10 Mbps Full/Half
110 = 5G, 2.5G, 1000 Mbps Full/Half, 100
Mbps Full/Half
111 = 5G, 2.5G, 1000 Mbps Full/Half, 100 Mbps
Full/Half, 10 Mbps Full/Half
–
Doc. No. MV-S111597-U0 Rev. D
Page 68
Copyright © 2020 Marvell
Document Classification: Public
December 1, 2020
Functional Description
Configuration and Resets
Table 20: Configuration Bit Definition (Continued)
Bits
Definition
D e s c ri pt i on
SPI_CONFIG
–
C Unit
31.F008.5
工商网监
湘ICP备2023018690号
