88EM8040xx-SAG2C000

Cover 88EM8040/88EM8041 Power Factor Correction Controller for Flyback Topology Datasheet Customer Use Only Doc. No. MV-S104983-01, Rev. A October 5, 2009 Marvell. Moving Forward Faster Document Classification: Proprietary 88EM8040/88EM8041 Datasheet Document Conventions Note: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury. Document Status Doc Status: Preliminary Technical Publication: 0.xx For more information, visit our website at: www.marvell.com Disclaimer No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. 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At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright © 1999–2009. Marvell International Ltd. All rights reserved. Marvell, Moving Forward Faster, the Marvell logo, Alaska, AnyVoltage, DSP Switcher, Fastwriter, Feroceon, Libertas, Link Street, PHYAdvantage, Prestera, TopDog, Virtual Cable Tester, Yukon, and ZJ are registered trademarks of Marvell or its affiliates. CarrierSpan, LinkCrypt, Powered by Marvell Green PFC, Qdeo, QuietVideo, Sheeva, TwinD, and VCT are trademarks of Marvell or its affiliates. Patent(s) Pending—Products identified in this document may be covered by one or more Marvell patents and/or patent applications. Doc. No. MV-S104983-01 Rev. A Page 2 Document Classification: Proprietary Copyright © 2009 Marvell October 5, 2009, Preliminary 88EM8040/88EM8041 Power Factor Correction Controller for Flyback Topology Datasheet PRODUCT OVERVIEW The Marvell® 88EM8040/88EM8041 device is a high performance Power Factor Correction (PFC) Controller for flyback applications. Both devices work at fixed frequencies, 88EM8040 at 60kHz while 88EM8041 at 120kHz. It can be used in a wide variety of universal input PFC flyback converters with an output power range of up to 150W without using any external driver. Marvell advanced mixed signal technology ensures the lowest Total Harmonic Distortion (THD) in the industry. The IC operates under average Continuous Conduction Mode (CCM). The 88EM8040/88EM8041 PFC controller improves the steady state and transient performance through Marvell's innovative Digital Signal Processing (DSP) solution. The proprietary adaptive over-current protection has the ability to ensure almost constant power constraint and provides safety provisions including open loop and over voltage protection protocols. The internal voltage loop compensation and current loop control guarantees system stability and thus reduces the external component count and costs. The 8-pin SOIC package further facilitates the application design process, saving board space. The resultant simple system design and minimum cost makes 88EM8040/88EM8041 the ideal choice for any flyback application with PFC. General Features Patented DSP control with adaptive loop coefficient Continuous Conduction Mode (CCM) operation Average current mode control Adaptive control loop achieves high power factor for a wide range of voltage and load conditions Adaptive over current protection for universal voltage Fixed frequency of operation High power factor and low harmonic distortion for a wide range of load conditions Up to 2A driver capability Minimal external components required Under voltage lockout (UVLO) Over voltage protection (OVP) Thermal shutdown Input line frequency range from 45Hz to 65Hz Applications Universal input PFC flyback converters AC/DC adaptors and battery charger Figure 1: PFC Flyback Circuit Diagram V DCin Bridge Retifier diode C in PFC Csn Rsn Dsn AC IN Rcs Ra Rb Rc Ccs OCP SW SGND R S1 R gate R sen Drain Q1 Np DR2 Vout N S2 C O2 Load ISNS VIN VDD 88EM8040/ 8041 FB PGND R S4 C S2 R S2 C S1 R S5 Opto-Coupler CVDD R f1 Vref R S3 Copyright © 2009 Marvell October 5, 2009, Preliminary Document Classification: Proprietary Doc. No. MV-S104983-01 Rev. A Page 3 88EM8040/88EM8041 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S104983-01 Rev. A Page 4 Document Classification: Proprietary Copyright © 2009 Marvell October 5, 2009, Preliminary Table of Contents Table of Contents Table of Contents ....................................................................................................................................... 5 List of Figures............................................................................................................................................. 7 List of Tables .............................................................................................................................................. 9 1 1.1 1.2 Signal Description ....................................................................................................................... 11 Pin Configurations ...........................................................................................................................................11 Pin Descriptions ..............................................................................................................................................11 2 2.1 2.2 2.3 Electrical Specifications ............................................................................................................. 13 Absolute Maximum Ratings ...........................................................................................................................13 Recommended Operating Conditions .............................................................................................................14 Electrical Characteristics ................................................................................................................................15 3 3.1 3.2 Functional Description................................................................................................................ 19 Overview .........................................................................................................................................................19 Signal Process and Functions.........................................................................................................................20 4 4.1 4.2 4.3 4.4 Functional Characteristics ......................................................................................................... 21 VDD Characteristics ........................................................................................................................................21 VFB Characteristics for Over Voltage Protection .............................................................................................23 Switching Frequency Characteristics ..............................................................................................................24 Over Current Threshold Characteristics..........................................................................................................25 5 5.1 5.2 Design and Applications Information ........................................................................................ 27 Input Voltage Resistor Divider on VIN Pin.......................................................................................................28 Isolated Voltage Loop and Output Voltage Feedback on FB Pin ....................................................................30 5.2.1 Resistor Divider Design for Output Voltage ......................................................................................31 5.2.2 Compensation Network Design ........................................................................................................31 5.2.3 RS2 and Rf1 Design .........................................................................................................................33 Current Sensing and Over Current Protection ................................................................................................34 5.3.1 Current Sensing Through ISNS Pin ..................................................................................................34 5.3.2 Average Current Signal and Over Power Limitation .........................................................................35 5.3.3 Cycle by Cycle Current Protection through OCP Pin........................................................................36 5.3.4 Peak Current and Average Current Relationship .............................................................................38 SW Pin to MOSFET Gate ...............................................................................................................................39 VDD, Signal Ground (SGND) and Power Ground (PGND) .............................................................................39 90W/20V Signal Stage PFC Adaptor Schematic and Bill of Materials (BOM).................................................41 5.3 5.4 5.5 5.6 Copyright © 2009 Marvell October 5, 2009, Preliminary Document Classification: Proprietary Doc. No. MV-S104983-01 Rev. A Page 5 88EM8040/88EM8041 Datasheet 6 6.1 Mechanical Drawings .................................................................................................................. 43 Mechanical Drawings ......................................................................................................................................43 7 7.1 7.2 Part Order Numbering/Package Marking .................................................................................. 45 Part Order Numbering ..................................................................................................................................45 Package Markings...........................................................................................................................................46 A Revision History .......................................................................................................................... 47 Doc. No. MV-S104983-01 Rev. A Page 6 Document Classification: Proprietary Copyright © 2009 Marvell October 5, 2009, Preliminary List of Figures List of Figures Figure 1: PFC Flyback Circuit Diagram ............................................................................................................3 1 Signal Description ........................................................................................................................... 11 Figure 2: SOIC-8 Pin Diagram (Top View).......................................................................................................11 2 3 Electrical Specifications ................................................................................................................. 13 Functional Description.................................................................................................................... 19 Figure 3: Top Level Block Diagram..................................................................................................................19 4 Functional Characteristics.............................................................................................................. 21 Figure 4: Figure 5a: Figure 5b: Figure 6a: Figure 6b: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: IDD Quiescent (IDD_QST) vs. VDD ...................................................................................................21 IDD vs. VDD (VDD_ON) ........................................................................................................................21 IDD vs. VDD (VDD_ON)........................................................................................................................21 IDD Operation (IDD_OP) vs. Temperature ........................................................................................22 IDD Operation (IDD_OP) vs. Temperature ........................................................................................22 VDD On/Off vs. Temperature ...........................................................................................................22 IDD vs. VFB (OVP) .............................................................................................................................23 VFB_OVP vs. Temperature ..............................................................................................................23 VFB_OVP Hysteresis vs. Temperature ............................................................................................23 VFB_OVP_LATCH vs. Temperature ................................................................................................23 Normal Regulation Reference (VFB_REG) vs. Temperature ...........................................................24 Switching Frequency vs. Temperature .............................................................................................24 Over Current (VIOVER) vs. Input Voltage VIN Peak Value).............................................................25 Over Current (VIOVER) vs. Temperature .........................................................................................25 VIOVER_CYC_ON/OFF vs. Temperature ........................................................................................26 5 Design and Applications Information ............................................................................................ 27 Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Internal Block for Zero-cross Detection, Brown-out Protection .........................................................28 Peak Detecting Signal for Predictive Sinusoidal AC Voltage............................................................29 Input Voltage Resistor Divider Layout Guidelines ............................................................................30 Secondary Compensation Network with Opt-coupler .......................................................................30 Bode Plot of Compensation Network at Secondary Side .................................................................32 Bias Current for Offset Voltage on FB Pin ........................................................................................33 Current Sensing Circuit.....................................................................................................................34 Current Sensing and Cycle by Cycle Over Current Protection Circuit ..............................................36 Current Sensing and Cycle by Cycle Over Current Protection Waveforms ......................................36 SW Pin Layout Guidelines ................................................................................................................39 VDD Decoupling Capacitor and Ground Layout Guidelines .............................................................40 90W/20V Single Stage PFC Adaptor Schematic ..............................................................................41 Copyright © 2009 Marvell October 5, 2009, Preliminary Document Classification: Proprietary Doc. No. MV-S104983-01 Rev. A Page 7 88EM8040/88EM8041 Datasheet 6 Mechanical Drawings ...................................................................................................................... 43 Figure 29: 8-Lead SOIC Mechanical Drawing ...................................................................................................43 7 Part Order Numbering/Package Marking....................................................................................... 45 Figure 30: Figure 31: 88EM8040/88EM8041 Sample Ordering Part Number ....................................................................45 88EM8040/88EM8041 Package Marking .........................................................................................46 A Revision History ............................................................................................................................... 47 Doc. No. MV-S104983-01 Rev. A Page 8 Document Classification: Proprietary Copyright © 2009 Marvell October 5, 2009, Preliminary List of Tables List of Tables 1 Signal Description ............................................................................................................................ 11 Table 1: Table 2: Pin Descriptions ................................................................................................................................11 Pin Descriptions ................................................................................................................................12 2 Electrical Specifications .................................................................................................................. 13 Table 3: Table 4: Table 5: Absolute Maximum Ratings ..............................................................................................................13 Recommended Operating Conditions...............................................................................................14 Electrical Characteristics ..................................................................................................................15 3 4 5 Functional Description..................................................................................................................... 19 Functional Characteristics............................................................................................................... 21 Design and Applications Information ............................................................................................. 27 Table 6: Table 7: Table 8: Comparison Between Average Current Mode and Critical Transition Mode Control........................27 Current Sensing Circuit.....................................................................................................................35 Current Sensing Resistor Selection Reference ................................................................................35 6 7 A Mechanical Drawings ....................................................................................................................... 43 Part Order Numbering/Package Marking........................................................................................ 45 Table 9: 88EM8040/88EM8041 Part Order Options .......................................................................................45 Revision History ............................................................................................................................... 47 Table 10: Revision History ................................................................................................................................47 Copyright © 2009 Marvell October 5, 2009, Preliminary Document Classification: Proprietary Doc. No. MV-S104983-01 Rev. A Page 9 88EM8040/88EM8041 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S104983-01 Rev. A Page 10 Document Classification: Proprietary Copyright © 2009 Marvell October 5, 2009, Preliminary Signal Description Pin Configurations 1 1.1 Signal Description Pin Configurations Figure 2: SOIC-8 Pin Diagram (Top View) PGND 1 8 SW SGND 2 7 VDD ISNS 3 6 OCP VIN 4 5 FB 1.2 Pi n # 1 2 3 4 5 6 7 8 Pin Descriptions Table 1: P in N a m e PGND SGND ISNS VIN FB OCP VDD SW Pin Descriptions P i n Ty p e Ground Ground Input Input Input Input Supply Output P in D e s c r i p t io n Power Ground Signal Ground Current Sense Voltage Input Feedback Over Voltage Current Protection IC Supply Voltage Switch Copyright © 2009 Marvell October 5, 2009, Preliminary Document Classification: Proprietary Doc. No. MV-S104983-01 Rev. A Page 11 88EM8040/88EM8041 Datasheet Table 2: P in # 1 Pin Descriptions P in N a m e PGND Pi n F u nc t io n Power Ground Connected to the source of the primary MOSFET. The PCB trace from the power ground to the source of the primary MOSFET must be kept as short as possible. To avoid any switching noise interruption on signal processing, PGND and SGND remain seperate inside the IC. Signal Ground Must be connected to the power ground with the Kelvin sensing connection, so that SGND has dedicated trace and connections and provides noiseless environment for the signal processing. Current Sense Sense resistor varies from 0.15Ω at 120W rated load to 0.44Ω for 40W rated load. Used for current shaping and for over current protection. Voltage Input • Connects to resistive divider at input AC line “phase” to GND. Voltage applied is a half rectified sine wave scaled down by the input resistive divider. • Voltage input pin is a high impedance input pin. An impedance of 2M (typical) is recommended to be designed from the input AC “phase” to GND in order to reduce the standby power. Higher impedance is preferred with the right PCB design on this pin signal. • Voltage is compared with a threshold reference (VVIN_BR) to detect the zero-cross location of the input sine wave and synthesize (regenerate) the input sine wave. This sine wave is used to generate the current reference. • Brown-out protection1 function is also provided by this pin. A resistor devider with a 100:1 ratio from the highside resistor to the lowside resistor is corresponding to the “brown-out protection” input voltage as 50V (RMS). Increasing that raio will increase the “brown-out voltage”. Please refer to footnote1 for further explaination. Feedback It is connected to the emitter of the transistor on the secondary side of the opto coupler (referred to within the Appication Information section). The output voltage is scaled to 2.5V with 100% rated value. Transition from soft start to normal regulation at 87.5% rated VFB. Over voltage shutdown SW gate signal at 107% rated VFB and recover once below VFB_OVP. There is another threshold (VFB_OVP_LATCH) as 3.77V on the FB pin. When FB Voltage reaches VFB_OVP_LATCH, SW signal is shutdown and latched until another VDD power on reset. Over Current Protection Used to turn off the MOSFET when it is pulled as logic low IC Supply Voltage Nominal voltage is typical 12V and the Under Voltage Lock Out (UVLO) for VDD