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MAS6180A2TC00

MAS6180A2TC00

  • 厂商:

    MAS

  • 封装:

  • 描述:

    MAS6180A2TC00 - AM Receiver IC - Micro Analog systems

  • 数据手册
  • 价格&库存
MAS6180A2TC00 数据手册
DA6180.001 27 December, 2006 MAS6180 AM Receiver IC • • • • • • • • DESCRIPTION The MAS6180 AM-Receiver chip is a highly sensitive, simple to use AM receiver specially intended to receive time signals in the frequency range from 40 kHz to 100 kHz. Only a few external components are required for time signal receiver. The circuit has preamplifier, wide range automatic gain control, demodulator and output comparator built in. The output signal can be processed directly by an additional digital circuitry to extract the data from the received signal. The control for AGC (automatic gain control) can be used to switch AGC on or off if necessary. MAS6180 has options for compensating shunt capacitances of different crystals (See ordering information on page 9). Single Band Receiver IC High Sensitivity Very Low Power Consumption Wide Supply Voltage Range Power Down Control Control for AGC On High Selectivity by Crystal Filter Fast Startup Feature FEATURES • • • • • • • • • • • • Single Band Receiver IC Highly Sensitive AM Receiver, 0.4 µVRMS typ. W ide Supply Voltage Range from 1.1 V to 3.6 V Very Low Power Consumption Power Down Control Fast Startup Only a Few External Components Necessary Control for AGC On W ide Frequency Range from 40 kHz to 100 kHz High Selectivity by Quartz Crystal Filter Crystal Compensation Capacitance Options Differential Input APPLICATIONS • Single Band Time Signal Receiver WWVB (USA), JJY (Japan), DCF77 (Germany), MSF (UK), HGB (Switzerland) and BPC (China) BLOCK DIAGRAM VDD QOP QI QOM AON Demodulator & Comparator OUT RFIP VDD AGC Amplifier RFIM Power Supply/Biasing VDD VSS PDN AGC DEC 1 (9) DA6180.001 27 December, 2006 MAS6180 PAD LAYOUT VSS pad bonded first! 1070 µm VDD QOP QOM QI AGC OUT VSS RFIM RFIP PDN AON DEC MAS6180Ax, x = 1, 2, 5 DIE size = 1.07 mm x 1.37 mm; PAD size = 80 µm x 80 µm Note: Because the substrate of the die is internally connected to VSS, the die has to be connected to VSS or left floating. Please make sure that VSS is the first pad to be bonded. Pick-and-place and all component assembly are recommended to be performed in ESD protected area. Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die. Pad Identification Power Supply Voltage Positive Quartz Filter Output for Crystal Negative Quartz Filter Output for Crystal Quartz Filter Input for Crystal and External Compensation Capacitor AGC Capacitor Receiver Output Demodulator Capacitor AGC On Control Power Down Positive Receiver Input Negative Receiver Input Power Supply Ground Name VDD QOP QOM QI AGC OUT DEC AON PDN RFIP RFIM VSS X-coordinate 152 µm 152 µm 152 µm 152 µm 152 µm 152 µm 915 µm 915 µm 915 µm 915 µm 915 µm 915 µm Y-coordinate 1137 µm 1002 µm 815 µm 629 µm 443 µm 257 µm 265 µm 451 µm 636 µm 824 µm 1010 µm 1158 µm Note 1370 µm 1 2 3 4 5 5 Notes: 1) External crystal compensation capacitor pin QOM is connected only in MAS6180A5 version. It is left unconnected in MAS6180A1 and A2 versions which have internal compensation capacitor. 2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |IOUT| > 5 µA - at power down the output is pulled to VSS (pull down switch) 3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up with current < 1 µA which is switched off at power down 4) PDN = VSS means receiver on; PDN = VDD means receiver off Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up (PDN=VSS) i.e. at the falling edge of PDN signal. 5) Receiver inputs RFIP and RFIM have both 600 kΩ biasing resistors towards VDD 2 (9) DA6180.001 27 December, 2006 6) ABSOLUTE MAXIMUM RATINGS All Voltages with Respect to Ground Parameter Supply Voltage Input Voltage ESD Rating Symbol VDD-VSS VIN VESD Conditions Min - 0.3 VSS-0.3 ±2 Max 5.5 VDD+0.3 Unit V V kV Latchup Current Limit ILUT For all pins, Human Body Model (HBM), ESD Association Standard Test Method ESD-STM5.11998, CESD = 100 pF, Rs = 1500 Ω), For all pins, test according to Micro Analog Systems specification ESQ0141. See note below. ±100 mA Operating Temperature Storage Temperature TOP TST -40 - 55 +85 +150 ° C ° C Stresses beyond those listed may cause permanent damage to the device. The device may not operate under these conditions, but it will not be destroyed. Note: In latchup testing the supply voltages are connected normally to the tested device. Then pulsed test current is fed to each input separately and device current consumption is observed. If the device current consumption increases suddenly due to test current pulses and the abnormally high current consumption continues after test current pulses are cut off then the device has gone to latch up. Current pulse is turned on for 10 ms and off for 20 ms. ELECTRICAL CHARACTERISTICS Operating Conditions: VDD = 1.5V, Temperature = 25° unless otherwise specified. C, Parameter Operating Voltage Current Consumption Symbol VDD IDD Conditions VDD=1.5 V, Vin=0 µVrms VDD=1.5 V, Vin=20 mVrms VDD=3.6 V, Vin=0 µVrms VDD=3.6 V, Vin=20 mVrms See note below. Min 1.10 40 24 Typ 55 40 58 43 Max 3.6 80 65 Unit V µA Stand-By Current Input Frequency Range Minimum Input Voltage Maximum Input Voltage Receiver Input Resistance Receiver Input Capacitance Input Levels |lIN| 5 µA - at power down the output is pulled to VSS (pull down switch) 4) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up with current < 1 µA which is switched off at power down 5) PDN = VSS means receiver on; PDN = VDD means receiver off - Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up (PDN=VSS) i.e. at the falling edge of PDN signal. 6) Receiver inputs RFIP and RFIM have both 600 kΩ biasing resistors towards VDD 8 (9) DA6180.001 27 December, 2006 ORDERING INFORMATION Product Code MAS6180A1TC00 Product Single Band AM-Receiver IC with Differential Input Single Band AM-Receiver IC with Differential Input Single Band AM-Receiver IC with Differential Input Description EWS-tested wafer, diameter 150 mm, thickness 400 µm. EWS-tested wafer, diameter 150 mm, thickness 400 µm. EWS-tested wafer, diameter 150 mm, thickness 400 µm. Capacitance Option CC = 0.75 pF CC = 1.3 pF External compensation capacitor MAS6180A2TC00 MAS6180A5TC00 Contact Micro Analog Systems Oy for other wafer thickness options. N The formation of product code An example for MAS6180A1TC00: MAS6180 A 1 Product Design Capacitance option: name version CC = 0.75 pF TC Package type: TC = 400 µm thick EWS tested wafer 00 Delivery format: 00 = bare wafer 05 = dies on tray LOCAL DISTRIBUTOR MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kamreerintie 2, P.O. Box 51 FIN-02771 Espoo, FINLAND Tel. +358 9 80 521 Fax +358 9 805 3213 http://www.mas-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. 9 (9)
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