MAS9116AASD08

DA9116.005 22 November, 2005 MAS9116 Stereo Digital Volume Control • • • • DESCRIPTION MAS9116 is a stereo volume control for audio systems, which require high output voltages (AC3). It has a 16-bit serial interface, which controls two audio channels. Simple serial interface allows microcontroller to control many MAS9116 chips on the same PCB board. “Clicking” between gain changes is eliminated by changing gain only when zero crossing has been detected from the signal. The use of external operational amplifier provides flexibility for the operating voltage, signal swing, noise floor and cost optimization. Signal Voltage up to ± 18V Two Independent Channels Use of Differential DACs Possible Serial Control Registers FEATURES • • • • • • Zero Detection for Gain Changes Gain Range +15.5db…-111.5dB 0.5 dB Step Size Mute Pin and Register Power On/Off Transient Suppression Signal Peak Level Comparator with Adjustable Reference APPLICATION • • High End Audio Systems Multichannel Audio Systems BLOCK DIAGRAM RIN R2 VIN R3 R1 RFO RMO RGND ZERO CROSSING PEAK DETECTOR VOUT DATA CCLK XCS XMUTE ZERO CROSSING 8 CONTROL DAC PEAK DETECTOR LIN R2 VIN R3 R1 LFO LMO LGND AGND AVCC DVCC DGND MAS9116 VOUT 1 (17) DA9116.005 22 November, 2005 PIN CONFIGURATIONS SO16 AVCC LMO LFO LIN LGND XCS DVCC XMUTE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 AGND RMO RFO RIN RGND DGND CCLK DATA QFN 4 x 5 LMO AVCC 1 2 LIN 3 LGND 4 5 6 XCS 7 LFO AGND RMO 19 RFO 18 17 RIN 16 RGND 15 14 13 DGND DATA CCLK 24 23 22 21 20 8 9 10 11 12 DVCC XMUTE PIN DESCRIPTION Pin Name AVCC LMO LFO* LIN* LGND XCS DVCC XMUTE DATA CCLK DGND RGND RIN* RFO* Pin SO16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin QFN 4x5 23 24 1 3 4 7 8 9 11 12 13 16 17 19 Type P AI AI AI AI DI P DI DIO DI G AI AI AI Function Power Supply, for Analog External Amplifier Negative Input (Left) Feedback Signal from External Amplifier Output (Left) Input, Left Channel Signal Ground, Left Channel Chip Select Input of Serial Interface Power Supply, for Digital Mute Input Data Input and Output of Serial Interface, Tristate Clock Input of Serial Interface Ground for Digital Signal Ground, Right Channel Input, Right Channel Feedback Signal from External Amplifier Output (Right) External Amplifier Negative Input (Right) Ground for Analog RMO 15 20 AI AGND 16 21 G *) Note: These Pins are only 300V HBM ESD protected 2 (18) DA9116.005 22 November, 2005 GENERAL DESCRIPTION Main features MAS9116 is a stereo digital volume control designed for audio systems. The levels of the left and right analog channels are set by the serial interface. Both channels can be programmed independently. Resistor values are decoded to 0.5 dB resolution by using internal multiplexers for a gain from –111.5 to +15.5 dB. The code for –112 dB activates mute for maximum attenuation. MAS9116 operates from single +5V supply and accepts input levels up to ±18V. Interfaces Control information is written into or read back from the internal register via the serial control port. Serial control port consists of a bi-directional pin for data (DATA), chip select pin (XCS) and control clock (CCLK) and supports the serial communication protocol. All control instructions require two bytes of data. To shift the data in CCLK must be pulsed 16 times when XCS is low. The data is shifted into the serial input register on the rising edges of CCLK pulses. The first 8 bits contain address information. The second byte contains the control word. XCS must return to high after the second byte. That is, after the 16th CCLK XCS must be returned to high. See the timing diagram on page 11. The same process takes place for reading the information. XCS will remain low for next 16 CCLK pulses. The data is shifted out on the falling edges of CCLK. When XCS is high, the DATA pin is in high impedance state, which enables DATA pins of other devices to be multiplexed together. On the PCB board the same DATA and CCLK lines can be directed to every MAS9116 chip. If the XCSpin is not active (low), DATA-pin of that chip is in high-impedance state. This allows using a simple PCB board for multichannel audio systems. Operating modes W hen power is first applied, power-on reset initializes control registers and sets MAS9116 into mute state. The activation of the device requires that XMUTE pin is high and a control byte with a greater than the default value is written in the gain register. It is possible to return to the mute stage either by setting XMUTE pin low or writing zero (00hex) to the gain register. The device has special test register which is used only for internal testing of the device. It is strongly 3 (18) recommended not to change the initial test register value (00hex) in normal operation. For device testing XMUTE pin is bidirectional. When the test register bit 1 is high, XMUTE pin is output pin. Internal signals can be directed to the pin. Note: In this state the analog output is muted and new gain values cannot be written into the gain register. Changing the gain of the channel W hen new gain value is written into the gain register the chip will activate zero crossing and delay generator for the selected channel. MAS9116 will wait until rising edge zero crossing is detected in the input signal to ensure that there is no audible click from the output of amplifier when gain is changed. LIN is the input line for the left channel and RIN for the right channel. If there are no zero crossings in the signal, the gain is changed after typical 18ms delay, since then the delay generator will provide about 100ns pulse forcing the new value to be latched. The delay generator´s delay has variation but it is guaranteed that the delay is no longer than 50ms. If new gain value has been written before zero crossing or delay generator´s delay have occured the previous gain value is overwritten, so the previous value is not latched to the output. If it is desired that each gain value will be latched to the output there should be minimum 50ms delay between each gain value writings. Programming both gain registers at the same time sets gain values first to the right channel and then to the left channel. Programming gain into left and right channel using separate commands causes gain values to be set in the same order as the programming. If no zero crossings occur in either channel, the firstly written channel´s gain is changed after first channel´s delay generator´s delay has passed. Only after that second channel´s delay generator is started. In these conditions the first channel gain is set after maximum 50ms delay but second channel is set after maximum 50ms+50ms = 100ms delay. To guarantee that each written gain value will be set in all conditions the maximum programming rate for both channel gains separately is thus 1/100ms = 10 Hz. DA9116.005 22 November, 2005 GENERAL DESCRIPTION Peak Level Detection MAS9116 has an 8-bit digital-to-analog converter (DAC) used for monitoring the peak level of the signal. The reference value is programmed via the serial interface. The reference value VREF is calculated from VREF=(0.16+0.0133*CODE)*VDD, where CODE is decimal value of the control byte (0..255) and VDD is MAS9116 supply voltage value. With nominal 5 V supply voltage the reference value is VREF=0.8V+66.5mV*CODE. When positive peak signal level at output exceeds this value, comparator signal sets bits 0 and 1 of the status register. The register contents stay high until the peak register has been read. 4 (18) DA9116.005 22 November, 2005 REGISTER DESCRIPTION Register Peak Detector Status CR4 7 X 6 1 5 0 Address Byte 4 1 3 1 2 R/W 1 X 0 X Data Byte msb…lsb Output code 00000000 00000001 00000010 00000011 Input code 11111111 11111110 11111101 • • 00000010 00000001 00000000 Function Peak Detector Reference CR3 X 1 1 0 0 R/W X X Left Channel Gain CR2 X 1 1 0 1 R/W X X Right Channel Gain CR1 X 1 1 1 0 R/W X X Test, CR5 Both Channel Gains X X 1 1 1 0 1 0 1 1 R/W W X X X X No overload Right overload Left overload Both overload DAC output VREF(255) VREF(254) VREF(253) • • VREF(2) VREF(1) VREF(0) Note 1 Input code Gain dB 11111111 +15.5 +15.0 11111110 +14.5 11111101 • • • • 11100000 0.0 00000010 -111.0 00000001 -111.5 00000000 mute Input code Gain dB 11111111 +15.5 +15.0 11111110 11111101 +14.5 • • • • 11100000 0.0 00000010 -111.0 00000001 -111.5 00000000 mute Reserved Write to both gain registers Note 1. Reference voltage is calculated from VREF(CODE)=(0.16+0.0133*CODE)*VDD Address byte bits: • Bit 2 is read/write bit (1=read, 0=write). • X is don’t care, recommended high for low power. Data byte bits: • All registers get their default value 00Hex except CR3 which gets FFHex during power-on reset. • Default value for all bits is zero (00hex). 5 (18) DA9116.005 22 November, 2005 TEST REGISTER CR5 DESCRIPTION Note: Test register is intended only for internal testing of the device and not supposed to be used in normal operation. It is strongly recommended not to change initial test register value (00hex). XMUTE pin is output pin when bit 1 is set in register CR5. Bits 2, 3 and 4 select different internal signals. In test phase those signals can be seen via XMUTE pin. Condition Data Byte bits Function XMUTE=in Test, XMUTE=in Test, XMUTE=out Test, XMUTE=out Test, XMUTE=out Test, XMUTE=out Test, XMUTE=out Test, XMUTE=out Test, XMUTE=out Test, XMUTE=out 7 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 1 1 1 1 3 0 0 0 0 1 1 0 0 1 1 2 0 0 0 1 0 1 0 1 0 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 Normal operation Force latch, note 1 left delay generator left peak detector left zero crossing left enable for zero crossing and delay generator right delay generator right peak detector right zero crossing right enable for zero crossing and delay generator Note 1. Forces the new gain value to be latched to resistor network without waiting for zero crossing or delay generator. LSB bit has to be returned to 0 before next gain value can be latched. When force latch is used, both channels are latched with the same value. ABSOLUTE MAXIMUM RATINGS All voltages with respect to ground. Parameter Signal Voltage Positive Supply Voltage All other pins Storage Temperature Operating Temperature ESD (HBM) pins 3, 4, 13 and 14 ESD (HBM) all other pins Symbol RIN, RFO, LIN, LFO AVCC, DVCC TS TA Conditions Min -20 -0.5 -0.3 -55 -40 300 2000 Max +20 +6.0 AVCC +0.3 +125 +85 Unit V V o o C C V V Stresses beyond those listed may cause permanent damage to the device. The device may not operate under these conditions, but it will not be destroyed. RECOMMENDED OPERATION CONDITIONS (AVCC=+5.0 V, AVSS=0 V, TA=+25oC unless otherwise noted) Parameter Signal Voltage Positive Supply Voltage Negative Supply Voltage Signal Grounds Operating Temperature Symbol RIN, RFO, LIN, LFO AVCC,DVCC AGND,DGND LGND,RGND TA Conditions Min -18 4.5 Typ Max +18 Unit V V V V 5 0 0 5.5 -20 +25 +60 o C 6 (18) DA9116.005 22 November, 2005 ANALOG CHARACTERISTICS N Analog Inputs/Outputs (AVCC=+5.0 V, AVSS=0 V, TA=+25oC unless otherwise noted) Parameter Input Resistance Input Capacitance Input offset voltage Symbol RIN CIN VIH Conditions For any gain For any gain External OP277 amplifier, Gain = 15.5 dB Note 1 From AVCC From AGND From AVCC Min 7 Typ 10 2 0.23 Max 13 1 Unit kΩ pF mV Supply current Supply current Power supply rejection ratio1 IVCC IGND PSRR 2.5 2.5 80 5 5 mA mA dB Note 1. Output offset voltage depends on external opamp and selected gain. Low input offset voltage and input bias current opamp is recommended to be used for minimum output offset. OP277 has excellent offset characteristics. Also OP1177 and AD8610 offer good offset performance. N Gain Control (AVCC=+5.0 V, AVSS=0 V, TA=+25oC unless otherwise noted) Parameter Gain range Step size Gain error1 Gain match error Mute attenuation 1 Symbol G D DE ME MATT Conditions Min -111.5 Typ Max +15.5 Unit dB dB dB dB dB 0.5 Lowest gains guaranteed by design, not tested in production. Between channels 113 0.5 0.2 N Audio Performance Parameter Noise1 (AVCC=+5.0 V, AVSS=0 V, TA=+25oC unless otherwise noted) Symbol N Total harmonic distortion plus noise Dynamic range 1 Crosstalk 1 THDN Conditions Vin=0 Vout with OP275, A-weighting -gain=0dB -gain=-60dB -gain=mute Vin=6Vrms, gain=1, Vout with OP275, 0…20kHz Between channels, gain=1, fin=1kHz Min Typ Max Unit 13 4 2.5 0.01 µVrms % DR CR 120 -100 130 -110 dB dB 1 Guaranteed by design 7 (18) DA9116.005 22 November, 2005 ANALOG CHARACTERISTICS Figure 1 and 2. THD+N vs. input amplitude at 1 kHz, Gain 0 dB. Lower trace is THD+N of Audio Precision System One generator Figure 3. THD+N vs. input amplitude at 1 kHz, Gain +15.5 dB Figure 4. Frequency response, 2.65 Vrms input Figure 5. Frequency response, 0.265 Vrms (-20 dB) input Figure 6. THD+N vs. frequency load = 100k , 600 , 300 8 (18) DA9116.005 22 November, 2005 ANALOG CHARACTERISTICS Figure 7. THD+N vs. frequency levels of 1, 2 and 2.8 Vrms Figure 8. Spectrum, input amplitude 1 Vrms, gain -20 dB Figure 9. Spectrum, input amplitude 1 Vrms, gain 0 dB Figure 10. Spectrum, input amplitude 1 Vrms, gain +15.5 dB 9 (18) DA9116.005 22 November, 2005 DIGITAL CHARACTERISTICS N Digital Inputs/Outputs (AVCC=+5.0 V, AVSS=0 V, TA=+25oC unless otherwise noted) Parameter Input low voltage Input high voltage Output low voltage Output high voltage Symbol VIL VIH VOL VOH Conditions All digital inputs, DC All digital inputs, DC All digital outputs, IL=2mA All digital outputs, IH=2mA Min Typ Max 0.3* DVCC Unit V V 0.7* DVCC 0.4 DVCC0.4 V V N Serial Interface Timing (AVCC=+5.0 V, AVSS=0 V, TA=+25oC unless otherwise noted) Parameter Frequency of CCLK Period of CCLK high Period of CCLK low Rise time of CCLK Fall time of CCLK Hold time, CCLK high to XCS low Setup time, XCS low to CCLK high Setup time, valid CI to CCLK high Hold time, CCLK high to invalid CI Delay time, CCLK low to valid CI Delay time, XCS high or 8th CCLK low to invalid CI th Hold time, 16 CCLK high to XCS high Setup time, XCS high to CCLK high Symbol FCCLK TWHC TWLC TRC TFC THCHS TSSLCH TSDCH THCHD TDCLD TDSZ THLCHS TSSHCH Conditions Min Typ Max 1 Unit MHz ns ns Measured from VIH to VIH Measured from VIL to VIL Measured from VIL to VIH Measured from VIH to VIL 500 500 100 100 20 100 100 100 ns ns ns ns ns ns Load=100pF Load=3.3kΩ 20 200 200 200 200 ns ns ns ns 10 (18) DA9116.005 22 November, 2005 Serial Interface Timing TWHC TWLC CCLK THCSH XCS THCHD TSDCH DATA (IN) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 TDSZ 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 TRC 12 TFC 13 14 15 16 TSSHCH TSSLCH THLCHS TDCLD DATA (OUT) ADDRESS BYTE 7 6 5 4 DATA BYTE APPLICATION INFORMATION Power supply connection and decoupling To get the best performance of the chip all digital activities should be avoided during analog signal processing. Important: Analog (AVDD) and digital (DVDD) supply voltage pins should be always connected directly together to keep them in the same voltage potential. No resistor is allowed in connection between AVDD and DVDD (see supply voltage connection circuit in the Application Note 1 on the next page). Otherwise possible voltage difference Opamp produced output offset voltage Opamp non-idealities in input offset voltage and in input bias current both produce offset voltage to the output. Since this offset voltage is gain dependent the gain change step can produce dc voltage steps to the output. To achieve the best audio performance it is recommended to use opamps which have both low input offset voltage and low Manufacturer Analog Devices Analog Devices Analog Devices Texas Instruments (BurrBrown) Linear On-Semi, ST Microelectronics input bias current characteristics. Burr-Brown OP277 has excellent offset and bias and no trimming is needed. Also Analog Devices OP1177 and AD8610 offer very good offset performance. See table below for these and other recommended op-amps. could trigger latch-up phenomenom which can damage the device. Due to the same reason also the digital control input voltages should not exceed supply and ground voltages as specified in absolute maximum rating specifications on page 6. These requirements are valid also during the startup when supply voltages are applied. Low noise supply voltages should be used for high quality audio. Supply decoupling capacitors must be located as close to MAS9116 as possible. Part Number OP275 OP1177 AD8610 OP277 LT1793 MC33078 Typical Output Offset at Maximum Gain (mV) 8.5 0.51 1.49 0.23 18.5 28.4 11 (18) DA9116.005 22 November, 2005 APPLICATION INFORMATION Application Note 1 Typical application Connect signal ground and opamp +input together on PCB RF LIN AUDIO SOURCE LGND RIN LFO LMO LEFT CHANNEL RF RIN AUDIO SOURCE RGND RIN RFO + -18V +18V +18V + -18V RMO RIGHT CHANNEL MAS9116 +5VDC MICROCONTROLLER XCS DATA CCLK XMUTE AVCC DVCC 220nF AGND DGND + 10uF Application note 2 Configuration for balanced output DAC (one channel) RFO RIN +18V RMO + 2k -18V + -18V 2k -18V 2k 2k +18V RGND MAS9116 +18V + LGND LFO LIN LMO - 12 (18) DA9116.005 22 November, 2005 APPLICATION INFORMATION Application Note 3 Single supply voltage circuit below is based on signal AC coupling and biasing output opamp in the middle point of supply voltages. Note that only right channel circuit is presented. The left channel circuit would be exactly the same. The component values have been chosen to limit lower corner frequency to about 20 Hz. AVCC DVCC + 5V supply 2uF MAS9116 (Right Channel) RFO 1MΩ 1MΩ IN 2uF RIN RMO 100nF AC RGND LGND DGND AGND 1MΩ 10kΩ + 2uF OUT (inverted) 13 (18) DA9116.005 22 November, 2005 SO-16 PACKAGE OUTLINE 16 LEAD SO OUTLINE (300 MIL BODY) 0.33 x 45° 5° TYP. 5°TYP 0.25 RAD. MIN. 0.94 1.12 1.27 5° TYP. TYP. 0.36 0.48 0-0.13 RAD. 2.36 2.64 10.10 10.50 10.00 10.65 PIN 1 SEATING PLANE 5° TYP. 5° TYP. . 0.86 TYP ALL MEASUREMENTS IN mm All dimensions are in accordance with JEDEC standard MS-013. 7.40 7.60 0.10 0.30 14 (18) DA9116.005 22 November, 2005 QFN 4x5 24ld PACKAGE OUTLINE D D/2 PIN 1 MARK AREA E/2 TOP VIEW A A3 A1 D2 D2/2 L E2/2 SIDE VIEW SEATING PLANE BOTTOM VIEW SHAPE OF PIN #1 IDENTIFICATION IS OPTIONAL EXPOSED PAD e b Symbol A A1 A3 b D D2 E E2 e L Min 0.80 0 0.15 0.18 Nom Max E2 Unit mm mm mm mm mm mm mm mm mm mm PACKAGE DIMENSIONS 0.90 1.0 0.02 0.05 0.20 0.25 0.25 0.30 4.00 BSC 2.0 2.15 2.25 5.00 BSC 3.0 3.15 3.25 0.50 BSC 0.45 0.55 0.75 Dimensions do not include mold or interlead flash, protrusions or gate burrs. All measurements according to JEDEC standard MO-187 15 (18) DA9116.005 22 November, 2005 SOLDERING INFORMATION N For Lead-Free / Green QFN 4mm x 5mm Resistance to Soldering Heat Maximum Temperature Maximum Number of Reflow Cycles Reflow profile Lead Finish According to RSH test IEC 68-2-58/20 260°C 3 Thermal profile parameters stated in IPC/JEDEC J-STD-020 should not be exceeded. http://www.jedec.org Solder plate 7.62 - 25.4 µm, material Matte Tin EMBOSSED TAPE SPECIFICATIONS, QFN 4x5 PACKAGE P2 PO P1 D0 X E T W F B0 R 0.5 typ A0 User Direction of Feed X K0 Dimension Ao Bo Do E F Ko Po P1 P2 T W Min/Max 4.30 ±0.10 5.30 ±0.10 1.50 +0.1/-0.0 1.75 5.50 ±0.5 1.10 ±0.10 4.0 8.0 ±0.10 2.0 ±0.05 0.3 ±0.05 12.00 ±0.3 All dimensions in millimeters Unit mm mm mm mm mm mm mm mm mm mm mm 16 (18) DA9116.005 22 November, 2005 REEL SPECIFICATIONS W2 A D B Tape Slot for Tape Start C N W1 1000 Components on Each Reel Reel Material: Conductive, Plastic Antistatic or Static Dissipative Carrier Tape Material: Conductive Cover Tape Material: Static Dissipative Carrier Tape Cover Tape End Start Trailer Components Leader Dimension A B C D N W 1 (measured at hub) W 2 (measured at hub) Trailer Leader Min 1.5 12.80 20.2 50 8.4 160 390, of which minimum 160 mm of empty carrier tape sealed with cover tape Max 178 13.50 Unit mm mm mm mm mm mm mm mm mm 9.9 14.4 17 (18) DA9116.005 22 November, 2005 ORDERING INFORMATION Product Code MAS9116ASBA-T MAS9116ASBA Product MAS9116 MAS9116 Package 16-pin Plastic SOIC 16-pin Plastic SOIC Quantity 1000 pcs/reel in MBB 47 pcs/tube Comments MBB=Moisture Barrier Bag MSB0091A Bake recommendation for surface mounted devices MBB=Moisture Barrier Bag MSB0091A Bake recommendation for surface mounted devices MBB=Moisture Barrier Bag MAS9116AASD06 MAS9116AASD08 MAS9116 MAS9116 16-pin Plastic SOIC, RoHS compliant 16-pin Plastic SOIC, RoHS compliant 1000 pcs/reel in MBB 47 pcs/tube MAS9116AAHV06 MAS9116 24-pin QFN 4x5, RoHS compliant 1000 pcs/reel LOCAL DISTRIBUTOR MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kamreerintie 2, P.O. Box 51 FIN-02771 Espoo, FINLAND Tel. +358 9 80 521 Fax +358 9 805 3213 http://www.mas-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. 18 (18)