MAS9180A1UA06

DA9180.004 15 September, 2005 MAS9180 • Single Band Receiver IC • High Sensitivity • Very Low Power Consumption • Wide Supply Voltage Range • Power Down Control • Control for AGC On • High Selectivity by Crystal Filter • Fast Startup Feature DESCRIPTION The MAS9180 AM-Receiver chip is a highly sensitive, simple to use AM receiver specially intended to receive time signals in the frequency range from 40 kHz to 100 kHz. Only a few external components are required for time signal receiver. The circuit has preamplifier, wide range automatic gain control, demodulator and output comparator built in. The output signal can be processed directly by an additional digital circuitry to extract the data from the received signal. The control for AGC (automatic gain control) can be used to switch AGC on or off if necessary. MAS9180 has both differential and asymmetric input options and also options for compensating shunt capacitances of different crystals (See ordering information on page 15). AM Receiver IC FEATURES • • • • • • • • • • • • Single Band Receiver IC Highly Sensitive AM Receiver, 0.4 µVRMS typ. W ide Supply Voltage Range from 1.1 V to 5.5 V Very Low Power Consumption Power Down Control Fast Startup Only a Few External Components Necessary Control for AGC On W ide Frequency Range from 40 kHz to 100 kHz High Selectivity by Quartz Crystal Filter Both Differential and Asymmetric Input Versions Crystal Compensation Capacitance Options APPLICATIONS • Single Band Time Signal Receiver WWVB (USA), JJY (Japan), DCF77 (Germany), MSF (UK), HGB (Switzerland) and BPC (China) BLOCK DIAGRAM QOP RFIP AGC Amplifier QI QOM AON Demodulator & Comparator OUT RFIM Power Supply/Biasing VDD VSS PDN AGC DEC 1 (15) DA9180.004 15 September, 2005 MAS9180 PAD LAYOUT MAS9180Ax, x = 1..5 differential input, B..F asymmetric input VDD QOP QOM QI AGC OUT VSS RFIP PDN AON DEC 1474 µm DIE size = 1.47 x 1.46 mm; PAD size = 80 x 80 µm Note: Because the substrate of the die is internally connected to VDD, the die has to be connected to VDD or left floating. Please make sure that VDD is the first pad to be bonded. Pick-and-place and all component assembly are recommended to be performed in ESD protected area. Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die. Pad Identification Power Supply Voltage Positive Quartz Filter Output for Crystal Negative Quartz Filter Output for Crystal Quartz Filter Input for Crystal and External Compensation Capacitor AGC Capacitor Receiver Output Demodulator Capacitor AGC On Control Power Down Positive Receiver Input Negative Receiver Input Power Supply Ground Name VDD QOP QOM QI AGC OUT DEC AON PDN RFIP RFIM VSS X-coordinate 174 µm 174 µm 174 µm 174 µm 174 µm 175 µm 1295 µm 1295 µm 1295 µm 1295 µm 1295 µm 1282 µm Y-coordinate 1262 µm 1057 µm 854 µm 648 µm 444 µm 240 µm 225 µm 425 µm 624 µm 825 µm 1039 µm 1200 µm Note 1456 µm RFIM 4 1 2 3 5 5 Notes: 1) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |IOUT| > 5 µA - at power down the output is pulled to VSS (pull down switch) 2) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up with current < 1 µA which is switched off at power down 3) PDN = VSS means receiver on; PDN = VDD means receiver off Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up (PDN=VSS) i.e. at the falling edge of PDN signal. 4) External crystal compensation capacitor pin QOM is connected only in MAS9190A5 and AF versions. It is left unconnected in MAS9180A1 and AB..E versions which have internal compensation capacitor. 5) Differential input versions A1..A5 have 600 kΩ biasing MOSFET-transistors towards ground from both receiver inputs RFIP and RFIM. Asymmetric input versions AB..AF have input pin RFIM unconnected. 2 (15) DA9180.004 15 September, 2005 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Input Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VDD-VSS VIN PMAX TOP TST Conditions Min -0.3 VSS-0.3 -40 -55 Max 6 VDD+0.3 100 +85 +150 Unit V V mW o C o C ELECTRICAL CHARACTERISTICS Operating Conditions: VDD = 1.4V, Temperature = 25°C Parameter Operating Voltage Current Consumption Symbol VDD IDD Conditions VDD=1.4 V, Vin=0 µVrms VDD=1.4 V, Vin=20 mVrms VDD=3.6 V, Vin=0 µVrms VDD=3.6 V, Vin=20 mVrms Min 1.10 Typ 64 37 67 40 Max 5.5 Unit V µA 31 27 40 Stand-By Current Input Frequency Range Minimum Input Voltage Maximum Input Voltage Receiver Input Resistance Receiver Input Capacitance Receiver Input Resistance Receiver Input Capacitance Input Levels |lIN| 5 µA - at power down the output is pulled to VSS (pull down switch) 3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up with current < 1 µA which is switched off at power down 4) PDN = VSS means receiver on; PDN = VDD means receiver off - Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up (PDN=VSS) i.e. at the falling edge of PDN signal. 5) External crystal compensation capacitor pin QOM is connected only in MAS9190A5 and AF versions. It is left unconnected in MAS9180A1 and AB..E versions which have internal compensation capacitor. 6) Differential input versions A1..A5 have 600 kΩ biasing MOSFET-transistors towards ground from both receiver inputs RFIP and RFIM. Asymmetric input versions AB..AF have input pin RFIM unconnected. 9 (15) DA9180.004 15 September, 2005 PIN CONFIGURATION & TOP MARKING FOR PLASTIC TSSOP-16 PACKAGE VDD QOP QOM NC QI AGC NC OUT VSS RFIM NC RFIP NC PDN AON DEC 9180Az YYWW Top Marking Definitions: z = Version Number YYWW = Year Week PIN DESCRIPTION Pin Name VDD QOP QOM NC QI AGC NC OUT DEC AON PDN NC RFIP NC RFIM VSS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type P AO AO Function Positive Power Supply Positive Quartz Filter Output for Crystal Negative Quartz Filter Output for External Compensation Capacitor or Second Crystal Quartz Filter Input for Crystal and External Compensation Capacitor AGC Capacitor Receiver Output Demodulator Capacitor AGC On Control Power Down Input Positive Receiver Input Negative Receiver Input Power Supply Ground 2 3 4 6 6 Note 5 1 AI AO DO AO DI DI AI AI G A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected Notes: 1) Pin 4 between quartz crystal filter pins must be connected to VSS to eliminate package leadframe parasitic capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also recommended to be connected to VSS to minimize noise coupling. 2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |IOUT| > 5 µA - at power down the output is pulled to VSS (pull down switch) 3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up (to AGC on) with current < 1 µA which is switched off at power down 4) PDN = VSS means receiver on; PDN = VDD means receiver off - Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up (PDN=VSS) i.e. at the falling edge of PDN signal. 5) External crystal compensation capacitor pin QOM is connected only in MAS9190A5 and AF versions. It is left unconnected in MAS9180A1 and AB..E versions which have internal compensation capacitor. 6) Differential input versions A1..A5 have 600 kΩ biasing MOSFET-transistors towards ground from both receiver inputs RFIP and RFIM. Asymmetric input versions AB..AF have input pin RFIM unconnected. 10 (15) DA9180.004 15 September, 2005 PACKAGE (TSSOP16) OUTLINES C B A D Seating Plane F G H E O Pin 1 Detail A B B L I I1 K P Section B-B J1 J M N Detail A Dimension A B C D E F G H I I1 J J1 K L M (The length of a terminal for soldering to a substrate) N O P Min 4.30 0.05 0.19 0.18 0.09 0.09 0.19 0.19 0° 0.24 0.50 6.40 BSC 5.00 BSC Max 4.50 0.15 1.10 0.30 0.28 0.20 0.16 0.30 0.25 8° 0.26 0.75 Unit mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm 0.65 BSC 1.00 REF 12° 12° Dimensions do not include mold flash, protrusions, or gate burrs. All dimensions are in accordance with JEDEC standard MO-153. 11 (15) DA9180.004 15 September, 2005 SOLDERING INFORMATION N For Eutectic Sn/Pb TSSOP-16 Resistance to Soldering Heat Maximum Temperature Maximum Number of Reflow Cycles Reflow profile Seating Plane Co-planarity Lead Finish N For Pb-Free, RoHS Compliant TSSOP-16 Resistance to Soldering Heat Maximum Temperature Maximum Number of Reflow Cycles Reflow profile Seating Plane Co-planarity Lead Finish According to RSH test IEC 68-2-58/20 260°C 3 Thermal profile parameters stated in IPC/JEDEC J-STD-020 should not be exceeded. http://www.jedec.org max 0.08 mm Solder plate 7.62 - 25.4 µm, material Matte Tin According to RSH test IEC 68-2-58/20 2*220°C 240°C 2 Thermal profile parameters stated in JESD22-A113 should not be exceeded. http://www.jedec.org max 0.08 mm Solder plate 7.62 - 25.4 µm, material Sn 85% Pb 15% 12 (15) DA9180.004 15 September, 2005 EMBOSSED TAPE SPECIFICATIONS Tape Feed Direction P0 D0 P2 A E1 F1 W D1 A P A0 Tape Feed Direction T Section A - A B0 S1 K0 Dimension A0 B0 D0 D1 E1 F1 K0 P P0 P2 S1 T W Min 6.50 5.20 1.50 1.65 7.20 1.20 11.90 1.95 0.6 0.25 11.70 Pin 1 Designator Max 6.70 5.40 1.85 7.30 1.40 12.10 2.05 0.35 12.30 Unit mm mm mm mm mm mm mm mm mm mm mm mm mm 1.50 +0.10 / -0.00 4.0 13 (15) DA9180.004 15 September, 2005 REEL SPECIFICATIONS W2 A D B Tape Slot for Tape Start C N W1 2000 Components on Each Reel Reel Material: Conductive, Plastic Antistatic or Static Dissipative Carrier Tape Material: Conductive Cover Tape Material: Static Dissipative Carrier Tape Cover Tape End Start Trailer Dimension A B C D N W1 (measured at hub) W2 (measured at hub) Trailer Leader Min Components Max 330 13.50 14.4 18.4 160 390, of which minimum 160 mm of empty carrier tape sealed with cover tape Leader Unit mm mm mm mm mm mm mm mm mm 1.5 12.80 20.2 50 12.4 W eight 1500 g 14 (15) DA9180.004 15 September, 2005 ORDERING INFORMATION Product Code MAS9180A1TC00 MAS9180A5TC00 MAS9180A1UA06 MAS9180A1UC06 MAS9180ABTC00 MAS9180ACTC00 MAS9180ADTC00 MAS9180AETC00 MAS9180AFTC00 Product Single Band AM-Receiver IC with Differential Input Single Band AM-Receiver IC with Differential Input Single Band AM-Receiver IC with Differential Input Single Band AM-Receiver IC with Differential Input Single Band AM-Receiver IC with Asymmetric Input Single Band AM-Receiver IC with Asymmetric Input Single Band AM-Receiver IC with Asymmetric Input Single Band AM-Receiver IC with Asymmetric Input Single Band AM-Receiver IC with Asymmetric Input Description EWS-tested wafer, Thickness 400 µm. EWS-tested wafer, Thickness 400 µm. TSSOP-16, Tape & Reel TSSOP-16, Pb-free, RoHS compliant, Tape & Reel EWS-tested wafer, Thickness 400 µm. EWS-tested wafer, Thickness 400 µm. EWS-tested wafer, Thickness 400 µm. EWS-tested wafer, Thickness 400 µm. EWS-tested wafer, Thickness 400 µm. Capacitance Option CC = 0.75 pF External compensation capacitor CC = 0.75 pF CC = 0.75 pF CC = 0.75 pF CC = 1.25 pF CC = 1.5 pF CC = 2.5 pF External compensation capacitor Contact Micro Analog Systems Oy for other wafer thickness options. N The formation of product code An example for MAS9180A1TC00: MAS9180 A 1 Product Design Input type and name version capacitance option: Differential input and CC = 0.75 pF TC Package type: TC = 400 µm thick EWS tested wafer UA = TSSOP16 (Pb/Sn) UC = TSSOP16 (Pb-free, RoHS compliant) 00 Delivery format: 00 = bare wafer 06 = Tape & Reel LOCAL DISTRIBUTOR MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kamreerintie 2, P.O. Box 51 FIN-02771 Espoo, FINLAND Tel. +358 9 80 521 Fax +358 9 805 3213 http://www.mas-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. 15 (15)