MAS9279A5TG00

DA9279.003 13 July 2006 MAS9279 IC FOR 10.00 – 52.00 MHz VCTCXO • • • • • • • DESCRIPTION The MAS9279 is an integrated circuit well suited to build high end VCTCXO for telecommunication. The trimming is done through a serial bus and the calibration information is stored in an internal PROM. This means no rework for trimming is needed. To build a VCTCXO only crystal is required in addition to MAS9279. The compensation method is fully analog, working continuously without generating any steps or other interference. Fourth Order Compensation Frequency Stability +/- 0.3 ppm Wide Frequency Range Very Low Phase Noise Low Voltage Minimum Operating Temperature –40 ° C Tri State CMOS Output FEATURES • • • • • • • Very small size Minimal current consumption W ide operating temperature range Very low phase noise Programmable VC-sensitivity Minimum operating temperature –40 ° C Oscillator frequency output f0/2 version available APPLICATIONS • • VCTCXO for high end telecommunications systems TCXO for high end telecommunication systems BLOCK DIAGRAM DA CLK PV Fourth Term CUB INF SENS LIN 4 f(T) 5 3 8 TE1 Σ T Vref TMux TE2 f(T) VC CDAC1 6 4 VDD CDAC2 OUT VSS X2 X1 1 (10) DA9279.003 13 July 2006 PIN DESCRIPTION Pin Description Power Supply Voltage Programming Input Serial Bus Clock Input Serial Bus Data Input Temperature Output Test Multiplexer Output Voltage Control Input Crystal Oscillator Output Crystal/Varactor Oscillator Input Power Supply Ground Buffer Output Symbol VDD PV CLK DA TE1 TE2 VC X1 X2 VSS OUT x-coordinate 149 561 1000 1565 2024 2016 147 1261 518 1549 1810 y-coordinate 1340 1340 1340 1340 1340 140 140 140 140 140 140 3 3 Note Note: Because the substrate of the die is internally connected to GND, the die has to be connected to GND or left floating. Make sure that GND is the first pad to be bonded. Pick-and-place and all component assembly are recommended to be performed in ESD protected area. Note: Pad coordinates are measured from the left bottom corner of the chip to the center of the pads. The coordinates may vary depending on sawing width and location, however, distances between pads are accurate. Note 3: Valid for MAS9279A1, A3, A5 and A7. In MAS9279A2, A4, A6 and A8 TE1 and TE2 pins have been swapped. ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Input Pin Voltage Power Dissipation Storage Temperature ESD Rating; HBM Symbol VDD - VSS PMAX TST Min -0.3 VSS -0.3 -55 Max 6.0 VDD + 0.3 100 150 2 Unit V V mW o C kV Note 1) 2) Note 1: Not valid for programming pin PV Note 2: In X1 and X2 pins maximum ESD rating is 1.5kV RECOMMENDED OPERATION CONDITIONS Parameter Supply Voltage Supply Current Operating Temperature Crystal Pulling Sensitivity Crystal Pulling Sensitivity Crystal Load Capacitance Crystal Load Capacitance Symbol VDD ICC TOP S S CL CL Conditions Vdd = 3.3 Volt -40 24 28 Vc = 1.2V Vc = 1.2V Min 2.7 Typ 3.3 6.0 28 33 8 10 Max 5.5 +85 35 38 Unit V mA o C ppm/pF ppm/pF pF pF Note 1 2 3 2 3 Note 1: At 26MHz crystal Note 2: MAS9279A1, MAS9279A3, MAS9279A5, MAS9279A7 Note 3: MAS9279A2, MAS9279A4, MAS9279A6, MAS9279A8 2 (10) DA9279.003 13 July 2006 ELECTRICAL CHARACTERISTICS (recommended operation conditions) Parameter Frequency Range Voltage Control Range Voltage Control Sensitivity Voltage Control Sensitivity Voltage Control Sensitivity Frequency vs. Supply Voltage Frequency vs. Load Change Output Voltage (10 pF, VDD 2.7 V) Output Voltage (10 pF, VDD 5.0 V) Rise and Fall Time (10 - 50 pF) Output Symmetry Compensation Range ± 1.0 ppm Compensation Range ± 0.75 ppm Compensation Range ± 0.3 ppm Compensation Range Linear Part Compensation Inflection Point Compensation Range Cubic Part Compensation CDAC1 (4 Bit) Compensation CDAC2 (6 Bit) Compensation CDAC1 (4 Bit) Compensation CDAC2 (6 Bit) Compensation CDAC1 (4 Bit) Compensation CDAC2 (6 Bit) Amplitude Start up Time Tri State Output Buffer ON State OFF State Note 1: In TCXO leave Vc floating Note 2: W ith 23 ppm/pF crystal Note 3: W ith 28 ppm/pF crystal. Note 4: W ith 33 ppm/pF crystal Note 5: VDD +/- 5% Symbol fo VC VCSENS VCSENS VCSENS dfo dfo Vout Vout Min 10.00 0 7.3 8.8 10.1 Typ Max 52.00 Vdd 10.4 13.4 14.5 ±0.2 ±0.2 Unit MHz V ppm/V ppm/V ppm/V ppm ppm Vpp Vpp ns % Note 1) 2) 3) 4) 5) 6) 2.3 4.5 3 45-55 TC TC TC a1 INF a3 CX1 CX2 CX1 CX2 CX1 CX2 TSTART DA -40 -20 10 -0.4 23 95 -1.5 -21 -2.6 -26 -3.0 -32 2 85 70 50 -0.1 31 2.4 27 2.1 32 2.6 36 o o o C C C 9) C 2) 7) 2) 8) 3) 7) 3) 8) 4) 7) 4) 8) ppm/K o ppm2/K3 ppm ppm ppm ppm ppm ppm ms V 0 0.55 1.6 VDD Note 6: R=10 kohm +/- 10%, C=10 pF +/- 10% Note 7: CDAC2=6. Note 8: CDAC1=4. Note 9: W ith LIN=255 temperature compensation is in off mode 3 (10) DA9279.003 13 July 2006 IC OUTLINES VDD PV CLK DA TE1 VDD PV CLK DA TE2 1506um MAS9279 1506um MAS9279 VC X2 X1 VSS OUT TE2 VC X2 X1 VSS OUT TE1 Die map reference 2202um Die map reference 2202um Figure 1. MAS9279A1, A3, A5, A7 Figure 2. MAS9279A2, A4, A6, A8 Note 1: MAS9279 pads are round with 80 µm diameter at opening. Note 2: Pin CLK can either be connected to VSS or left floating, pin PV should be connected to Ground or left floating and pin TE1 must be left floating in VCTCXO module end-user application. Note 3: Die map reference is the actual left bottom corner of the sawn chip. SAMPLES IN SB20 DIL PACKAGE 1 2 3 20 TE2 19 OUT 18 VSS 17 X1 MAS9279 YYWW XXXXX.X TE1 4 DA 5 CLK 6 PV 7 VDD 8 9 10 16 15 X2 14 VC 13 12 11 Top marking: YYWW = Year, Week XXXXX.X = Lot number 4 (10) DA9279.003 13 July 2006 DEVICE OUTLINE CONFIGURATION QFN10 3x3 Top View VC X2 X1 VSS OUT VDD PV CLK DA TE1 VC X2 X1 VSS OUT QFN10 3x3 Top View VDD PV CLK DA TE2 9279 AX YWW A = product version X = Load / Output version 1, 3, 5, 7 Y = year WW = week 9279 AX YWW A = product version X = Load / Output version 2, 4, 6, 8 Y = year WW = week 5 (10) DA9279.003 13 July 2006 PACKAGE (QFN10 3X3) OUTLINE D D/2 L2 PIN 1 MARK 0-10 deg A2 TOP VIEW A3 E/2 SEATING PLANE A1 SIDE VIEW L A E2/2 D2 EXPOSED PAD b e BOTTOM VIEW Symbol A A1 A2 A3 b D D2 E E2 e L L2 Min 0.8 0 0.65 0.15 0.200 1.92 1.65 0.350 - Nom 0.9 0.025 0.70 0.20 0.250 3.00 BSC 2.02 3.00 BSC 1.70 0.50 BSC 0.400 - E2 Max 1.0 0.05 0.75 0.25 0.300 2.12 1.75 0.450 0.125 Unit mm mm mm mm mm mm mm mm mm mm mm mm Dimensions do not include mold or interlead flash, protrusions or gate burrs. 6 (10) DA9279.003 13 July 2006 SOLDERING INFORMATION Resistance to Soldering Heat Maximum Temperature Maximum Number of Reflow Cycles Reflow profile Seating Plane Co-planarity Lead Finish According to RSH test IEC 68-2-58/20 260°C 3 Thermal profile parameters stated in JESD22-A113 should not be exceeded. http://www.jedec.org max 0.08 mm Solder plate 7.62 - 25.4 µm, material Matte Tin EMBOSSED TAPE SPECIFICATIONS 4.0 +/- 0.1 1.37 +/- 0.1 8.0 +0.3,-0.1 ORIENTATION ON TAPE 0.254 +/-0.02 3.23 +/- 0.1 USER FEED DIRECTION 4.0 +/- 0.1 3.17 +/- 0.1 7 (10) DA9279.003 13 July 2006 REEL SPECIFICATIONS W2 A D B Tape Slot for Tape Start C N W1 Carrier Tape Cover Tape End Start Trailer Components Leader Dimension A B C D N W1 (measured at hub) W2 (measured at hub) Trailer Leader Min 1.5 12.80 20.2 50 8.4 160 390, of which minimum 160 mm of empty carrier tape sealed with cover tape Max 178 13.50 Unit mm mm mm mm mm mm mm mm mm 9.9 14.4 8 (10) DA9279.003 13 July 2006 ORDERING INFORMATION Product Code MAS9279A1TG00 MAS9279A1HH06 MAS9279A2TG00 MAS9279A2HH06 MAS9279A3TG00 MAS9279A3HH06 MAS9279A4TG00 MAS9279A4HH06 MAS9279A5TG00 MAS9279A5HH06 MAS9279A6TG00 MAS9279A6HH06 MAS9279A7TG00 MAS9279A7HH06 MAS9279A8TG00 MAS9279A8HH06 Product IC FOR VCTCXO IC FOR VCTCXO IC FOR VCTCXO IC FOR VCTCXO IC FOR VCTCXO Frequency output f0/2 IC FOR VCTCXO Frequency output f0/2 IC FOR VCTCXO Frequency output f0/2 IC FOR VCTCXO Frequency output f0/2 IC FOR TCXO IC FOR TCXO IC FOR TCXO IC FOR TCXO IC FOR TCXO Frequency output f0/2 IC FOR TCXO Frequency output f0/2 IC FOR TCXO Frequency output f0/2 IC FOR TCXO Frequency output f0/2 TE2 TE1 TE2 TE1 TE OUTPUT In QFN10 Package EWS Tested wafers 215 µm QFN10, T&R, 3.000 pcs/reel; Pb free, RoHS compliant EWS Tested wafers 215 µm QFN10, T&R, 3.000 pcs/reel; Pb free, RoHS compliant EWS Tested wafers 215 µm QFN10, T&R, 3.000 pcs/reel; Pb free, RoHS compliant EWS Tested wafers 215 µm QFN10, T&R, 3.000 pcs/reel; Pb free, RoHS compliant EWS Tested wafers 215 µm QFN10, T&R, 3.000 pcs/reel; Pb free, RoHS compliant EWS Tested wafers 215 µm QFN10, T&R, 3.000 pcs/reel; Pb free, RoHS compliant EWS Tested wafers 215 µm QFN10, T&R, 3.000 pcs/reel; Pb free, RoHS compliant EWS Tested wafers 215 µm QFN10, T&R, 3.000 pcs/reel; Pb free, RoHS compliant Comments For 8pF Crystal load For 8pF Crystal load For 10pF Crystal load For 10pF Crystal load For 8pF Crystal load For 8pF Crystal load For 10pF Crystal load For 10pF Crystal load For 8pF Crystal load For 8pF Crystal load For 10pF Crystal load For 10pF Crystal load For 8pF Crystal load For 8pF Crystal load For 10pF Crystal load For 10pF Crystal load TE2 TE1 TE1 TE2 Contact Micro Analog Systems Oy for other wafer thickness and bonding options LOCAL DISTRIBUTOR 9 (10) DA9279.003 13 July 2006 MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kamreerintie 2, P.O. Box 51 FIN-02771 Espoo, FINLAND Tel. +358 9 80 521 Fax +358 9 805 3213 http://www.mas-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. 10 (10)