1340A1-3

Rev 4; 3/06 I2C RTC with Trickle Charger General Description The DS1340 is a real-time clock (RTC)/calendar that is pin compatible and functionally equivalent to the ST M41T00, including the software clock calibration. The device additionally provides trickle-charge capability on the VBACKUP pin, a lower timekeeping voltage, and an oscillator STOP flag. Block access of the register map is identical to the ST device. Two additional registers, which are accessed individually, are required for the trickle charger and flag. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. A built-in power-sense circuit detects power failures and automatically switches to the backup supply. Reads and writes are inhibited while the clock continues to run. The device is programmed serially through an I2C* bidirectional bus. Features ♦ Enhanced Second Source for the ST M41T00 ♦ Available in a Surface-Mount Package with an Integrated Crystal (DS1340C) ♦ Fast (400kHz) I2C Interface ♦ Software Clock Calibration ♦ RTC Counts Seconds, Minutes, Hours, Day, Date, Month, and Year ♦ Automatic Power-Fail Detect and Switch Circuitry ♦ Trickle-Charge Capability ♦ Low Timekeeping Voltage Down to 1.3V ♦ Three Operating Voltage Ranges (1.8V, 3V, and 3.3V) ♦ Oscillator Stop Flag ♦ Available in 8-Pin µ SOP or SO Packages ♦ Underwriters Laboratory (UL) Recognized DS1340 Applications Portable Instruments Point-of-Sale Equipment Medical Equipment Telecommunications PART DS1340Z-18 DS1340Z-3 DS1340Z-33 DS1340U-18 DS1340U-3 DS1340U-33 VCC CRYSTAL VCC RPU RPU 1 X1 6 SCL CPU 2 X2 8 VCC FT/OUT 7 C1 VCC Ordering Information TEMP RANGE PIN-PACKAGE -40°C to +85°C 8 SO (0.150in) -40°C to +85°C 8 SO (0.150in) -40°C to +85°C 8 SO (0.150in) -40°C to +85°C 8 µSOP -40°C to +85°C 8 µSOP -40°C to +85°C 8 µSOP -40°C to +85°C 16 SO -40°C to +85°C 16 SO -40°C to +85°C 16 SO -40°C to +85°C 8 SO (0.150in) -40°C to +85°C 8 SO (0.150in) -40°C to +85°C 8 SO (0.150in) -40°C to +85°C 8 µSOP -40°C to +85°C 16 SO -40°C to +85°C 16 SO -40°C to +85°C 16 SO TOP MARK† D1340-18 DS1340-3 D1340-33 1340A1-18 1340A1-3 1340A1-33 1340C-18 1340C-3 1340C-33 D1340-18 DS1340-3 D1340-33 1340A1-18 1340A1-3 1340A1-33 1340C-18 1340C-3 1340C-33 Typical Operating Circuit DS1340C-18 DS1340C-3 DS1340C-33 DS1340Z-18+ DS1340Z-3+ DS1340Z-33+ DS1340U-3+ DS1340C-18# DS1340C-3# DS1340C-33# DS1340U-18+ -40°C to +85°C 8 µSOP DS1340 5 SDA RPU = tR / CB GND 4 VBACKUP 3 DS1340U-33+ -40°C to +85°C 8 µSOP + Denotes a lead-free/RoHS-compliant device. *Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. # Denotes a RoHS-compliant device that may include lead that is exempt under RoHS requirements. The lead finish is JESD97 category e3, and is compatible with both lead-based and leadfree soldering processes. † A "+" anywhere on the top mark denotes a lead-free device. A "#" denotes a RoHS-compliant device. Pin Configurations appear at end of data sheet. ______________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. I2C RTC with Trickle Charger DS1340 ABSOLUTE MAXIMUM RATINGS Voltage Range on VCC Pin Relative to Ground .....-0.3V to +6.0V Voltage Range on SDA, SCL, and FT/OUT Relative to Ground..................................-0.3V to (VCC + 0.3V) Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature Range............................See IPC/JEDEC J-STD-020 Specification Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AC ELECTRICAL CHARACTERISTICS (VCC = VCC MIN to VCC MAX, TA = -40°C to +85°C, unless otherwise noted.) (Note 1, Figure 1) PARAMETER SCL Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition (Note 2) Low Period of SCL Clock High Period of SCL Clock Data Hold Time (Notes 3, 4) Data Setup Time (Note 5) START Setup Time Rise Time of SDA and SCL Signals (Note 6) Fall Time of SDA and SCL Signals (Note 6) Setup Time for STOP Condition Capacitive Load for Each Bus Line I/O Capacitance (SCL, SDA) Pulse Width of Spikes that Must be Suppressed by the Input Filter Oscillator Stop Flag (OSF) Delay SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tSU:STA tR tF tSU:STO CB CI/O tSP tOSF Fast mode (Note 7) CONDITIONS Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode (Note 6) 10 30 100 MIN 0 100 4.7 1.3 4.0 0.6 4.7 1.3 4.0 0.6 0 0 250 100 4.7 0.6 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 4.7 0.6 400 1000 300 300 300 0.9 0.9 TYP MAX 100 400 UNITS kHz µs µs µs µs µs ns µs ns ns µs pF pF ns ms 2 _____________________________________________________________________ I2C RTC with Trickle Charger RECOMMENDED DC OPERATING CONDITIONS (VCC = VCC MIN to VCC MAX, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Supply Voltage (Note 8) Input Logic 1 (SDA, SCL) Input Logic 0 (SDA, SCL) Supply Voltage, Pullup (FT/OUT, SDA, SCL), VCC = 0V Backup Supply Voltage (Note 8) SYMBOL DS1340-18 VCC VIH VIL VPU DS1340-3 DS1340-33 (Note 8) (Note 8) (Note 8) DS1340-18 VBACKUP R1 Trickle-Charge Current-Limiting Resistors R2 R3 Power-Fail Voltage (Note 8) Input Leakage (SCL, CLK) I/O Leakage (SDA, FT/OUT) SDA Logic 0 Output VPF ILI ILO IOLSDA VCC > 2V; VOL = 0.4V 1.7V < VCC < 2V; VOL = 0.2 x VCC VCC > 2V; VOL = 0.4V FT/OUT Logic 0 Output IOLSQW 1.7V < VCC < 2V; VOL = 0.2 x VCC 1.3V < VCC < 1.7V; VOL = 0.2x VCC DS1340-18 Active Supply Current (Note 13) ICCA DS1340-3 DS1340-33 DS1340-18 Standby Current (Note 14) VBACKUP Leakage Current ICCS DS1340-3 DS1340-33 IBACKUPLKG VBACKUP = 3.7V 72 108 192 60 81 100 DS1340-3 DS1340-33 (Notes 9, 10) (Note 11) (Note 12) DS1340-18 DS1340-3 DS1340-33 1.51 2.45 2.70 -1 -1 1.3 1.3 1.3 250 2000 4000 1.6 2.6 2.88 1.71 2.7 2.97 +1 +1 3.0 3.0 3.0 3.0 250 150 200 300 100 125 150 100 nA µA µA µA µA mA mA µA V Ω CONDITIONS MIN 1.71 2.7 2.97 0.7 x VCC -0.3 TYP 1.8 3.0 3.3 MAX 1.89 3.3 5.5 VCC + 0.3 +0.3 x VCC 5.5 3.7 3.7 5.5 V V V V UNITS V DS1340 DC ELECTRICAL CHARACTERISTICS (VCC = 0V, VBACKUP = 3.7V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL IBACKUP1 IBACKUP2 IBACKUP3 VBACKUP Data-Retention Current CONDITIONS OSC ON, FT = 0 (Note 15) OSC ON, FT = 1 (Note 15) OSC ON, FT = 0, VBACKUP = 3.0V, TA = +25°C (Notes 15, 16) MIN TYP 800 850 800 25.0 MAX 1150 1250 1000 100 nA UNITS VBACKUP Current nA IBACKUPDR OSC OFF _____________________________________________________________________ 3 I2C RTC with Trickle Charger DS1340 POWER-UP/POWER-DOWN CHARACTERISTICS (TA = -40°C to +85°C) (Figure 2) PARAMETER Recovery at Power-Up VCC Fall Time; VPF(MAX) to VPF(MIN) VCC Rise Time; VPF(MIN) to VPF(MAX) SYMBOL tREC tVCCF tVCCR (Note 17) 300 0 CONDITIONS MIN TYP MAX 2 UNITS ms µs µs WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode. Note 1: Note 2: Note 3: Note 4: Note 5: Limits at -40°C are guaranteed by design and not production tested. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum tHD:DAT only has to be met if the device does not stretch the low period (tLOW) of the SCL signal. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR MAX + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. CB—total capacitance of one bus line in pF. The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the 0V ≤ VCC ≤ VCCMAX and 1.3V ≤ VBAT ≤ 3.7V range. All voltages are referenced to ground. Measured at VCC = typ, VBACKUP = 0V, register 08h = A5h. The use of the 250Ω trickle-charge resistor is not allowed at VCC > 3.63V and should not be enabled. Measured at VCC = typ, VBACKUP = 0V, register 08h = A6h. Measured at VCC = typ, VBACKUP = 0V, register 08h = A7h. ICCA—SCL clocking at max frequency = 400kHz. Specified with I2C bus inactive. Measured with a 32.768kHz crystal attached to the X1 and X2 pins. Limits at +25°C are guaranteed by design and not production tested. This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay occurs. Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: Note 17: SDA tBUF tLOW tR tF tHD:STA tSP SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO Figure 1. Data Transfer on I2C Serial Bus 4 _____________________________________________________________________ I2C RTC with Trickle Charger DS1340 VCC VPF(MAX) VPF(MIN) tF VPF VPF tR tRPU tRST RST INPUTS RECOGNIZED DON'T CARE RECOGNIZED HIGH-Z OUTPUTS VALID VALID Figure 2. Power-Up/Power-Down Timing Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) ICCSA vs. VCC FT = 0 DS1340 toc01 ICCS vs. VCC FT = 0 DS1340 toc02 IBACKUP1 (FT = 0) vs. VBACKUP 800 SUPPLY CURRENT (nA) 750 700 650 600 550 500 DS1340 toc03 250 150 125 SUPPLY CURRENT (µA) 100 -3.0V 75 50 25 -1.8V 850 200 SUPPLY CURRENT (µA) -3.3V 150 100 50 450 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC (V) 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC (V) 400 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VBACKUP (V) IBACKUP2 (FT = 1) vs. VBACKUP DS1340 toc04 IBACKUP3 vs. TEMPERATURE 850 800 SUPPLY CURRENT (nA) 750 700 650 600 550 500 FREQUENCY (Hz) VBACKUP = 3.0V DS1340 toc05 FT vs. VBACKUP 511.9995 511.9990 511.9985 511.9980 511.9975 511.9970 511.9965 511.9960 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VBACKUP (V) DS1340 toc06 850 800 SUPPLY CURRENT (nA) 750 700 650 600 550 500 450 400 512.0000 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VBACKUP (V) -40 -20 0 20 40 60 80 TEMPERATURE (°C) _____________________________________________________________________ 5 I2C RTC with Trickle Charger DS1340 Pin Description PIN 8 1 2 16 — — NAME X1 X2 FUNCTION Connections for a Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 12.5pF. X1 is the input to the oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the internal oscillator, X2, is floated if an external oscillator is connected to X1. 3 14 Connection for a Secondary Power Supply. For the 1.8V and 3V devices, VBACKUP must be held between 1.3V and 3.7V for proper operation. Diodes placed in series between the supply and the input pin may result in improper operation. VBACKUP can be as high as 5.5V on the 3.3V device. VBACKUP This pin can be connected to a primary cell such as a lithium coin cell. Additionally, this pin can be connected to a rechargeable cell or a super cap when used with the trickle-charge feature. UL recognized to ensure against reverse charging when used with a lithium battery (www.maxim-ic.com/qa/info/ul). GND SDA SCL Ground Serial Data Input/Output. SDA is the data input/output for the I2C serial interface. The SDA pin is open drain and requires an external pullup resistor. Serial Clock Input. SCL is the clock input for the I2C interface and is used to synchronize data movement on the serial interface. Frequency Test/Output. This pin is used to output either a 512Hz signal or the value of the OUT bit. When the FT bit is logic 1, the FT/OUT pin toggles at a 512Hz rate. When the FT bit is logic 0, the FT/OUT pin reflects the value of the OUT bit. This open-drain pin requires an external pullup resistor, and operates with either VCC or VBACKUP applied. Primary Power Supply. When voltage is applied within normal limits, the device is fully accessible and data can be written and read. When a backup supply is connected to the device and VCC is below VTP, reads and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage. No Connection. Must be connected to ground. 4 5 6 15 16 1 7 2 FT/OUT 8 — 3 4–13 VCC N.C. Detailed Description The DS1340 is a low-power clock/calendar with a trickle charger. Address and data are transferred serially through a I2C bidirectional bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The DS1340 has a built-in power-sense circuit that detects power failures and automatically switches to the backup supply. VCC drops below VPF. If VPF is greater than VBACKUP, the device power is switched from VCC to VBACKUP when VCC drops below VBACKUP. The registers are maintained from the V BACKUP source until V CC is returned to nominal levels (Table 1). After VCC returns above VPF, read and write access is allowed tREC. Table 1. Power Control SUPPLY CONDITION VCC < VPF, VCC < VBACKUP VCC < VPF, VCC > VBACKUP VCC > VPF, VCC < VBACKUP VCC > VPF, VCC > VBACKUP READ/WRITE ACCESS No No Yes Yes POWERED BY VBAT VCC VCC VCC Power Control The power-control function is provided by a precise, temperature-compensated voltage reference and a comparator circuit that monitors the V CC level. The device is fully accessible and data can be written and read when VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If V PF is less than V BACKUP , the device power is switched from VCC to VBACKUP when 6 _____________________________________________________________________ I2C RTC with Trickle Charger Oscillator Circuit The DS1340 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 2 specifies several crystal parameters for the external crystal. Figure 3 shows a functional schematic of the oscillator circuit. If using a crystal with the specified characteristics, the startup time is usually less than one second. Operation The DS1340 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and providing a device identification code followed by data. Subsequent registers can be accessed sequentially until a STOP condition is executed. The device is fully accessible and data can be written and read when VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If VPF is less than VBACKUP, the device power is switched from VCC to VBACKUP when V CC drops below V PF . If V PF is greater than VBACKUP, the device power is switched from VCC to VBACKUP when VCC drops below VBACKUP. The registers are maintained from the VBACKUP source until VCC is returned to nominal levels. The functional diagram (Figure 5) shows the main elements of the serial RTC. DS1340 Clock Accuracy The initial clock accuracy depends on the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Figure 4 shows a typical PC board layout for isolating the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks (www.maxim-ic.com/RTCapps) for detailed information. LOCAL GROUND PLANE (LAYER 2) DS1340C Only The DS1340C integrates a standard 32,768Hz crystal into the package. Typical accuracy with nominal VCC and +25°C is approximately +15ppm. Refer to Application Note 58 for information about crystal accuracy vs. temperature. CRYSTAL X1 X2 Table 2. Crystal Specifications* PARAMETER Nominal Frequency Series Resistance Load Capacitance SYMBOL fO ESR CL MIN TYP 32.768 45,60** 12.5 MAX UNITS GND kHz kΩ pF Figure 4. Layout Example *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications. **A crystal with up to 60kΩ ESR can be used if the minimum operating voltages on both VCC and VBACKUP are at least 2.0V. RTC X1 X2 OSCILLATOR 32,768Hz DIVIDER AND CALIBRATION CIRCUIT 512Hz MUX/BUFFER FT/OUT "C" VERSION ONLY VCC COUNTDOWN CHAIN VBACKUP POWER CONTROL CONTROL LOGIC SERIAL BUS INTERFACE AND ADDRESS REGISTER 1Hz CLOCK AND CALENDAR REGISTERS SCL CL1 X1 CRYSTAL X2 CL2 RTC REGISTERS SDA USER BUFFER (7 BYTES) DS1340 Figure 3. Oscillator Circuit Showing Internal Bias Network Figure 5. Functional Diagram 7 _____________________________________________________________________ I2C RTC with Trickle Charger DS1340 Address Map Table 3 shows the DS1340 address map. The RTC registers are located in address locations 00h to 06h, and the control register is located at 07h. The trickle-charge and flag registers are located in address locations 08h to 09h. During a multibyte access of the timekeeping registers, when the address pointer reaches 07h—the end of the clock and control register space—it wraps around to location 00h. Writing the address pointer to the corresponding location accesses address locations 08h and 09h. After accessing location 09h, the address pointer wraps around to location 00h. On a I2C START, STOP, or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to reread the registers in case the main registers update during a read. enable oscillator (EOSC) bit. When this bit is set to 1, the oscillator is disabled. When cleared to 0, the oscillator is enabled. The initial power-up value of EOSC is 0. Location 02h is the century/hours register. Bit 7 and bit 6 of the century/hours register are the century-enable bit (CEB) and the century bit (CB). Setting CEB to logic 1 causes the CB bit to toggle, either from a logic 0 to a logic 1, or from a logic 1 to a logic 0, when the years register rolls over from 99 to 00. If CEB is set to logic 0, CB does not toggle. When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers on any START or STOP and when the register pointer rolls over to zero. The time information is read from these secondary registers while the clock continues to run. This eliminates the need to reread the registers in case the internal registers update during a read. The divider chain is reset whenever the seconds register is written. Write transfers occur on the acknowledge from the DS1340. Once the divider chain is reset, to avoid rollover issues, the remaining time and date registers must be written within one second. Clock and Calendar The time and calendar information is obtained by reading the appropriate register bytes. Table 3 shows the RTC registers. The time and calendar data are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the binary-coded decimal (BCD) format. The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. Bit 7 of register 0 is the Special-Purpose Registers The DS1340 has three additional registers (control, trickle charger, and flag) that control the RTC, trickle charger, and oscillator flag output. Table 3. Address Map ADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H OUT TCS3 OSF FT TCS2 0 BIT 7 EOSC X CEB X X X CB X X X X 10 Year S TCS1 0 CAL4 TCS0 0 CAL3 DS1 0 CAL2 DS0 0 X 10 Date 10 Month BIT 6 BIT 5 10 Seconds 10 Minutes 10 Hours X X Date Month Year CAL1 ROUT1 0 CAL0 ROUT0 0 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION Seconds Minutes Century/Hours Day Date Month Year Control Trickle Charger Flag RANGE 00–59 00–59 0–1; 00–23 01–07 01–31 01–12 00–99 — — — Seconds Minutes Hours Day X = Read/Write bit Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. 8 _____________________________________________________________________ I2C RTC with Trickle Charger Control Register (07h) Bit 7: Output Control (OUT). This bit controls the output level of the FT/OUT pin when the FT bit is set to 0. If FT = 0, the logic level on the FT/OUT pin is 1 if OUT = 1 and 0 if OUT = 0. The initial power-up OUT value is 1. Bit 6: Frequency Test (FT). When this bit is 1, the FT/OUT pin toggles at a 512Hz rate. When FT is written to 0, the OUT bit controls the state of the FT/OUT pin. The initial power-up value of FT is 0. Bit 5: Calibration Sign Bit (S). A logic 1 in this bit indicates positive calibration for the RTC. A 0 indicates negative calibration for the clock. See the C lock Calibration section for a detailed description of the bit operation. The initial power-up value of S is 0. Bits 4 to 0: Calibration Bits (CAL4 to CAL0). These bits can be set to any value between 0 and 31 in binary form. See the Clock Calibration section for a detailed description of the bit operation. The initial power-up value of CAL0–CAL4 is 0. is disabled when power is first applied. The diodeselect (DS) bits (bits 2, 3) select whether or not a diode is connected between VCC and VBACKUP. If DS is 01, no diode is selected; if DS is 10, a diode is selected. The ROUT bits (bits 0, 1) select the value of the resistor connected between VCC and VBACKUP. Table 3 shows the resistor selected by the resistor select (ROUT) bits and the diode selected by the diode select (DS) bits. Warning: The ROUT value of 250Ω must not be selected whenever VCC is greater than 3.63V. The user determines diode and resistor selection according to the maximum current desired for battery or super cap charging (Table 4). The maximum charging current can be calculated as illustrated in the following example. Assume that a 3.3V system power supply is applied to VCC and a super cap is connected to VBACKUP. Also assume that the trickle charger has been enabled with a diode and resistor R2 between VCC and VBACKUP. The maximum current IMAX would therefore be calculated as follows: IMAX = (3.3V - diode drop) / R2 ≈ (3.3V - 0.7V) / 2kΩ ≈ 1.3mA As the super cap charges, the voltage drop between VCC and VBACKUP decreases and therefore the charge current decreases. DS1340 Trickle-Charger Register (08h) The simplified schematic in Figure 6 shows the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4–7) control the selection of the trickle charger. To prevent accidental enabling, only a pattern on 1010 enables the trickle charger. All other patterns disable the trickle charger. The trickle charger BIT 7 TCS3 BIT 6 TCS2 BIT 5 TCS1 BIT 4 TCS0 BIT 3 DS1 BIT 2 DS0 BIT 1 BIT 0 ROUT1 ROUT0 TCS0-3 = TRICKLE-CHARGER SELECT DS0-1 = DIODE SELECT TOUT0-1 = RESISTOR SELECT 1 OF 16 SELECT NOTE: ONLY 1010b ENABLES CHARGER 1 OF 2 SELECT 1 OF 3 SELECT R1 250Ω VCC R2 2kΩ R3 4kΩ VBACKUP Figure 6. Trickle Charger Functional Diagram _____________________________________________________________________ 9 I2C RTC with Trickle Charger DS1340 Table 4. Trickle-Charge Register TCS3 X X X 1 1 1 1 1 1 0 TCS2 X X X 0 0 0 0 0 0 0 TCS1 X X X 1 1 1 1 1 1 0 TCS0 X X X 0 0 0 0 0 0 0 DS1 0 1 X 0 1 0 1 0 1 0 DS0 0 1 X 1 0 1 0 1 0 0 ROUT1 X X 0 0 0 1 1 1 1 0 ROUT0 X X 0 1 1 0 0 1 1 0 Disabled Disabled Disabled No diode, 250Ω resistor One diode, 250Ω resistor No diode, 2kΩ resistor One diode, 2kΩ resistor No diode, 4kΩ resistor One diode, 4kΩ resistor Power-on reset value FUNCTION Flag Register (09h) Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator has stopped or was stopped for some time period and may be used to judge the validity of the clock and calendar data. This bit is edge triggered and is set to logic 1 when the internal circuitry senses that the oscillator has transitioned from a normal run state to a STOP condition. The following are examples of conditions that can cause the OSF bit to be set: The first time power is applied. The voltages present on VCC and VBACKUP are insufficient to support oscillation. 3) The E OSC bit is set to 1, disabling the oscillator. 4) External influences on the crystal (e.g., noise, leakage). The OSF bit remains at logic 1 until written to logic 0. It can only be written to logic 0. Attempting to write OSF to logic 1 leaves the value unchanged. Bits 6 to 0: All other bits in the flag register read as 0 and cannot be written. 1) 2) Clock Calibration The DS1340 provides a digital clock calibration feature to allow compensation for crystal and temperature variations. The calibration circuit adds or subtracts counts from the oscillator divider chain at the divide-by-256 stage. The number of pulses blanked (subtracted for negative calibration) or inserted (added for positive calibration) depends upon the value loaded into the five calibration bits (CAL4–CAL0) located in the control reg10 ister. Adding counts speeds the clock up and subtracting counts slows the clock down. The calibration bits can be set to any value between 0 and 31 in binary form. Bit 5 of the control register, S, is the sign bit. A value of 1 for the S bit indicates positive calibration, while a value of 0 represents negative calibration. Calibration occurs within a 64-minute cycle. The first 62 minutes in the cycle can, once per minute, have a one-second interval where the calibration is performed. Negative calibration blanks 128 cycles of the 32,768Hz oscillator, slowing the clock down. Positive calibration inserts 256 cycles of the 32,768Hz oscillator, speeding the clock up. If a binary 1 is loaded into the calibration bits, only the first two minutes in the 64minute cycle are modified. If a binary 6 is loaded, the first 12 minutes are affected, and so on. Therefore, each calibration step either adds 512 or subtracts 256 oscillator cycles for every 125,829,120 actual 32,678Hz oscillator cycles (64 minutes). This equates to +4.068ppm or -2.034ppm of adjustment per calibration step. If the oscillator runs at exactly 32,768Hz, each of the 31 increments of the calibration bits would represent +10.7 or -5.35 seconds per month, corresponding to +5.5 or -2.75 minutes per month. For example, if using the FT function, a reading of 512.01024Hz would indicate a +20ppm oscillator frequency error, requiring a -10(00 1010) value to be loaded in the S bit and the five calibration bits. Note: Setting the calibration bits does not affect the frequency test output frequency. Also note that writing to the control register resets the divider chain. ____________________________________________________________________ I2C RTC with Trickle Charger I2C Serial Data Bus The DS1340 supports a bidirectional I2C bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are slaves. A master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the bus. The DS1340 operates as a slave on the I2C bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. Within the bus specifications a standard mode (100kHz max clock rate) and a fast mode (400kHz max clock rate) are defined. The DS1340 works in both modes. The following bus protocol has been defined (Figure 7): • Data transfer can be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. START data transfer: A change in the data line’s state from high to low, while the clock line is high, defines a START condition. STOP data transfer: A change in the data line’s state from low to high, while the clock line is high, defines a STOP condition. Data valid: The data line’s state represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between the START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the STOP condition. DS1340 SDA MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 START CONDITION 2 6 7 8 9 ACK REPEATED IF MORE BYTES ARE TRANSFERED 1 2 3–7 8 9 ACK STOP CONDITION OR REPEATED START CONDITION ACKNOWLEDGEMENT SIGNAL FROM RECEIVER Figure 7. I2C Data Transfer Overview ____________________________________________________________________ 11 I2C RTC with Trickle Charger DS1340 Figures 8 and 9 detail how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two types of data transfer are possible: Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave address). The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned. The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. The DS1340 can operate in the following two modes: Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. Start and STOP conditions are recognized as the beginning and end of a serial transfer. Hardware performs address recognition after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains the 7-bit DS1340 address, which is 1101000, followed by the direction bit (R/W), which is 0 for a write. After receiving and decoding the slave address byte, the DS1340 outputs an acknowledge on SDA. After the DS1340 acknowledges the slave address + write bit, the master transmits a word address to the DS1340. This sets the register pointer on the DS1340, with the DS1340 acknowledging the transfer. The master can then transmit zero or more bytes of data, with the DS1340 acknowledging each byte received. The register pointer increments after each data byte is transferred. The master generates a STOP condition to terminate the data write. Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. The DS1340 transmits serial data on SDA while the serial clock is input on SCL. Start and STOP conditions are recognized as the beginning and end of a serial transfer. Hardware performs address recognition after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains the 7-bit DS1340 address, which is 1101000, followed by the direction bit (R/ W ), which is 1 for a read. After receiving and decoding the slave address byte, the DS1340 outputs an acknowledge on SDA. The DS1340 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode, the first address that is read is the last one stored in the register pointer. The DS1340 must receive a not acknowledge to end a read. S 1101000 0 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P S 1101000 1 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P DATA TRANSFERRED S — START (X + 1 BYTES + ACKNOWLEDGE) A — ACKNOWLEDGE NOTE: LAST DATA BYTE IS FOLLOWED BY P — STOP A NOT ACKNOWLEDGE (A) SIGNAL A — NOT ACKNOWLEDGE R/W — READ/WRITE OR DIRECTION BIT ADDRESS = D0H S — START DATA TRANSFERRED A — ACKNOWLEDGE (X + 1 BYTES + ACKNOWLEDGE) P — STOP R/W — READ/WRITE OR DIRECTION BIT ADDRESS = D0H Figure 8. Slave Receiver Mode (Write Mode) Figure 9. Slave Transmitter Mode (Read Mode 12 ____________________________________________________________________ I2C RTC with Trickle Charger Handling, PC Board Layout, and Assembly The DS1340C package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but precautions should be taken to ensure that excessive shocks are avoided. Exposure to reflow is limited to 2 times maximum. Ultrasonic cleaning should be avoided to prevent damage to the crystal. Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. All N.C. (no connect) pins must be connected to ground. The leaded 16-pin SO package may be reflowed as long as the peak temperature does not exceed 240°C. Peak reflow temperature (≥ 230°C) duration should not exceed 10 seconds, and the total time above 200°C should not exceed 40 seconds (30 seconds nominal). The RoHS and lead-free/RoHS packages may be reflowed using a reflow profile that complies with JEDEC J-STD-020. Moisture-sensitive packages are shipped from the factory dry-packed.Handling instructions listed on the package label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020 standard for moisture-sensitive device (MSD) classifications. DS1340 Pin Configurations TOP VIEW SCL 1 FT/OUT 2 X1 1 X2 VBACKUP GND 2 3 4 8 VCC FT/OUT SCL SDA VCC 3 N.C. 4 N.C. 5 N.C. 6 N.C. 7 N.C. 8 16 SDA 15 GND 14 VBACKUP DS1340 7 6 5 DS1340C 13 N.C. 12 N.C. 11 N.C. 10 N.C. 9 N.C. SO, µSOP SO (300 mils) ____________________________________________________________________ 13 I2C RTC with Trickle Charger DS1340 Chip Information TRANSISTOR COUNT: 10,930 PROCESS: CMOS SUBSTRATE CONNECTED TO GROUND Package Information For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. PACKAGE 8-pin SO (150 mils) 8-pin µSOP 16-pin SO (300 mils) DOCUMENT NUMBER 56-G2008-001 56-G2018-001 56-G4009-001 Thermal Information Theta-JA: +170°C/W (0.150in SO) Theta-JC: +40°C/W (0.150in SO) Theta-JA: +221°C/W (µSOP) Theta-JC: +39°C/W (µSOP) Theta-JA: +89.6°C/W (0.300in SO) Theta-JC: +24.8°C/W (0.300in SO) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation.