71M6545H

19-5378; Rev 1.0; 4/11 71M6545/71M6545H A Maxim Integrated Products Brand Metrology Processors DATA SHEET April 2011 GENERAL DESCRIPTION The 71M6545/71M6545H metrology processors are based on Teridian’s 4th-generation metering architecture supporting the 71M6xxx series of isolated current sensing products that offer drastic reduction in component count, immunity to magnetic tampering, and unparalleled reliability. The 71M6545/71M6545H integrate our Single Converter Technology® with a 22-bit deltasigma ADC, a customizable 32-bit computation engine (CE) for core metrology functions, as well as a user-programmable 8051compatible application processor (MPU) core with up to 64KB flash and up to 5KB RAM. An external host processor can access metrology functions directly through the SPI™ interface, or alternatively through the embedded MPU core in applications requiring metrology data capture, storage, and preprocessing within the metrology subsystem. In addition, the devices integrate an RTC, DIO, and UART. A complete array of ICE and development tools, programming libraries, and reference designs enable rapid development and certification of meters that meet all ANSI and IEC electricity metering standards worldwide. C FEATURES • Up to < 0.1% Accuracy Over 2000:1 Current Range • Exceeds IEC 62053/ANSI C12.20 Standards • Seven Sensor Inputs with Neutral Current Measurement, Differential Mode Selectable for Current Inputs • Selectable Gain of 1 or 8 for One Current Input to Support Shunts • High-Speed Wh/VARh Pulse Outputs with Programmable Width • Flash/RAM Size 32KB/3KB (71M6545) 64KB/5KB (71M6545H) • Up to Four Pulse Outputs with Pulse Count • Four-Quadrant Metering, Phase Sequencing • Digital Temperature Compensation Metrology Compensation Accurate RTC for TOU Functions with Automatic Temperature Compensation for Crystal in All Power Modes • Independent 32-Bit Compute Engine • 46–64Hz Line Frequency Range with the Same Calibration • Phase Compensation (±7°) • 1µA Supply Current in Sleep Mode • Flash Security • In-System Program Update • 8-Bit MPU (80515), Up to 5 MIPS, for Optional Implementation of Postprocessing and Host Support Functions (Optional Use) • Up to 29 DIO Pins • Hardware Watchdog Timer (WDT) • I2C/MICROWIRE® EEPROM Interface • SPI Interface for Host: Full Access to Shared Memory Space Flash Program Capability • UART • Industrial Temperature Range • 64-Pin Lead(Pb)-Free LQFP Package Shunt Resistor Sensors NEUTRAL B LOAD A POWER SUPPLY 71M6xx3 71M6xx3 71M6xx3 This system is referenced to Neutral NEUTRAL Resistor Dividers Pulse Transformers C MUX and ADC IADC0 } IN* IADC1 VADC10 (VC) IADC6 IADC7 } IC VADC9 (VB) IADC4 } IB IADC5 VADC8(VA) IADC2 } IA IADC3 VREF SERIAL PORT RX TX V3P3A V3P3SYS GNDA GNDD PWR MODE CONTROL B TERIDIAN 71M6545/H PB REGULATOR A VBAT_RTC TEMPERATURE SENSOR BATTERY MONITOR OSCILLATOR/ PLL XIN RTC BATTERY RAM 32 kHz XOUT DIO, PULSES, LEDs DIO 2 MPU FLASH MEMORY ICE SPI_CKI SPI_DI SPI_DO SPI_CSZ XFER_BUSY SAG *IN = Optional Neutral Current RTC TIMERS 24 DIO I C or µWire EEPROM V3P3D SPI INTERFACE HOST T M COMPUTE U ENGINE X WPULSE XPULSE RPULSE YPULSE 10/7/2010 PULSES 3.3 VDC S ingle Converter Technology is a registered trademark of Maxim Integrated Products, Inc. SPI is a trademark of Motorola, Inc. MICROWIRE is a registered trademark of National Semiconductor Corp. v1.0 © 2008–2011 Teridian Semiconductor Corporation 1 Data Sheet 71M6545/H PDS_6545_009 Table of Contents 1 2 INTRODUCTION ........................................................................................................................... 10 Hardware Description .................................................................................................................. 11 2.1 Hardware Overview............................................................................................................... 11 2.2 Analog Front End (AFE) ........................................................................................................ 12 2.2.1 Signal Input Pins ....................................................................................................... 13 2.2.2 Input Multiplexer ........................................................................................................ 14 2.2.3 Delay Compensation ................................................................................................. 19 2.2.4 ADC Pre-Amplifier ..................................................................................................... 20 2.2.5 A/D Converter (ADC) ................................................................................................. 20 2.2.6 FIR Filter ................................................................................................................... 20 2.2.7 Voltage References ................................................................................................... 20 2.2.8 71M6xx3 Isolated Sensor Interface............................................................................ 21 2.3 Digital Computation Engine (CE) ........................................................................................... 25 2.3.1 CE Program Memory ................................................................................................. 25 2.3.2 CE Data Memory ....................................................................................................... 25 2.3.3 CE Communication with the MPU .............................................................................. 25 2.3.4 Meter Equations ........................................................................................................ 26 2.3.5 Real-Time Monitor (RTM) .......................................................................................... 26 2.3.6 Pulse Generators ...................................................................................................... 26 2.3.7 CE Functional Overview ............................................................................................ 28 2.4 80515 MPU Core .................................................................................................................. 30 2.4.1 MPU Setup Code ...................................................................................................... 30 2.4.2 80515 MPU Overview................................................................................................ 30 2.4.3 Memory Organization and Addressing ....................................................................... 31 2.4.4 Special Function Registers (SFRs) ............................................................................ 33 2.4.5 Generic 80515 Special Function Registers ................................................................ 33 2.4.6 Instruction Set ........................................................................................................... 36 2.4.7 UARTs ...................................................................................................................... 36 2.4.8 Timers and Counters ................................................................................................. 38 2.4.9 W D Timer (Software Watchdog Timer) ...................................................................... 40 2.4.10 Interrupts................................................................................................................... 40 2.5 On-Chip Resources............................................................................................................... 46 2.5.1 Physical Memory ....................................................................................................... 46 2.5.2 Oscillator ................................................................................................................... 48 2.5.3 PLL and Internal Clocks............................................................................................. 48 2.5.4 Real-Time Clock (RTC) ............................................................................................. 49 2.5.5 71M6545/H Temperature Sensor............................................................................... 53 2.5.6 71M6xx3 Temperature Sensor .................................................................................. 54 2.5.7 71M6545/H Battery Monitor ....................................................................................... 55 2.5.8 71M6xx3 VCC Monitor .............................................................................................. 55 2.5.9 UART Interface ......................................................................................................... 55 2.5.10 DIO Pins ................................................................................................................... 55 2.5.11 EEPROM Interface .................................................................................................... 57 2.5.12 SPI Slave Port ........................................................................................................... 60 2.5.13 Hardware Watchdog Timer ........................................................................................ 64 2.5.14 Test Ports (TMUXOUT and TMUX2OUT Pins)........................................................... 64 Functional Description ................................................................................................................ 66 3 2 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 3.1 3.2 3.3 Data Sheet 71M6545/H 4 5 6 Theory of Operation .............................................................................................................. 66 SLP Mode (Sleep Mode) ....................................................................................................... 67 Fault and Reset Behavior ...................................................................................................... 68 3.3.1 Events at Power-Down .............................................................................................. 68 3.3.2 Reset Sequence ........................................................................................................ 69 3.4 Data Flow and Host Communication ..................................................................................... 69 Application Information ............................................................................................................... 71 4.1 Connecting 5 V Devices ........................................................................................................ 71 4.2 Directly Connected Sensors .................................................................................................. 71 4.3 Systems Using 71M6xx3 Isolated Sensors and Current Shunts ............................................. 72 4.4 System Using Current Transformers ..................................................................................... 73 4.5 Metrology Temperature Compensation.................................................................................. 74 4.5.1 Distinction Between Standard and High-Precision Parts ............................................ 74 4.5.2 Temperature Coefficients for the 71M6545 ................................................................ 75 4.5.3 Temperature Coefficients for the 71M6545H.............................................................. 75 4.5.4 Temperature Coefficients for the 71M6603 and 71M6103 (1% Energy Accuracy) ...... 75 4.5.5 Temperature Compensation for VREF and Shunt Sensors ........................................ 75 4.5.6 Temperature Compensation of VREF and Current Transformers ............................... 77 4.6 Connecting I2C EEPROMs .................................................................................................... 79 4.7 Connecting Three-Wire EEPROMs ....................................................................................... 79 4.8 UART (TX/RX) ...................................................................................................................... 79 4.9 Connecting the Reset Pin...................................................................................................... 79 4.10 Connecting the Emulator Port Pins ........................................................................................ 80 4.11 Flash Programming ............................................................................................................... 80 4.11.1 Flash Programming via the ICE Port .......................................................................... 80 4.11.2 Flash Programming via the SPI Port .......................................................................... 80 4.12 MPU Demonstration Code..................................................................................................... 81 4.13 Crystal Oscillator ................................................................................................................... 81 4.14 Meter Calibration................................................................................................................... 81 Firmware Interface ....................................................................................................................... 82 5.1 I/O RAM Map –Functional Order ........................................................................................... 82 5.2 I/O RAM Map – Alphabetical Order ....................................................................................... 88 5.3 Reading the Info Page (71M6545H only) ............................................................................... 98 5.4 CE Interface Description ..................................................................................................... 100 5.4.1 CE Program ............................................................................................................ 100 5.4.2 CE Data Format ...................................................................................................... 100 5.4.3 Constants ................................................................................................................ 100 5.4.4 Environment ............................................................................................................ 101 5.4.5 CE Calculations....................................................................................................... 101 5.4.6 CE Front End Data (Raw Data)................................................................................ 102 5.4.7 CE Status and Control ............................................................................................. 103 5.4.8 CE Transfer Variables ............................................................................................. 105 5.4.9 Pulse Generation..................................................................................................... 107 5.4.10 CE Calibration Parameters ...................................................................................... 110 5.4.11 CE Flow Diagrams .................................................................................................. 111 71M6545/H Specifications ......................................................................................................... 113 v1.0 © 2008–2011 Teridian Semiconductor Corporation 3 Data Sheet 71M6545/H 6.1 6.2 6.3 6.4 PDS_6545_009 Absolute Maximum Ratings ................................................................................................. 113 Recommended External Components ................................................................................. 114 Recommended Operating Conditions .................................................................................. 114 Performance Specifications ................................................................................................. 115 6.4.1 Input Logic Levels ................................................................................................... 115 6.4.2 Output Logic Levels................................................................................................. 115 6.4.3 Battery Monitor ........................................................................................................ 116 6.4.4 Temperature Monitor ............................................................................................... 117 6.4.5 Supply Current ........................................................................................................ 118 6.4.6 V3P3D Switch ......................................................................................................... 118 6.4.7 Internal Power Fault Comparators ........................................................................... 119 6.4.8 2.5 V Voltage Regulator – System Power ................................................................ 119 6.4.9 Crystal Oscillator ..................................................................................................... 119 6.4.10 Phase-Locked Loop (PLL) ....................................................................................... 120 6.4.11 71M6545/H VREF ................................................................................................... 121 6.4.12 ADC Converter (71M6545/H)................................................................................... 122 6.4.13 Pre-Amplifier for IADC0-IADC1 ................................................................................ 123 6.5 Timing Specifications .......................................................................................................... 124 6.5.1 Flash Memory ......................................................................................................... 124 6.5.2 SPI Slave ................................................................................................................ 124 6.5.3 EEPROM Interface .................................................................................................. 124 6.5.4 RESET Pin .............................................................................................................. 125 6.5.5 Real-Time Clock (RTC) ........................................................................................... 125 6.6 64-Pin LQFP Package Outline Drawing ............................................................................... 126 6.7 71M6545/H Pinout .............................................................................................................. 127 6.8 71M6545/H Pin Descriptions ............................................................................................... 128 6.8.1 71M6545/H Power and Ground Pins........................................................................ 128 6.8.2 71M6545/H Analog Pins .......................................................................................... 129 6.8.3 71M6545/H Digital Pins ........................................................................................... 130 6.8.4 I/O Equivalent Circuits ............................................................................................. 131 7 Ordering Information ................................................................................................................. 132 7.1 71M6545/H Ordering Guide ................................................................................................ 132 8 R elated Information ................................................................................................................ 132 9 C ontact Information ................................................................................................................ 132 Appendix A: Acronyms .................................................................................................................... 133 Appendix B: Revision History .......................................................................................................... 134 4 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H Figures Figure 1: IC Functional Block Diagram ..................................................................................................... 9 Figure 2: AFE Block Diagram (Shunts: One-Local, Three-Remotes) ...................................................... 12 Figure 3. AFE Block Diagram (Four CTs) ............................................................................................... 13 Figure 4: States in a Multiplexer Frame (MUX_DIV[3:0] = 6) .................................................................. 17 Figure 5: States in a Multiplexer Frame (MUX_DIV[3:0] = 7) .................................................................. 17 Figure 6: General Topology of a Chopped Amplifier ............................................................................... 21 Figure 7: CROSS Signal with CHOP_E = 00........................................................................................... 21 Figure 8: RTM Timing ............................................................................................................................ 26 Figure 9. Pulse Generator FIFO Timing ................................................................................................. 28 Figure 10: Samples from Multiplexer Cycle (Frame) ............................................................................... 29 Figure 11: Accumulation Interval ............................................................................................................ 29 Figure 12: Interrupt Structure ................................................................................................................. 45 Figure 13: Automatic Temperature Compensation ................................................................................. 52 Figure 14: Connecting an External Load to DIO Pins ............................................................................. 57 Figure 15: 3-wire Interface. Write Command, HiZ=0. ............................................................................. 59 Figure 16: 3-wire Interface. Write Command, HiZ=1 .............................................................................. 59 Figure 17: 3-wire Interface. Read Command. ........................................................................................ 59 Figure 18: 3-Wire Interface. Write Command when CNT=0 ................................................................... 59 Figure 19: 3-wire Interface. Write Command when HiZ=1 and WFR=1. ................................................. 60 Figure 20: SPI Slave Port - Typical Multi-Byte Read and Write operations.............................................. 61 Figure 21: Voltage, Current, Momentary and Accumulated Energy......................................................... 66 Figure 22: Data Flow ............................................................................................................................. 70 Figure 23: Resistive Voltage Divider (Voltage Sensing) .......................................................................... 71 Figure 24. CT with Single-Ended Input Connection (Current Sensing) .................................................... 71 Figure 25: CT with Differential Input Connection (Current Sensing) ........................................................ 71 Figure 26: Differential Resistive Shunt Connections (Current Sensing)................................................... 71 Figure 27: System Using Three-Remotes and One-Local (Neutral) Sensor ............................................ 72 Figure 28. System Using Current Transformers ..................................................................................... 73 Figure 29: I2C EEPROM Connection...................................................................................................... 79 Figure 30: Connections for the UART .................................................................................................... 79 Figure 31: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right) ....... 80 Figure 32: External Components for the Emulator Interface ................................................................... 80 Figure 33. Trim Fuse Bit Mapping .......................................................................................................... 98 Figure 34: CE Data Flow: Multiplexer and ADC .................................................................................... 111 Figure 35: CE Data Flow: Scaling, Gain Control, Intermediate Variables for one Phase........................ 111 Figure 36: CE Data Flow: Squaring and Summation Stages ................................................................. 112 Figure 37: 64-pin LQFP Package Outline ............................................................................................. 126 Figure 38: Pinout for the LQFP-64 Package ......................................................................................... 127 Figure 39: I/O Equivalent Circuits......................................................................................................... 131 v1.0 © 2008–2011 Teridian Semiconductor Corporation 5 Data Sheet 71M6545/H PDS_6545_009 Tables Table 1. Required CE Code and Settings for 1-Local / 3-Remotes ......................................................... 15 Table 2. Required CE Code and Settings for CT Sensors ...................................................................... 16 Table 3: Multiplexer and ADC Configuration Bits ................................................................................... 19 Table 4. RCMD[4:0] Bits ........................................................................................................................ 22 Table 5: Remote Interface Read Commands ........................................................................................ 23 Table 6: I/O RAM Control Bits for Isolated Sensor ................................................................................. 23 Table 7: Inputs Selected in Multiplexer Cycles ....................................................................................... 26 Table 8: CKMPU Clock Frequencies ...................................................................................................... 30 Table 9: Memory Map ............................................................................................................................ 31 Table 10: Internal Data Memory Map ..................................................................................................... 33 Table 11: Special Function Register Map ............................................................................................... 33 Table 12: Generic 80515 SFRs - Location and Reset Values ................................................................. 33 Table 13: PSW Bit Functions (SFR 0xD0) ............................................................................................... 35 Table 14: Port Registers (DIO0-14)........................................................................................................ 35 Table 15: Stretch Memory Cycle Width .................................................................................................. 36 Table 16: Baud Rate Generation............................................................................................................ 37 Table 17: UART Modes ......................................................................................................................... 37 Table 18: The S0CON (UART0) Register (SFR 0x98) ............................................................................. 38 Table 19: PCON Register Bit Description (SFR 0x87) .............................................................................. 38 Table 20: Timers/Counters Mode Description ........................................................................................ 38 Table 21: Allowed Timer/Counter Mode Combinations ........................................................................... 39 Table 22: TMOD Register Bit Description (SFR 0x89) ............................................................................ 39 Table 23: The TCON Register Bit Functions (SFR 0x88) ........................................................................ 39 Table 24: The IEN0 Bit Functions (SFR 0xA8)........................................................................................ 40 Table 25: The IEN1 Bit Functions (SFR 0xB8)........................................................................................ 41 Table 26: The IEN2 Bit Functions (SFR 0x9A)........................................................................................ 41 Table 27: TCON Bit Functions (SFR 0x88) ............................................................................................. 41 Table 28: The T2CON Bit Functions (SFR 0xC8) ................................................................................... 41 Table 29: The IRCON Bit Functions (SFR 0xC0) .................................................................................... 42 Table 30: External MPU Interrupts ......................................................................................................... 42 Table 31: Interrupt Enable and Flag Bits ................................................................................................ 43 Table 32: Interrupt Priority Level Groups ................................................................................................ 43 Table 33: Interrupt Priority Levels .......................................................................................................... 44 Table 34: Interrupt Priority Registers (IP0 and IP1) ................................................................................. 44 Table 35: Interrupt Polling Sequence ..................................................................................................... 44 Table 36: Interrupt Vectors .................................................................................................................... 44 Table 37: Flash Memory Access ............................................................................................................ 46 Table 38: Flash Security ........................................................................................................................ 47 Table 39: Clock System Summary ......................................................................................................... 49 Table 40: RTC Control Registers ........................................................................................................... 50 Table 41: I/O RAM Registers for RTC Temperature Compensation ........................................................ 51 Table 42: I/O RAM Registers for RTC Interrupts .................................................................................... 52 Table 43: I/O RAM Registers for Temperature and Battery Measurement .............................................. 54 Table 44: Data/Direction Registers and Internal Resources for DIO0 to DIO14....................................... 55 Table 45: Data/Direction Registers for DIO19-25 and DIO28-29 ............................................................. 56 Table 46: Data/Direction Registers for DIO55 ........................................................................................ 56 Table 47: Selectable Resources using the DIO_Rn[2:0] Bits................................................................... 56 Table 48: EECTRL Bits for 2-pin Interface............................................................................................... 57 6 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H Table 49: EECTRL Bits for the 3-wire Interface ....................................................................................... 58 Table 50: SPI Transaction Fields ........................................................................................................... 61 Table 51: SPI Command Sequences ..................................................................................................... 62 Table 52: SPI Registers ......................................................................................................................... 62 Table 53: TMUX[4:0] Selections ............................................................................................................ 64 Table 54: TMUX2[4:0] Selections........................................................................................................... 65 Table 55: Available Circuit Functions ..................................................................................................... 67 Table 56: VSTAT[2:0] (SFR 0xF9[2:0]) ................................................................................................... 68 Table 57: GAIN_ADJn Compensation Channels (Figure 2, Figure 27, Table 1) ...................................... 76 Table 58: GAIN_ADJx Compensation Channels (Figure 3, Figure 28, Table 2) ...................................... 78 Table 59: I/O RAM Map – Functional Order, Basic Configuration ........................................................... 82 Table 60: I/O RAM Map – Functional Order ........................................................................................... 84 Table 61: I/O RAM Map – Alphabetical Order ........................................................................................ 88 Table 62. Info Page Trim Fuses ............................................................................................................. 98 Table 63: CE EQU[2:0] Equations and Element Input Mapping ............................................................ 101 Table 64: CE Raw Data Access Locations ........................................................................................... 102 Table 65: CESTATUS Register .............................................................................................................. 103 Table 66: CESTATUS Bit Definitions...................................................................................................... 103 Table 67: CECONFIG Register ............................................................................................................. 103 Table 68: CECONFIG Bit Definitions (CE RAM 0x20) ........................................................................... 103 Table 69: Sag Threshold, Phase Measurement, and Gain Adjust Control ............................................. 105 Table 70: CE Transfer Variables (with Shunts) ..................................................................................... 105 Table 71: CE Transfer Variables (with CTs) ......................................................................................... 105 Table 72: CE Energy Measurement Variables (with Shunts)................................................................. 106 Table 73: CE Energy Measurement Variables (with CTs) ..................................................................... 106 Table 74: Other Transfer Variables ...................................................................................................... 107 Table 75: CE Pulse Generation Parameters......................................................................................... 108 Table 76: CE Parameters for Noise Suppression and Code Version..................................................... 109 Table 77: CE Calibration Parameters ................................................................................................... 110 Table 78: Absolute Maximum Ratings .................................................................................................. 113 Table 79: Recommended External Components .................................................................................. 114 Table 80: Recommended Operating Conditions ................................................................................... 114 Table 81: Input Logic Levels ................................................................................................................ 115 Table 82: Output Logic Levels ............................................................................................................. 115 Table 83: Battery Monitor Performance Specifications (TEMP_BAT = 1) ............................................... 116 Table 84. Temperature Monitor............................................................................................................ 117 Table 85: Supply Current Performance Specifications.......................................................................... 118 Table 86: V3P3D Switch Performance Specifications........................................................................... 118 Table 87: 2.5 V Voltage Regulator Performance Specifications (VDD pin) ............................................ 119 Table 88: Crystal Oscillator Performance Specifications....................................................................... 119 Table 89: PLL Performance Specifications........................................................................................... 120 Table 90: 71M6545/H VREF Performance Specifications ..................................................................... 121 Table 91: ADC Converter Performance Specifications ......................................................................... 122 Table 92: Pre-Amplifier Performance Specifications ............................................................................. 123 Table 93: Flash Memory Timing Specifications .................................................................................... 124 Table 94. SPI Slave Timing Specifications ........................................................................................... 124 Table 95: EEPROM Interface Timing ................................................................................................... 124 Table 96: RESET Pin Timing ............................................................................................................... 125 Table 97: RTC Range for Date ............................................................................................................ 125 Table 98: 71M6545/H Power and Ground Pins .................................................................................... 128 v1.0 © 2008–2011 Teridian Semiconductor Corporation 7 Data Sheet 71M6545/H PDS_6545_009 Table 99: 71M6545/H Analog Pins....................................................................................................... 129 Table 100: 71M6545/H Digital Pins ...................................................................................................... 130 Table 101. 71M6545/H Ordering Guide................................................................................................ 132 8 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H VREF IADC0 IADC1 IADC2 IADC3 IADC4 IADC5 IADC6 IADC7 VADC8 VADC9 VADC10 ∆Σ AD CONVERTER MUX and PREAMP VBIAS VBIAS GNDA GNDA GNDD GNDD V3P3SYS V3P3A FIR V3P3A + VREF VREF V3P3D MUX MUX CTRL CROSS Voltage Regulator CK32 RTCLK (32KHz) MCK PLL CK32 32KHz 4.9 MHZ 4.9 MHz DIV ADC XIN XOUT Oscillator 32 KHz CKADC CKFIR 22 2.5V to logic VDD CLOCK GEN CK_4X MUX CKMPU_2x MUX_SYNC CKCE < 4.9MHz CE STRT WPULSE VARPULSE RTM 32-bit Compute Engine MPU RAM (5 KB) MEMORY SHARE TEST TEST MODE CE CONTROL CEDATA 32 0x000...0x2FF 0x0000...0x13FF 8 PROG 0x000...0x3FF 16 WPULSE XFER BUSY CE_BUSY SPI SPI I/F DIGITAL I/O VARPULSE DIO Pins I/O RAM CKMPU < 4.9MHz EEPROM INTERFACE PB RTC RTCLK VBAT_RTC SDCK RX TX UART MPU (80515) SDOUT SDIN Non-Volatile CONFIGURATION RAM CONFIGURATION RAM (I/O RAM) 0x2000...0x20FF 8 MEMORY SHARE 0x0000… FLASH 64 KB 0xFFFF 16 EMULATOR PORT CONFIGURATION PARAMETERS TEMP SENSOR BAT TEST DATA 0x0000...0xFFFF 8 PROGRAM 0x0000...0xFFFF 8 CKMPU_2x VBIAS MPU_RSTZ POWER FAULT DETECTION WAKE RTM FAULTZ VSTAT 3 E_RXTX E_TCLK E_RST(Open Drain) TEST MUX TEST MUX 2 RESET E_RXTX E_TCLK E_RST ICE_E TMUXOUT TMU2XOUT April 2011 Figure 1: IC Functional Block Diagram v1.0 © 2008–2011 Teridian Semiconductor Corporation 9 Data Sheet 71M6545/H PDS_6545_009 1 INTRODUCTION This data sheet covers the 71M6545 (0.5%) and 71M6545H (0.1%) fourth generation Teridian poly-phase Metrology Processors. The term “71M6545/H” is used when discussing a device feature or behavior that is applicable to both part numbers. The appropriate part number is indicated when a device feature or behavior is being discussed that applies only to a specific part number. This data sheet also covers details about the companion 71M6xx3 isolated current sensor device. This document covers the use of the 71M6545/H in conjunction with the 71M6xx3 isolated current sensor. The 71M6545/H and 71M6xx3 ICs make it possible to use one non-isolated and three additional isolated shunt current sensors to create poly-phase energy meters using inexpensive shunt resistors, while achieving unprecedented performance with this type of sensor technology. The 71M6545/H Metrology Processors also support Current Transformers (CT). To facilitate document navigation, hyperlinks are often used to reference figures, tables and section headings that are located in other parts of the document. All hyperlinks in this document are highlighted in blue. Hyperlinks are used extensively to increase the level of detail and clarity provided within each section by referencing other relevant parts of the document. To further facilitate document navigation, this document is published as a PDF document with bookmarks enabled. The reader is also encouraged to obtain and review the documents listed in 8 RELATED INFORMATION on page 132 of this document. 10 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H 2 2.1 HARDWARE DESCRIPTION Hardware Overview The Teridian 71M6545/H single-chip Metrology Processor integrates all primary functional blocks required to implement a solid-state electricity meter. Included on the chip are: • • • • • An analog front end (AFE) featuring a 22-bit second-order sigma-delta ADC An independent 32-bit digital computation engine (CE) to implement DSP functions An 8051-compatible microprocessor (MPU) which executes one instruction per clock cycle (80515) A precision voltage reference (VREF) A temperature sensor for digital temperature compensation: - Metrology digital temperature compensation (MPU) - Automatic RTC digital temperature compensation operational in sleep mode (SLP) RAM and Flash memory A real time clock (RTC) A variety of I/O pins A power failure interrupt (CE code feature) A zero-crossing interrupt (CE code feature) Selectable current sensor interfaces for locally-connected sensors as well as isolated sensors (i.e., using the 71M6xx3 companion IC with a shunt resistor sensor) Resistive Shunt and Current Transformers are supported • • • • • • • In order to implement a poly-phase meter with or without neutral current sensing, one resistive shunt current sensor may be connected directly (non-isolated) to the 71M6545/H device, while three additional current shunts are isolated using a companion 71M6xx3 isolated sensor IC. An inexpensive, small size pulse transformer is used to electrically isolate the 71M6xx3 remote sensor from the 71M6545/H. The 71M6545/H performs digital communications bi-directionally with the 71M6xx3 and also provides power to the 71M6xx3 through the isolating pulse transformer. Isolated (remote) shunt current sensors are connected to the differential input of the 71M6xx3. The 71M6545/H may also be used with Current Transformers; in this case the 71M6xx3 isolated sensors are not required. Included on the 71M6xx3 companion isolator chip are: • • • • • • • Digital isolation communications interface An analog front end (AFE) featuring a 22-bit second-order sigma-delta ADC A precision voltage reference (VREF) A temperature sensor (for current-sensing digital temperature compensation) A f ully differential shunt resistor sensor input A pre-amplifier to optimize shunt current sensor performance Isolated power circuitry obtains dc power from pulses sent by the 71M6545/H In a typical application, the 32-bit compute engine (CE) of the 71M6545/H sequentially processes the samples from the voltage inputs on analog input pins and performs calculations to measure active energy 2 2 (Wh) and reactive energy (VARh), as well as A h, and V h for four-quadrant metering. These measurements are then accessed by the host processor via the SPI or by the on-chip MPU, to be processed further and output using either the peripheral devices available to the on-chip MPU or by the host processor. In addition to advanced measurement functions, the real time clock (RTC) function allows the 71M6545/H to record time of use (TOU) metering information for multi-rate applications and to time-stamp tamper or other events. An automatic RTC temperature compensation circuit operates in all power states including when the MPU is halted, and continues to compensate using back-up battery power during power outages (VBAT_RTC pin). In addition to the temperature-trimmed ultra-precision voltage reference, the on-chip digital temperature compensation mechanism includes a temperature sensor and associated controls for correction of unwanted temperature effects on metrology and RTC accuracy (i.e., to meet the requirements of ANSI and IEC standards). Temperature-dependent external components such as the crystal, current transformers (CTs), Current Shunts and their corresponding signal conditioning circuits can be characterized and their v1.0 © 2008–2011 Teridian Semiconductor Corporation 11 Data Sheet 71M6545/H PDS_6545_009 correction factors can be programmed to produce electricity meters with exceptional accuracy over the industrial temperature range. One of the two internal UARTs is adapted to support an Infrared LED with internal drive and sense configuration and can also function as a standard UART. This flexibility makes it possible to implement AMR meters with an IR interface. A block diagram of the IC is shown in Figure 1. 2.2 Analog Front End (AFE) The AFE functions as a data acquisition system, controlled by the MPU or by the host processor over the SPI interface. The 71M6545/H AFE may also be augmented by isolated 71M6xx3 sensors in order to support low-cost current shunt sensors. Figure 2 and Figure 3 show two of the most common configurations; other configurations are possible. Sensors that are connected directly to the 71M6545/H (i.e., IADC0-IADC1, VADC8, VADC9 and VADC10) are multiplexed into the single second-order sigmadelta ADC input for sampling in the 71M6545/H. The 71M6545/H ADC output is decimated by the FIR filter and stored in CE RAM where it can be accessed and processed by the CE. Shunt current sensors that are isolated by using a 71M6xx3 device, are sampled by a second-order sigma delta ADC in the 71M6xx3 and the signal samples are transferred over the digital isolation interface through the low-cost isolation pulse transformer. Figure 2 shows the 71M6545/H using shunt current sensors and the 71M6xx3 isolated sensor devices. Figure 2 supports neutral current measurement with a local shunt connected to the IADC0-IADC1 input plus three remote (isolated) shunt sensors. As seen in Figure 2, when a remote isolated shunt sensor is connected via the 71M6xx3, the samples associated with this current channel are not routed to the multiplexer, and are instead transferred digitally to the 71M6545/H via the isolation interface and are directly stored in CE RAM. The MUX_SELn[3:0] I/O RAM control fields allow the MPU to configure the AFE for the desired multiplexer sampling sequence. Refer to Table 1 and Table 2 for the appropriate CE code and the corresponding AFE settings. See Figure 27 for the meter wiring configuration corresponding to Figure 2. IN* IADC0 Local Shunt MUX VREF IADC1 VADC8 (VA) VADC9 (VB) VADC10 (VC) IA INP Remote Shunt INN IB INP Remote Shunt INN IC INP Remote Shunt INN 71M6xx3 SN IADC7 SP IADC6 22 VREF ∆Σ ADC CONVERTER VREF VADC FIR 22 SP 71M6xx3 SN IADC2 IADC3 22 CE RAM SP 71M6xx3 SN IADC5 IADC4 Digital Isolation Interface 22 71M6545/H *IN = Neutral Current 10/7/2010 Figure 2: AFE Block Diagram (Shunts: One-Local, Three-Remotes) 12 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H The 71M6545/H AFE can also be directly interfaced to Current Transformers (CTs), as seen in Figure 3. In this case, all voltage and current channels are multiplexed into a single second-order sigma-delta ADC in the 71M6545/H and the 71M6xx3 remote isolated sensors are not used. The fourth CT and the measurement of Neutral current via the IADC0-IADC1 current channel are optional. See Figure 28 for the meter wiring configuration corresponding to Figure 3. VREF IA IADC2 CT IADC3 MUX VREF VADC IB IADC4 CT IADC5 IC IADC6 CT IADC7 IN* IADC0 CT IADC1 ∆Σ ADC CONVERTER VREF FIR 22 CE RAM VADC8 (VA) VADC9 (VB) VADC10 (VC) 71M6545/H *IN = Neutral Current 10/7/2010 Figure 3. AFE Block Diagram (Four CTs) 2.2.1 Signal Input Pins The 71M6545/H features eleven ADC input pins. IADC0 through IADC7 are intended for use as current sensor inputs. These eight current sensor inputs can be configured as eight single-ended inputs, or can be paired to form four differential inputs. For best performance, it is recommended to configure the current sensor inputs as differential inputs (i.e., IADC0IADC1, IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7). The first differential input (IADC0-IADC1) features a pre-amplifier with a selectable gain of 1 or 8, and is intended for direct connection to a shunt resistor sensor, and can also be used with a Current Transformer (CT). The three remaining differential pairs (i.e., IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7) may be used with CTs, or may be enabled to interface to a remote 71M6xx3 isolated current sensor providing isolation for a shunt resistor sensor using a low cost pulse transformer. The remaining three inputs VADC8 (VA), VADC9 (VB) and VADC10 (VC) are single-ended, and are intended for sensing each of the phase voltages in a poly-phase meter application. These three singleended inputs are referenced to the V3P3A pin. All ADC input pins measure voltage. In the case of shunt current sensors, currents are sensed as a voltage drop in the shunt resistor sensor. In the case of Current Transformers (CT), the current is measured as a voltage across a burden resistor that is connected to the secondary of the CT. Meanwhile, line voltages are sensed through resistive voltage dividers. The VADC8 (VA), VADC9 (VB) and VADC10 (VC) pins are single-ended and their common return is the V3P3A pin. See Figure 23, Figure 24, Figure 25 and Figure 26 for detailed connections for each type of sensor. Pins IADC0-IADC1 can be programmed individually to be differential or single-ended as determined by the DIFF0_E (I/O RAM 0x210C[4]) control bit. However, for most applications, IADC0-IADC1 are v1.0 © 2008–2011 Teridian Semiconductor Corporation 13 Data Sheet 71M6545/H PDS_6545_009 configured as a differential input to work with a resistive shunt or CT directly interfaced to the IADC0IADC1 differential input with the appropriate external signal conditioning components. The performance of the IADC0-IADC1 pins can be enhanced by enabling a pre-amplifier with a fixed gain of 8, using the I/O RAM control bit PRE_E (I/O RAM 0x2704[5]). When PRE_E = 1, IADC0-IADC1 become the inputs to the 8x pre-amplifier, and the output of this amplifier is supplied to the multiplexer. The 8x amplification is useful when current sensors with low sensitivity, such as shunt resistors, are used. With PRE_E set, the IADC0-IADC1 input signal amplitude is restricted to 31.25 mV peak. When PRE_E = 0 (Gain = 1), the IADC0-IADC1 input signal is restricted to 250 mV peak. For the 71M6545/H application utilizing shunt resistor sensors (Figure 2), the IADC0-IADC1 pins are configured for differential mode to interface to a local shunt by setting the DIFF0_E control bit. Meanwhile, the IADC2-IADC3 , IADC4-IADC5 and IADC6-IADC7 pins are re-configured as digital remote sensor interface designed to communicate with a Teridian 71M6xx3 isolated sensor by setting the RMTx_E control bits (I/O RAM 0x2709[5:3]). The 71M6xx3 communicates with the 71M6545/H using a bi-directional digital data stream through an isolating low-cost pulse transformer. The 71M6545/H also supplies power to the 71M6xx3 through the isolating transformer. This type of interface is further described at the end of this chapter. See 2.2.8 71M6xx3 Isolated Sensor Interface. For use with Current Transformers (CTs), as shown in Figure 3, the RMTx_E control bits are reset, so that IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7 are configured as local analog inputs. The IADC0-IADC1 pins cannot be configured as a remote sensor interface. 2.2.2 Input Multiplexer When operating with locally connected sensors, the input multiplexer sequentially applies the input signals from the analog input pins to the input of the ADC (see Figure 3), according to the sampling sequence determined by the eleven MUXn_SEL[3:0] control fields. One complete sampling sequence is called a multiplexer frame. The multiplexer of the 71M6545/H can select up to eleven input signals when the current sensor inputs are configured for single-ended mode. When the current sensor inputs are configured in differential mode (recommended for best performance), the number of input signals is seven (i.e., IADC0IADC1, IADC2-IADC3, IADC4-IADC5, IADC6-IADC7, VADC8, VADC9 and VADC10) per multiplexer frame. The number of slots in the multiplexer frame is controlled by the I/O RAM control field MUX_DIV[3:0] (I/O RAM 0x2100[7:4]) (see Figure 4). The multiplexer always starts at state 0 and proceeds until the number of sensor channels determined by the MUX_DIV[3:0] field setting have been converted. The 71M6545/H requires a unique CE code that is written for the specific meter configuration. Moreover, each CE code requires specific AFE and MUX settings in order to function properly. Table 1 provides the CE code and settings corresponding to the 1-Local / 3-Remote sensor configuration shown in Figure 2. Table 2 provides the CE code and settings corresponding to the CT configuration shown in Figure 3. 14 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H T able 1. Required CE Code and Settings for 1-Local / 3-Remotes I/O RAM I/O RAM I/O RAM Setting Comments Mnemonic Location FIR_LEN[1:0] 210C[2:1] 1 288 cycles ADC_DIV 2200[5] 0 Fast PLL_FAST 2200[4] 1 19.66 MHz MUX_DIV[3:0] 2100[7:4] 6 See note 1 MUX0_SEL[3:0] Slot 0 is IADC0-IADC1 2105[3:0] 0 (IN) MUX1_SEL[3:0] 2105[7:4] 1 Unused (See note 2) MUX2_SEL[3:0] 2104[3:0] 1 Unused (See note 2) MUX3_SEL[3:0] Slot 3 is VADC8 2104[7:4] 8 (VA) MUX4_SEL[3:0] Slot 4 is VADC9 2103[3:0] 9 (VB) MUX5_SEL[3:0] Slot 5 is VADC10 2103[7:4] A (VC) MUX6_SEL[3:0] 2102[3:0] 0 MUX7_SEL[3:0] 2102[7:4] 0 MUX8_SEL[3:0] 2101[3:0] 0 Slots not enabled MUX9_SEL[3:0] 2101[7:4] 0 MUX10_SEL[3:0] 2100[3:0] 0 RMT2_E 2709[3] 1 Enable Remote IADC2-IADC3 (IA) RMT4_E 2709[4] 1 Enable Remote IADC4-IADC5 (IB) RMT6_E 2709[5] 1 Enable Remote IADC6-IADC7 (IC) DIFF0_E 210C[4] 1 Differential IADC0-IADC1 (IN) DIFF2_E 210C[5] 0 See note 3 DIFF4_E 210C[6] 0 See note 3 DIFF6_E 210C[7] 0 See note 3 PRE_E 2704[5] 1 IADC0-IADC1 Gain = 8 EQU[2:0] 2106[7:5] 5 IA*VA + IB*VB + IC*VC ce43b016603 (use with 71M6603) CE Codes ce43b016103 (use with 71M6103) (See note 4) ce43b016113 (use with 71M6113) ce43b016203 (use with 71M6203) Equation(s) 5 Current Sensor Type 1 Local Shunt and 3 Remote Shunts Applicable Figures Figure 2 and Figure 27 Notes: 1. MUX_DIV[3:0] should be set to 0 while writing the other values in this table, and then set to the indicated value before writing the MUXn_SEL[3:0] fields. 2. Each unused slot must be assigned to a valid (0 to A), but unused ADC handle 3. This channel is remote (71M6xx3), hence DIFFx_E is irrelevant 4. Must use the CE code that corresponds to the specific 71M6xx3 device used TERIDIAN updates the CE code periodically. Please contact your local TERIDIAN representative to obtain the latest CE code and the associated settings. v1.0 © 2008–2011 Teridian Semiconductor Corporation 15 Data Sheet 71M6545/H PDS_6545_009 T able 2. Required CE Code and Settings for CT Sensors I/O RAM I/O RAM I/O RAM Setting Comments Mnemonic Location (Hex) FIR_LEN[1:0] 210C[2:1] 1 288 cycles ADC_DIV 2200[5] 0 Fast PLL_FAST 2200[4] 1 19.66 MHz MUX_DIV[3:0] 2100[7:4] 7 See note 1 MUX0_SEL[3:0] Slot 0 is IADC2-IADC3 2105[3:0] 2 (IA) MUX1_SEL[3:0] Slot 1 is VADC8 2105[7:4] 8 (VA) MUX2_SEL[3:0] Slot 2 is IADC4-IADC5 2104[3:0] 4 (IB) MUX3_SEL[3:0] Slot 3 is VADC9 2104[7:4] 9 (VB) MUX4_SEL[3:0] Slot 4 is IADC6-IADC7 2103[3:0] 6 (IC) MUX5_SEL[3:0] Slot 5 is VADC10 2103[7:4] A (VC) MUX6_SEL[3:0] 2102[3:0] 0 Slot 6 is IADC0-IADC1 (IN – See note 2) MUX7_SEL[3:0] 2102[7:4] 0 MUX8_SEL[3:0] 2101[3:0] 0 Slots not enabled MUX9_SEL[3:0] 2101[7:4] 0 MUX10_SEL[3:0] 2100[3:0] 0 RMT2_E 2709[3] 0 Local Sensor IADC2-IADC3 RMT4_E 2709[4] 0 Local Sensor IADC4-IADC5 RMT6_E 2709[5] 0 Local Sensor IADC6-IADC7 DIFF0_E 210C[4] 1 Differential IADC0-IADC1 DIFF2_E 210C[5] 1 Differential IADC2-IADC3 DIFF4_E 210C[6] 1 Differential IADC4-IADC5 DIFF6_E 210C[7] 1 Differential IADC6-IADC7 PRE_E 2704[5] 0 IADC0-IADC1 Gain = 1 EQU[2:0] 2106[7:5] 5 IA*VA + IB*VB + IC*VC CE Code ce43a02 Equation(s) 5 Current Sensor Type 4 Current Transformers (CTs) Applicable Figures Figure 3 and Figure 28 Notes: 1. MUX_DIV[3:0] should be set to 0 while writing the other values in this table, and then set to the indicated value before writing the MUXn_SEL[3:0] fields. 2. IN is the optional Neutral Current TERIDIAN updates the CE code periodically. Please contact your local TERIDIAN representative to obtain the latest CE code and the associated settings. Using settings for the I/O RAM Mnemonics listed in Table 1 and Table 2 that do not match those required by the corresponding CE code being used may result in undesirable side effects and must not be selected by the MPU. Consult your local TERIDIAN representative to obtain the correct CE code and AFE / MUX settings corresponding to the application. For a poly-phase configuration with neutral current sensing using shunt resistor current sensors and the 71M6xx3 isolated sensors, as shown in Figure 2, the IADC0-IADC1 input must be configured as a differential input, to be connected to a local shunt (see Figure 26 for the shunt connection details). The local shunt connected to the IADC0-IADC1 input is used to sense the Neutral current. The voltage sensors (VADC8, VADC9 and VADC10) are also directly connected to the 71M6545/H (see Figure 23 for 16 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H the connection details) and are also routed though the multiplexer, as seen in Figure 2. Meanwhile, the IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7 current inputs are configured as remote sensor digital interfaces and the corresponding samples are not routed through the multiplexer. For this configuration, the multiplexer sequence is as shown in Figure 4. For a poly-phase configuration with optional neutral current sensing using Current Transformer (CTs) sensors, as shown in Figure 3, all four current sensor inputs must be configured as a differential inputs, to be connected to their corresponding CTs (see Figure 25 for the differential CT connection details). The IADC0-IADC1 current sensor input is optionally used to sense the Neutral current for anti-tampering purposes. The voltage sensors (VADC8, VADC9 and VADC10) are directly connected to the 71M6545/H (see Figure 23 for the voltage sensor connection details). No 71M6xx3 isolated sensors are used in this configuration and all sensors are routed through the multiplexer, as seen in Figure 3. For this configuration, the multiplexer sequence is as shown in Figure 5. The multiplexer sequence shown in Figure 4, covers the shunt configuration shown in Figure 2. The frame duration is 13 CK32 cycles (where CK32 = 32,768 Hz), therefore, the resulting sample rate is 32,768 Hz / 13 = 2,520.6 Hz. Note that Figure 4 only shows the currents that pass through the 71M6545/H multiplexer, and does not show the currents that are copied directly into CE RAM from the remote sensors (see Figure 2), which are sampled during the second half of the multiplexer frame. The two unused conversion slots shown are necessary to produce the desired 2,520.6 Hz sample rate. Multiplexer Frame MUX_DIV[3:0] = 6 Conversions CK32 MUX STATE CROSS MUX_SYNC S 0 IN Settle 1 Unused 2 Unused 3 VA 4 VB 5 VC S 1 Local / 3 Remotes: Figure 4: States in a Multiplexer Frame (MUX_DIV[3:0] = 6) The multiplexer sequence shown in Figure 5 corresponds to the CT configuration shown in Figure 3. Since in this case all current sensors are locally connected to the 71M6545/H, all currents are routed through the multiplexer, as seen in Figure 3. For this multiplexer sequence, the frame duration is 15 CK32 cycles (where CK32 = 32,768 Hz), therefore, the resulting sample rate is 32,768 Hz / 15 = 2,184.5 Hz. Multiplexer Frame MUX_DIV[3:0] = 7 Conversions CK32 MUX STATE CROSS MUX_SYNC S 0 IA 1 VA 2 IB 3 VB 4 IC 5 VC 6 IN S Settle Figure 5: States in a Multiplexer Frame (MUX_DIV[3:0] = 7) Multiplexer advance, FIR initiation and chopping of the ADC reference voltage (using the internal CROSS signal, see 2.2.7 Voltage References) are controlled by the internal MUX_CTRL circuit. Additionally, MUX_CTRL launches each pass of the CE through its code. Conceptually, MUX_CTRL is clocked by CK32, the 32768 Hz clock from the PLL block. The behavior of the MUX_CTRL circuit is governed by: v1.0 © 2008–2011 Teridian Semiconductor Corporation 17 Data Sheet 71M6545/H • • • • CHOP_E[1:0] (I/O RAM 0x2106[3:2]) MUX_DIV[3:0] (I/O RAM 0x2100[7:4]) FIR_LEN[1:0] (I/O RAM 0x210C[2:1]) ADC_DIV (I/O RAM 0x2200[5] ) PDS_6545_009 The duration of each multiplexer state depends on the number of ADC samples processed by the FIR as determined by the FIR_LEN[1:0] (I/O RAM 0x210C[2:1] control field. Each multiplexer state starts on the rising edge of CK32, the 32-kHz clock. It is recommended that MUX_DIV[3:0] (I/O RAM 0x2200[2:0]) be set to zero while changing the ADC configuration. Although not required, it minimizes system transients that might be caused by momentary shorts between the ADC inputs, especially when changing the DIFFn_E control bits (I/O RAM 0x210C[5:4]). After the configuration bits are set, MUX_DIV[3:0] should be set to the required value. The duration of each time slot in CK32 cycles depends on FIR_LEN[1:0], ADC_DIV and PLL_FAST: Time_Slot_Duration (PLL_FAST = 1) = (FIR_LEN[1:0]+1) * (ADC_DIV+1) Time_Slot_Duration (PLL_FAST = 0) = 3*(FIR_LEN[1:0]+1) * (ADC_DIV+1) The duration of a multiplexer frame in CK32 cycles is: MUX_Frame_Duration = 3-2*PLL_FAST + Time_Slot_Duration * MUX_DIV[3:0] The duration of a multiplexer frame in CK_FIR cycles is: MUX frame duration (CK_FIR cycles) = [3-2*PLL_FAST + Time_Slot_Duration * MUX_DIV] * (48+PLL_FAST*102) The ADC conversion sequence is programmable through the MUXn_SEL control fields (I/O RAM 0x2100 to 0x2105). As stated above, there are up to eleven ADC time slots in the 71M6545/H, as set by MUX_DIV[3:0] (I/O RAM 0x2100[7:4]). In the expression MUXn_SEL[3:0] = x, ‘n’ refers to the multiplexer frame time slot number and ‘x’ refers to the desired ADC input number or ADC handle (i.e., IADC0 to VADC10, or simply 0 to 10 decimal). Thus, there are a total of 11 valid ADC handles in the 71M6545/H devices. For example, if MUX0_SEL[3:0] = 0, then IADC0, corresponding to the sample from the IADC0-IADC1 input (configured as a differential input), is positioned in the multiplexer frame during time slot 0. See Table 1 and Table 2 for the appropriate MUXn_SEL[3:0] settings and other settings applicable to a particular meter configuration and CE code. Note that when the remote sensor interface is enabled, the samples corresponding to the remote sensor currents do not pass through the 71M6545/H multiplexer. The sampling of the remote current sensors occurs in the second half of the multiplexer frame. The VA, VB and VC voltages are assigned the last three slots in the frame. With this slot assignment for VA, VB and VC, the sampling of the corresponding remote sensor currents bears a precise timing relationship to their corresponding phase voltages, and delay compensation is accurately performed (see 2.2.3 Delay Compensation on page 19). Also when using remote sensors, it is necessary to introduce unused slots to realize the number of slots specified by the MUX_DIV[3:0] (I/O RAM 0x2100[7:4] ) field setting (see Figure 4 and Figure 5). The MUXn_SEL[3:0] control fields for these unused (“dummy”) slots must be written with a valid ADC handle (i.e., 0 to 10 decimal) that is not otherwise being used. In this manner, the unused ADC handle, is used as a “dummy” place holder in the multiplexer frame, and the correct duration multiplexer frame sequence is generated and also the desired sample rate. The resulting sample data stored in the CE RAM location corresponding to the “dummy” ADC handle is ignored by the CE code. Meanwhile, the digital isolation interface takes care of automatically storing the samples for the remote current sensors in the appropriate CE RAM locations. Delay compensation and other functions in the CE code require the settings for MUX_DIV[3:0], MUXn_SEL[3:0], RMT_E, FIR_LEN[1:0], ADC_DIV and PLL_FAST to be fixed for a given CE code. Refer to Table 1 and Table 2 for the settings that are applicable to the 71M6545/H. 18 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H Table 3 summarizes the I/O RAM registers used for configuring the multiplexer, signals pins, and ADC. All listed registers are 0 after reset and wake from SLP mode, and are readable and writable. T able 3: Multiplexer and ADC Configuration Bits Name MUX0_SEL[3:0] MUX1_SEL[3:0] MUX2_SEL[3:0] MUX3_SEL[3:0] MUX4_SEL[3:0] MUX5_SEL[3:0] MUX6_SEL[3:0] MUX7_SEL[3:0] MUX8_SEL[3:0] MUX9_SEL[3:0] MUX10_SEL[3:0] ADC_DIV MUX_DIV[3:0] PLL_FAST FIR_LEN[1:0] DIFF0_E DIFF2_E DIFF4_E DIFF6_E Location 2105[3:0] 2105[7:4] 2104[3:0] 2104[7:4] 2103[3:0] 2103[7:4] 2102[3:0] 2102[7:0] 2101[3:0] 2101[7:0] 2100[3:0] 2200[5] 2100[7:4] 2200[4] 210C[2:1] 210C[4] 210C[5] 210C[6] 210C[7] Description Selects the ADC input converted during time slot 0. Selects the ADC input converted during time slot 1. Selects the ADC input converted during time slot 2. Selects the ADC input converted during time slot 3. Selects the ADC input converted during time slot 4. Selects the ADC input converted during time slot 5. Selects the ADC input converted during time slot 6. Selects the ADC input converted during time slot 7. Selects the ADC input converted during time slot 8. Selects the ADC input converted during time slot 9. Selects the ADC input converted during time slot 10. Controls the rate of the ADC and FIR clocks. The number of ADC time slots in each multiplexer frame (maximum = 11). Controls the speed of the PLL and MCK. Determines the number of ADC cycles in the ADC decimation FIR filter. Enables the differential configuration for analog input pins IADC0-IADC1 . Enables the differential configuration for analog input pins IADC2-IADC3 . Enables the differential configuration for analog input pins IADC4-IADC5 . Enables the differential configuration for analog input pins IADC6-IADC7 . Enables the remote sensor interface transforming pins IADC2-IADC3 into a digital RMT2_E 2709[3] interface for communications with a 71M6xx3 sensor. Enables the remote sensor interface transforming pins IADC4-IADC5 into a digital RMT4_E 2709[4] interface for communications with a 71M6xx3 sensor. Enables the remote sensor interface transforming pins IADC6-IADC7 into a digital RMT6_E 2709[5] interface for communications with a 71M6xx3 sensor. PRE_E 2704[5] Enables the 8x pre-amplifier. Refer to Table 61 starting on page 88 for more complete details about these I/O RAM locations. 2.2.3 Delay Compensation W hen measuring the energy of a phase (i.e., Wh and VARh) in a service, the voltage and current for that phase must be sampled at the same instant. Otherwise, the phase difference, Ф, introduces errors. φ= t delay T ⋅ 360 o = t delay ⋅ f ⋅ 360 o W here f is the frequency of the input signal, T = 1/f and tdelay is the sampling delay between current and voltage. Traditionally, sampling is accomplished by using two A/D converters per phase (one for voltage and the other one for current) controlled to sample simultaneously. Teridian’s Single-Converter Technology®, however, exploits the 32-bit signal processing capability of its CE to implement “constant delay” all-pass filters. The all-pass filter corrects for the conversion time difference between the voltage and the corresponding current samples that are obtained with a single multiplexed A/D converter. o The “constant delay” all-pass filter provides a broad-band delay 360 - θ, that is precisely matched to the difference in sample time between the voltage and the current of a given phase. This digital filter does not affect the amplitude of the signal, but provides a precisely controlled phase response. The recommended ADC multiplexer sequence samples the current first, immediately followed by sampling of the corresponding phase voltage, thus the voltage is delayed by a phase angle Ф relative to the current. The delay compensation implemented in the CE aligns the voltage samples with their corresponding current samples by first delaying the current samples by one full sample interval (i.e., v1.0 © 2008–2011 Teridian Semiconductor Corporation 19 Data Sheet 71M6545/H PDS_6545_009 360o), then routing the voltage samples through the all-pass filter, thus delaying the voltage samples by 360o - θ, resulting in the residual phase error between the current and its corresponding voltage of θ – Ф. The residual phase error is negligible, and is typically less than ±1.5 milli-degrees at 100Hz, thus it does not contribute to errors in the energy measurements. When using remote sensors, the CE performs the same delay compensation described above to align each voltage sample with its corresponding current sample. Even though the remote current samples do not pass through the 71M6545/H multiplexer, their timing relationship to their corresponding voltages is fixed and precisely known, provided that the MUXn_SEL[3:0] slot assignment fields are programmed as shown in Table 1. Note that these slot assignments result in VA, VB and VC occupying multiplexer slots 3, 4 and 5, respectively (see Figure 4). 2.2.4 ADC Pre-Amplifier The ADC pre-amplifier is a low-noise differential amplifier with a fixed gain of 8 available only on the IADC0-IADC1 sensor input pins. A gain of 8 is enabled by setting PRE_E = 1 (I/O RAM 0x2704[5]). When disabled, the supply current of the pre-amplifier is =1 S1CON.1 (TI1) byte transmitted IEN0.1 (ET0) Timer 0 XPULSE YPULSE 2 WPULSE VPULSE 1 3 DIO CE_BUSY overflow occurred TCON.5 (TF0) IE_XPULSE IE_YPULSE IE_WPULSE IE_VPULSE TCON.3 (IE1) I3FR CE detected zero crossing CE detected sag Wh pulse VARh pulse DIO status changed EX_XPULSE EX_YPULSE EX_WPULSE EX_VPULSE DIO_Rn IEN1.1 (EX2) >=1 I2FR IRCON.1 (IEX2) IP1.1/ IP0.1 IEN0.2 (EX1) IEN1.2 (EX3) IP1.2/ IP0.2 CE completed code run and has new status information overflow occurred IRCON.2 (IEX3) IEN0.3 (ET1) Timer 1 TCON.7 (TF1) IEN1.3 (EX4) IP1.3/ IP0.3 4 VSTAT Supply status changed IRCON.3 (IEX4) S0CON.0 (RI0) >=1 S0CON.0 (TI0) IE_EEX >=1 IE_SPI IEN1.5 (EX6) IRCON.5 (IEX6) >=1 IP1.5/ IP0.5 IRCON.4 (IEX5) IEN0.4 (ES0) IEN1.4 (EX5) IP1.4/ IP0.4 byte received UART0 byte transmitted BUSY fell command received accumulation cycle completed every second every minute EEPROM 5 SPI EX_EEX EX_SPI XFER_BUSY EX_XFER EX_RTC1S EX_RTC1M EX_RTCT IE_XFER IE_RTC1S IE_RTC1M IE_RTCT RTC_1S 6 RTC_1M RTC_T alarm clock Flag=1 means that an interrupt has occurred and has not been cleared EX0 – EX6 are cleared automaticallywhen the hardware vectors to the interrupt handler Interrupt Vector 3/19/2010 Figure 12: Interrupt Structure v1.0 © 2008–2011 Teridian Semiconductor Corporation 45 Polling Sequence byte received IEN2.0 (ES1) IP1.0/ IP0.0 PDS_6545_009 Data Sheet 71M6545/H 2.5 2.5.1 On-Chip Resources Physical Memory 2.5.1.1 Flash Memory The 71M6545/H includes 64 KB of on-chip flash memory. The flash memory primarily contains MPU and CE program code. It also contains images of the CE RAM and I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations. Flash space allocated for the CE program is limited to 4096 16-bit words (8 KB). The CE program must begin on a 1-KB boundary of the flash address space. The CE_LCTN[5:0] (I/O RAM 0x2109[5:0]) field defines which 1-KB boundary contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[5:0]. Flash memory can be accessed by the MPU, the CE, and by the SPI interface (R/W). T able 37: Flash Memory Access Access by MPU CE SPI Flash Write Procedures If the FLSH_UNLOCK[3:0] (I/O RAM 0x2702[7:4]) key is correctly programmed, the MPU may write to the flash memory. This is one of the non-volatile storage options available to the user in addition to external EEPROM. The flash program write enable bit, FLSH_PSTWR (SFR 0xB2[0]), differentiates 80515 data store instructions (MOVX@DPTR,A) between Flash and XRAM writes. This bit is automatically cleared by hardware after each byte write operation. Write operations to this bit are inhibited when interrupts are enabled. If the CE is enabled (CE_E = 1, I/O RAM 0x2106[0]), flash write operations must not be attempted unless FLSH_PSTWR is set. This bit enables the “posted flash write” capability. FLSH_PSTWR has no effect when CE_E = 0). When CE_E = 1, however, FLSH_PSTWR delays a flash write until the time interval between the CE code passes. During this delay time, the FLSH_PEND (SFR 0xB2[3]) bit is high, and the MPU continues to execute commands. When the CE code pass ends (CE_BUSY falls), the FLSH_PEND bit falls and the write operation occurs. The MPU can query the FLSH_PEND bit to determine when the write operation has been completed. While FLSH_PEND = 1, further flash write requests are ignored. Updating Individual Bytes in Flash Memory The original state of a flash byte is 0xFF (all bits are 1). Once a value other than 0xFF is written to a flash memory cell, overwriting with a different value usually requires that the cell be erased first. Since cells cannot be erased individually, the page has to be first copied to RAM, followed by a page erase. After this, the page can be updated in RAM and then written back to the flash memory. Flash Erase Procedures Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence. These special pattern/sequence requirements prevent inadvertent erasure of the flash memory. The mass erase sequence is: • • W rite 1 to the FLSH_MEEN bit (SFR 0xB2[1]). W rite the pattern 0xAA to the FLSH_ERASE (SFR 0x94) register. The mass erase cycle can only be initiated when the ICE port is enabled. Access Type R/W/E R R/W/E Condition W/E only if CE is disabled. Access only when SFM is invoked (MPU halted). v1.0 © 2008–2011 Teridian Semiconductor Corporation 46 PDS_6545_009 The page erase sequence is: • • W rite the page address to FLSH_PGADR[6:0] (SFR 0xB7[7:1]). W rite the pattern 0x55 to the FLSH_ERASE register (SFR 0x94). Data Sheet 71M6545/H Program Security When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE operations, such as reading via the SPI or ICE port, are blocked. This guarantees the security of the user’s MPU and CE program code. Security is enabled by MPU code that is executed in a 64 CKMPU cycle pre-boot interval before the primary boot sequence begins. Once security is enabled, the only way to disable it is to perform a global erase of the flash, followed by a chip reset. The first 60 cycles of the MPU boot code are called the pre-boot phase because during this phase the ICE is inhibited. A read-only status bit, PREBOOT (SFR 0xB2[7]), identifies these cycles to the MPU. Upon completion of pre-boot, the ICE can be enabled and is permitted to take control of the MPU. The security enable bit, SECURE (SFR 0xB2[6]), is reset whenever the chip is reset. Hardware associated with the bit allows only ones to be written to it. Thus, pre-boot code may set SECURE to enable the security feature but may not reset it. Once SECURE is set, the pre-boot and CE code are protected from erasure, and no external read of program code is possible. Specifically, when the SECURE bit is set, the following applies: • • • The ICE is limited to bulk flash erase only. Page zero of flash memory, the preferred location for the user’s pre-boot code, may not be page-erased by either MPU or ICE. Page zero may only be erased with global flash erase. W rite operations to page zero, whether by MPU or ICE are inhibited. The 71M6545/H also includes hardware to protect against unintentional Flash write and erase. To enable flash write and erase operations, a 4-bit hardware key that must be written to the FLSH_UNLOCK[3:0] field. The key is the binary number ‘0010’. If FLSH_UNLOCK[3:0] is not ‘0010’, the Flash erase and write operation is inhibited by hardware. Proper operation of this security key requires that there be no firmware function that writes ‘0010’ to FLSH_UNLOCK[3:0]. The key should be written by the external SPI master, in the case of SPI flash programming (SFM mode), or through the ICE interface in the case of ICE flash programming. When a boot loader is used, the key should be sent to the boot load code which then writes it to FLSH_UNLOCK[3:0]. FLSH_UNLOCK[3:0] is not automatically reset. It should be cleared when the SPI or ICE has finished changing the Flash. Table 38 summarizes the I/O RAM registers used for flash security. T able 38: Flash Security Name FLSH_UNLOCK[3:0] Location 2702[7:4] Rst 0 Wk 0 Dir R/W Description SECURE SFR B2[6] 0 0 R/W Must be a 2 to enable any flash modification. See the description of Flash security for more details. Inhibits erasure of page 0 and flash addresses above the beginning of CE code as defined by CE_LCTN[5:0](I/O RAM 0x2109[5:0]). Also inhibits the read of flash via the ICE and SPI ports. SPI Flash Mode In normal operation, the SPI slave interface cannot read or write the flash memory. However, the 71M6545/H contains a Special Flash Mode (SFM) that facilitates initial (production) programming of the flash memory. When the 71M6545/H is in SFM mode, the SPI interface can erase, read, and write the flash. Other memory elements such as XRAM and I/O RAM are not accessible to the SPI in this mode. In order to protect the flash contents, several operations are required before the SFM mode is successfully invoked. Details on the SFM can be found in 2.5.12 SPI Slave Port. v1.0 © 2008–2011 Teridian Semiconductor Corporation 47 Data Sheet 71M6545/H 2.5.1.2 MPU/CE RAM PDS_6545_009 The 71M6545/H includes 5 KB of static RAM memory on-chip (XRAM) plus 256 bytes of internal RAM in the MPU core. The 5KB of static RAM are used for data storage by both MPU and CE and for the communication between MPU and CE. 2.5.1.3 I/O RAM (Configuration RAM) The I/O RAM can be seen as a series of hardware registers that control basic hardware functions. I/O RAM address space starts at 0x2000. The registers of the I/O RAM are listed in Table 59. The 71M6545/H includes 128 bytes non-volatile RAM memory on-chip in the I/O RAM address space (addresses 0x2800 to 0x287F). This memory section is supported by the voltage applied at VBAT_RTC, and the data in it are preserved in SLP mode provided that the voltage at the VBAT_RTC pin is within specification. 2.5.2 Oscillator The 71M6545/H oscillator drives a standard 32.768 kHz watch crystal. This type of crystal is accurate and does not require a high-current oscillator circuit. The oscillator has been designed specifically to handle watch crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery attached to VBAT_RTC. Oscillator calibration can improve the accuracy of both the RTC and metering. Refer to 2.5.4, Real-Time Clock (RTC) for more information. The oscillator is powered from the V3P3SYS pin or from the VBAT_RTC pin, depending on the V3OK internal bit (i.e., V3OK = 1 if V3P3SYS ≥ 2.8 VDC and V3OK = 0 if V3P3SYS < 2.8 VDC). The oscillator requires approximately 100 nA, which is negligible compared to the internal leakage of a battery. If VBAT_RTC is connected to a drained battery or disconnected, a battery test that sets TEMP_BAT may drain the supply connected to VBAT_RTC and cause the oscillator to stop. A stopped oscillator may force the device to reset. Therefore, an unexpected reset during a battery test should be interpreted as a battery failure. 2.5.3 PLL and Internal Clocks Timing for the device is derived from the 32.768 kHz crystal oscillator output that is multiplied by a PLL by 600 to obtain 19.660800 MHz, the master clock (MCK). All on-chip timing, except for the RTC clock, is derived from MCK. Table 39 provides a summary of the clock functions and their controls. The two general-purpose counter/timers contained in the MPU are controlled by CKMPU (see 2.4.8 Timers and Counters). The master clock can be boosted to 19.66 MHz by setting the PLL_FAST bit = 1 (I/O RAM 0x2200[4]) and can be reduced to 6.29 MHz by PLL_FAST = 0. The MPU clock frequency CKMPU is determined by another divider controlled by the I/O RAM control field MPU_DIV[2:0] (I/O RAM 0x2200[2:0]) and can be -( MPU_DIV+2) where MPU_DIV[2:0] may vary from 0 to 4. When the ICE_E pin is high, the set to MCK*2 circuit also generates the 9.83 MHz clock for use by the emulator. When the part is waking up from SLP mode, the PLL is turned on in 6.29 MHz mode, and the PLL frequency is not be accurate until the PLL_OK (SFR 0xF9[4]) flag rises. Due to potential overshoot, the MPU should not change the value of PLL_FAST until PLL_OK is true. 48 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 T able 39: Clock System Summary Clock OSC MCK CKCE CKADC CKMPU CKICE CKOPTMOD CK32 Derived From Crystal Crystal/PLL MCK MCK MCK MCK MCK MCK Fixed Frequency or Range PLL_FAST=1 PLL_FAST=0 Data Sheet 71M6545/H Controlled by Function 32.768 kHz – Crystal clock 19.660800 MHz 6.291456 MHz PLL_FAST Master clock (600*CK32) (192*CK32) 4.9152 MHz 1.5728 MHz – CE clock 1.572864 MHz, 4.9152 MHz, ADC_DIV ADC clock 2.4576 MHz 0.786432 MHz 4.9152 MHz … 1.572864 MHz… MPU_DIV[2:0] MPU clock 307.2 kHz 98.304 kHz 9.8304 MHz… 3.145728 MHz … MPU_DIV[2:0] ICE clock 196.608 kHz 614.4 kHz Optical UART 38.40 kHz 38.6 kHz – Modulation 32.768 kHz – 32 kHz clock 2.5.4 Real-Time Clock (RTC) 2.5.4.1 RTC General Description The RTC is driven directly by the crystal oscillator and is powered by either the V3P3SYS pin or the VBAT_RTC pin, depending on the V3OK internal bit. The RTC consists of a counter chain and output registers. The counter chain consists of registers for seconds, minutes, hours, day of week, day of month, month, and year. The chain registers are supported by a shadow register that facilitates read and write operations. Table 40 shows the I/O RAM registers for accessing the RTC. 2.5.4.2 Accessing the RTC Two bits, RTC_RD (I/O RAM 0x2890[6] ) and RTC_WR (I/O RAM 0x2890[7]), control the behavior of the shadow register. When RTC_RD is low, the shadow register is updated by the RTC after each two milliseconds. When RTC_RD is high, this update is halted and the shadow register contents become stationary and are suitable to be read by the MPU. Thus, when the MPU wishes to read the RTC, it freezes the shadow register by setting the RTC_RD bit, reads the shadow register, and then lowers the RTC_RD bit to let updates to the shadow register resume. Since the RTC clock is only 500 Hz, there may be a delay of approximately 2 ms from when the RTC_RD bit is lowered until the shadow register receives its first update. Reads to RTC_RD continues to return a one until the first shadow update occurs. When RTC_WR is high, the update of the shadow register is also inhibited. During this time, the MPU may overwrite the contents of the shadow register. When RTC_WR is lowered, the shadow register is written into the RTC counter on the next 500Hz RTC clock. A ‘change’ bit is included for each word in the shadow register to ensure that only programmed words are updated when the MPU writes a zero to RTC_WR. Reads of RTC_WR returns one until the counter has actually been updated by the register. The sub-second register of the RTC, RTC_SBSC (I/O RAM 0x2892), can be read by the MPU after the one second interrupt and before reaching the next one second boundary. RTC_SBSC contains the count since the last full second, in 1/128 second nominal clock periods, until the next one-second boundary. When the RST_SUBSEC bit is written, the SUBSEC counter is restarted, counting from 0 to 127. Reading and resetting the sub-second counter can be used as part of an algorithm to accurately set the RTC. The RTC is capable of processing leap years. Each counter has its own output register. The RTC chain registers are not be affected by the reset pin, watchdog timer resets, or by transitions between the SLP mode and mission mode. v1.0 © 2008–2011 Teridian Semiconductor Corporation 49 Data Sheet 71M6545/H T able 40: RTC Control Registers Name RTCA_ADJ[6:0] RTC_P[16:14] RTC_P[13:6] RTC_P[5:0] RTC_Q[1:0] RTC_RD Location 2504[6:0] 289B[2:0] 289C[7:0] 289D[7:2] 289D[1:0] 2890[6] Rst 40 4 0 0 0 0 Wk -4 0 0 0 0 Dir R/W R/W Description PDS_6545_009 Register for analog RTC frequency adjustment. Registers for digital RTC adjustment. 0x0FFBF ≤ RTC_P ≤ 0x10040 Register for digital RTC adjustment. Freezes the RTC shadow register so it is suitable for MPU reads. When RTC_RD is read, it returns the status of the shadow register: 0 = up to date, 1 = frozen. Freezes the RTC shadow register so it is suitable for MPU write operations. When RTC_WR is cleared, the contents of the shadow register are written to the RTC counter on the next RTC clock (~1 kHz). When RTC_WR is read, it returns 1 as long as RTC_WR is set, and continues to return one until the RTC counter is updated. Indicates that a count error has occurred in the RTC and that the time is not trustworthy. This bit can be cleared by writing a 0. Time remaining since the last 1 second boundary. LSB = 1/128 second. R/W R/W RTC_WR 2890[7] 0 0 R/W RTC_FAIL RTC_SBSC[7:0] 2890[4] 2892[7:0] 0 0 R/W R 2.5.4.3 RTC Rate Control The 71M6545/H has two rate adjustment mechanisms: • • The first rate adjustment mechanism is an analog rate adjustment, using the I/O RAM register RTCA_ADJ[6:0], that trims the crystal load capacitance. The second rate adjustment mechanism is a digital rate adjust that affects the way the clock frequency is processed in the RTC. Setting RTCA_ADJ[6:0] to 00 minimizes the load capacitance, maximizing the oscillator frequency. Setting RTCA_ADJ[6:0] to 0x7F maximizes the load capacitance, minimizing the oscillator frequency. The adjustable capacitance is approximately: C ADJ = RTCA _ ADJ ⋅ 16.5 pF 128 The precise amount of adjustment depends on the crystal properties, the PCB layout and the value of the external crystal capacitors. The adjustment may occur at any time, and the resulting clock frequency should be measured over a one-second interval. The second rate adjustment is digital, and can be used to adjust the clock rate up to ±988ppm, with a resolution of 3.8 ppm (±1.9 ppm). The rate adjustment is implemented starting at the next secondboundary following the adjustment. Since the LSB results in an adjustment every four seconds, the frequency should be measured over an interval that is a multiple of four seconds. The clock rate is adjusted by writing the appropriate values to RTC_P[16:0] (I/O RAM 0x289B[2:0], 0x289C, 0x289D[7:2]) and RTC_Q[1:0] (I/O RAM 0x289D[1:0]). Updates to RTC rate adjust registers, RTC_P and RTC_Q, are done through the shadow register described above. The new values are loaded into the counters when RTC_WR (I/O RAM 0x2890[7]) is lowered. The default frequency is 32,768 RTCLK cycles per second. To shift the clock frequency by ∆ ppm, RTC_P and RTC_Q are calculated using the following equation: 50 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H  32768 ⋅ 8  + 0.5  4 ⋅ RTC_P + RTC_Q = floor  −6  1 + ∆ ⋅10  Conversely, the amount of ppm shift for a given value of 4RTC_P+RTC_Q is:   32768 ⋅ 8 − 1 ⋅ 106 ∆ ( ppm) =    4 ⋅ RTCP + RTCQ   For example, for a shift of -988 ppm, 4 ⋅ RTC_P + RTC_Q = 262403 = 0x40103. RTC_P[16:0] = 0x10040, (I/O RAM 0x289B[2:0], 0x289C, 0x289D[7:2]) and RTC_Q[1:0] = 0x03 (I/O RAM 0x289D[1:0]. The default values of RTC_P[16:0] and RTC_Q[1:0], corresponding to zero adjustment, are 0x10000 and 0x0, respectively. Two settings for the TMUX2OUT test pin, PULSE_1S and PULSE_4S, are available for measuring and calibrating the RTC clock frequency. These are waveforms of approximately 25% duty cycle with 1s or 4s period. Default values for RTCA_ADJ[6:0] , RTC_P[16:0] and RTC_Q[1:0] should be nominal values, at the center of the adjustment range. Uncalibrated extreme values (zero, for example) can cause incorrect operation. If the crystal temperature coefficient is known, the MPU can integrate temperature and correct the RTC time as necessary. Alternatively, the characteristics can be loaded into an NV RAM and the OSC_COMP (I/O RAM 0x28A0[5]) bit may be set. In this case, the oscillator is adjusted automatically, even in SLP mode. See 2.5.4.4 RTC Temperature Compensation for details. 2.5.4.4 RTC Temperature Compensation The 71M6545/H can be configured to regularly measure die temperature, including in SLP mode, provided that the VBAT_RTC pin is supplied with a voltage within specification provided by a battery. If enabled by OSC_COMP, this temperature information is automatically used to correct for the temperature variation of the crystal. A table lookup method is used. Table 41 shows I/O RAM registers involved in automatic RTC temperature compensation. T able 41: I/O RAM Registers for RTC Temperature Compensation Name OSC_COMP STEMP[10:3] STEMP[2:0] LKPADDR[6:0] Location 28A0[5] 2881[7:0] 2882[7:5] 2887[6:0] Rst 0 – 0 Wk 0 – 0 Dir R/W R R/W Description Enables the automatic update of RTC_P[16:0] and RTC_Q[1:0] every time the temperature is measured. The result of the temperature measurement (10-bits of magnitude data plus a sign bit). The address for reading and writing the RTC lookup RAM. Auto-increment flag. When set, LKPADDR[6:0] auto increments every time LKP_RD or LKP_WR is pulsed. The incremented address can be read at LKPADDR[6:0]. The data for reading and writing the RTC lookup RAM. Strobe bits for the RTC lookup RAM read and write. When set, the LKPADDR[6:0] and LKPDAT registers are used in a read or write operation. When a strobe is set, it stays set until the operation completes, at which time the strobe is cleared and LKPADDR[6:0] is incremented if LKPAUTOI is set. LKPAUTOI 2887[7] 0 0 R/W LKPDAT[7:0] 2888[7:0] 0 0 R/W LKP_RD LKP_WR 2889[1] 2889[0] 0 0 0 0 R/W R/W Referring to Figure 13 the table lookup method uses the 10-bits plus sign-bit value in STEMP[10:0] right-shifted by two bits to obtain an 8-bit plus sign value (i.e., NV RAM Address = STEMP[10:0]/4). A limiter ensures that the resulting look-up address is in the 6-bit plus sign range of -64 to +63 (decimal). v1.0 © 2008–2011 Teridian Semiconductor Corporation 51 Data Sheet 71M6545/H PDS_6545_009 The 8-bit NV RAM content pointed to by the address is added as a 2’s complement value to 0x40000, the nominal value of 4*RTC_P[16:0] + RTC_Q[1:0]. Refer to 2.5.4.3 RTC Rate Control for information on the rate adjustments performed by registers RTC_P[16:0] and RTC_Q[1:0]. The 8-bit values loaded in to NV RAM must be scaled correctly to produce rate adjustments that are consistent with the equations given in 2.5.4.3 RTC Rate Control for RTC_P[16:0] and RTC_Q[1:0]. Note that the sum of the looked-up 8-bit 2’s complement value and 0x40000 form a 19bit value, which is equal to 4*RTC_P[16:0] + RTC_Q[1:0], as shown in Figure 13. The output of the Temperature Compensation is automatically loaded into the RTC_P[16:0] and RTC_Q[1:0] locations after each look-up and summation operation. LIMIT STEMP 10+S >>2 8+S 63 Look Up RAM ADDR 63 255 -256 -64 -64 6+S Q 7+S 19 Σ 19 4*RTC_P+RTC_Q 0x40000 Figure 13: Automatic Temperature Compensation As mentioned above, the STEMP[10:0] digital temperature values are scaled such that the corresponding NV RAM addresses are equal to STEMP[10:0]/4 (limited in the range of -64 to +63). See 2.5.5 71M6545/H Temperature Sensor on page 53 for the equations to calculate temperature in degrees °C from the STEMP[10:0] reading. For proper operation, the MPU has to load the lookup table with values that reflect the crystal properties with respect to temperature, which is typically done once during initialization. Since the lookup table is not directly addressable, the MPU uses the following procedure to load the NV RAM table: 1. Set the LKPAUTOI bit (I/O RAM 0x2887[7]) to enable address auto-increment. 2. Write zero into the I/O RAM register LKPADDR[6:0] (I/O RAM 0x2887[6:0]). 3. Write the 8-bit datum into I/O RAM register LKPDAT (I/O RAM 0x2888). 4. Set the LKP_WR bit (I/O RAM 0x2889[0]) to write the 8-bit datum into NV_RAM 5. Wait for LKP_WR to clear (LKP_WR auto-clears when the data has been copied to NV RAM). 6. Repeat steps 3 through 5 until all data has been written to NV RAM. The NV RAM table can also be read by writing a 1 into the LKP_RD bit (I/O RAM 0x2889[1]). The process of reading from and writing to the NV RAM is accelerated by setting the LKPAUTOI bit (I/O RAM 0x2887[7]). When LKPAUTOI is set, LKPADDR[6:0] (I/O RAM 0x2887[6:0]) auto-increments every time LKP_RD or LKP_WR is pulsed. It is also possible to perform random access of the NV RAM by writing a 0 to the LKPAUTOI bit and loading the desired address into LKPADDR[6:0]. If the oscillator temperature compensation feature is not being used, it is possible to use the NV RAM storage area as ordinary battery-backed NV storage space using the procedure described above to read and write NV RAM data. In this case, the OSC_COMP bit (I/O RAM 0x28A0[5]) is reset to disable the automatic oscillator temperature compensation feature. 2.5.4.5 RTC Interrupts The RTC generates interrupts each second and each minute. These interrupts are called RTC_1SEC and RTC_1MIN. In addition, the RTC functions as an alarm clock by generating an interrupt when the minutes and hours registers both equal their respective target counts. The alarm clock interrupt is called RTC_T. All three interrupts appear in the MPU’s external interrupt 6. See Table 31 in the interrupt section for the enable bits and flags for these interrupts. The minute and hour target registers are listed in Table 42. T able 42: I/O RAM Registers for RTC Interrupts 52 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Name Location Rst RTC_TMIN[5:0] 289E[5:0] 0 RTC_THR[4:0] 289F[4:0] 0 Wk 0 0 Dir Description Data Sheet 71M6545/H R/W The target minutes register. See below. The target hours register. The RTC_T interrupt occurs R/W when RTC_MIN[5:0] becomes equal to RTC_TMIN[5:0] and RTC_HR[4:0] becomes equal to RTC_THR[4:0]. 2.5.5 71M6545/H Temperature Sensor T he 71M6545/H includes an on-chip temperature sensor for determining the temperature of its bandgap reference. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system for the compensation of current, voltage and energy measurement and the RTC. See 4.5 Metrology Temperature Compensation on page 74. Also see 2.5.4.4 RTC Temperature Compensation on page 51. The temperature sensor can be used to compensate for the frequency variation of the crystal, during ac power outages, provided the VBAT_RTC voltage is within specification (supplied by a battery). See 2.5.4.4 RTC Temperature Compensation on page 51. In MSN mode, the temperature sensor is awakened on command from the MPU by setting the TEMP_START (I/O RAM 0x28B4[6]) control bit. During power outages and while operating from VBAT_RTC power, it is awakened at a regular rate set by TEMP_PER[2:0] (I/O RAM 0x28A0[2:0]). The result of the temperature measurement can be read from the two I/O RAM locations STEMP[10:3] (I/O RAM 0x2881) and STEMP[2:0] (I/O RAM 0x2882[7:5]). Note that both of these I/O RAM locations must be read and properly combined to form the STEMP[10:0] 11-bit value (see STEMP in Table 43). The resulting 11-bit value is in 2’s complement form and ranges from -1024 to +1023 (decimal). The equations below are used to calculate the sensed temperature from the 11-bit STEMP[10:0] reading. For the 71M6545 in MSN Mode (with TEMP_PWR = 1): Temp( o C ) = 0.325 ⋅ STEMP + 22 For the temperature sensors in the 71M6545H: If STEMP ≤ 0: ������������������������(℃) = 0.325 ∙ ������������������������������ + 0.00218 ∙ ������������������������������������ 2 − 0.609 ∙ ������������������������������������ + 64.4 ������������������������(℃) = 63 ∙ ������������������������������ + 0.00218 ∙ ������������������������������������2 − 0.609 ∙ ������������������������������������ + 64.4 ������������������������_85 If STEMP > 0: The TEMP_85[10:0] trim fuses are read from the Info Page. See 5.3 Reading the Info Page (71M6545H only) on page 98 for information on how to read the 71M6545H trim fuses. Table 43 shows the I/O RAM registers used for temperature and battery measurement. If TEMP_PWR selects VBAT_RTC when the battery is nearly discharged, the temperature measurement may not finish. In this case, firmware may complete the measurement by selecting V3P3D (TEMP_PWR = 1). v1.0 © 2008–2011 Teridian Semiconductor Corporation 53 Data Sheet 71M6545/H PDS_6545_009 T able 43: I/O RAM Registers for Temperature and Battery Measurement Name TBYTE_BUSY Location 28A0[3] Rst 0 Wk 0 Dir R Description Indicates that hardware is still writing the 0x28A0 byte. Additional writes to this byte are locked out while it is one. Write duration could be as long as 6 ms. Sets the period between temperature measurements. Automatic measurements can be enabled in any mode (MSN and during ac power outages if the VBAT_RTC voltage is within specification, as supplied by a battery). TEMP_PER 0 1-6 7 TEMP_BAT 28A0[4] 0 – R/W Time Manual updates (see TEMP_START) 2 ^ (3+TEMP_PER) (seconds) Continuous TEMP_PER[2:0] 28A0[2:0] 0 – R/W TEMP_START 28B4[6] 0 – TEMP_PWR Reserved 28A0[6] 28A0[7] 0 0 – – TEMP_TEST[1:0] 2500[1:0] 0 – Causes the VBAT_RTC pin to be measured whenever a temperature measurement is performed. TEMP_PER[2:0] must be zero in order for TEMP_START t o function. If TEMP_PER[2:0] = 0, then setting TEMP_START starts a temperature measurement. R/W This bit is ignored in SLP mode. Hardware clears TEMP_START when the temperature measurement is complete. Selects the power source for the temperature sensor: 1 = V3P3D, 0 = VBAT_RTC. This bit is ignored in R/W SLP mode, where the temperature sensor is always powered by VBAT_RTC. R/W Must always be zero. Test bits for the temperature monitor VCO. TEMP_TEST must be 00 in regular operation. Any other value causes the VCO to run continuously with the control voltage described below. R/W TEMP_TEST Function 00 01 1X Normal operation Reserved for factory test Reserved for factory test STEMP[10:3] STEMP[2:0] 2881[7:0] 2882[7:5] BSENSE[7:0] BCURR 2885[7:0] 2704[3] – 0 – 0 The result of the temperature measurement. The STEMP[10:0] value may be obtained in C with a single 16-bit read and divide by 32 operation as follows: volatile int16_t xdata STEMP _at_0x2881; f a = (float)(STEMP/32); R The result of the battery measurement. Connects a 100 µA load to the battery (VBAT_RTC R/W pin). R R 2.5.6 71M6xx3 Temperature Sensor T he 71M6xx3 includes an on-chip temperature sensor for determining the temperature of its bandgap reference. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system for the compensation of the current measurement performed by the71M6xx3. See the 71M6xxx Data Sheet for the equation to calculate temperature from the 71M6xx3 STEMP[10:0] reading. Also, see 4.5 Metrology Temperature Compensation on page 74. 54 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H See 2.2.8.3 Control of the 71M6xx3 Isolated Sensor on page 22 for information on how to read the STEMP[10:0] information from the 71M6xx3. 2.5.7 71M6545/H Battery Monitor The 71M6545/H temperature measurement circuit can also monitor the battery at the VBAT_RTC pin. When TEMP_BAT (I/O RAM 0x28A0[4] ) is set, a battery measurement is performed as part of each temperature measurement. The value of the battery reading is stored in register BSENSE[7:0] (I/O RAM 0x2885). The following equations are used to calculate the voltage measured on the VBAT_RTC pin from the BSENSE[7:0] and STEMP[10:0] values. The result of the equation below is in volts. In MSN mode, TEMP_PWR = 1 use: VBAT _ RTC = 3.3V + ( BSENSE − 142) ⋅ 0.0246V + STEMP ⋅ 0.000297V In MSN mode, a 100 µA de-passivation load can be applied to the battery by setting the BCURR (I/O RAM 0x2704[3]) bit. Battery impedance can be measured by taking a battery measurement with and without BCURR. Regardless of the BCURR bit setting, the battery load is never applied in SLP mode. 2.5.8 71M6xx3 VCC Monitor The 71M6xx3 monitors its VCC pin voltage. The voltage of the VCC pin can be obtained by the 71M6545/H by issuing a read command to the 71M6xx3. The 71M6545/H must request both the VSENSE[7:0] and STEMP[10:0] values from the 71M6xx3. See the 71M6xxx Data Sheet for the equation to calculate the 71M6xx3 VCC pin voltage from the VSENSE[7:0] and STEMP[10:0] values read from the 71M6xx3. See 2.2.8.3 Control of the 71M6xx3 Isolated Sensor on page 22 for information on how to read VSENSE[7:0] and STEMP[10:0] from the 71M6xx3 remote sensors. 2.5.9 UART Interface The 71M6545/H provides an asynchronous interface (UART). The UART can be used to connect to AMR modules, user interfaces, etc., and also support a mechanism for programming the on-chip flash memory. 2.5.10 DIO Pins On reset or power-up, all DIO pins are DIO inputs until they are configured for the desired configuration under MPU control. After reset or power up, pins DIO0 through DIO14 are initially DIO outputs, but are disabled by PORT_E = 0 (I/O RAM 0x270C[5]) to avoid unwanted pulses. After configuring pins DIO0 through DIO14 the host enables the pins by setting PORT_E = 1. DIO pins can be configured independently as an input or output. For DIO0 to DIO14, this is done with the SFR registers P0 (SFR 0x80), P1 (SFR 0x90), P2 (SFR 0xA0) and P3 (SFR 0xB0) as shown in Table 44. Example: DIO12 (pin 19, gray fields in Table 44) is configured as a DIO output pin with a value of 1 (high) by writing 1 to both P3[4]and P3[0] . T able 44: Data/Direction Registers and Internal Resources for DIO0 to DIO14 DIO Pin # DIO Data Register Direction Register: 0 = input, 1 = output Internal Resources Configurable 0 31 1 30 2 29 3 28 4 27 5 26 6 25 7 24 8 23 9 22 10 21 11 20 12 19 13 18 14 17 1 2 3 P0 (SFR80) 4 5 6 7 P0 (SFR80) ----- 0 1 2 3 P1 (SFR90) 4 5 6 7 P1 (SFR90) Y Y Y Y 0 1 2 3 P2 (SFRA0) 4 5 6 7 P2 (SFRA0) Y Y Y Y 0 0 1 2 P3 (SFRB0) 4 5 6 P3 (SFRB0) – – – The configuration for pins DIO19 to DIO25, DIO28 and DIO29 are shown in Table 45 The configuration for pins DIO55 is shown in Table 46. v1.0 © 2008–2011 Teridian Semiconductor Corporation 55 Data Sheet 71M6545/H T able 45: Data/Direction Registers for DIO19-25 and DIO28-29 DIO Pin # DIO Data Register Direction Register: 0 = input, 1 = output 19 20 19 14 19 20 13 20 21 12 21 22 11 23 10 24 9 25 8 28 7 28 PDS_6545_009 29 6 29 22 23 24 25 DIO16[0] to DIO31[0] (I/O RAM 0x2420[0] to 0x242F[0]) 21 22 23 24 25 DIO16[1] to DIO31[1] (I/O RAM 0x2420[1] to 0x242F[1]) 28 29 T able 46: Data/Direction Registers for DIO55 DIO Pin # DIO Data Register Direction Register: 0 = input, 1 = output – – – – – – – – – – – 55 32 – – – – – – – – – 55 – – DIO51[0] to DIO55[0] (I/O RAM 0x2443[0] to 0x2447[0]) – – – 55 – – DIO51[1] to DIO55[1] (I/O RAM 0x2443[1] to 0x2447[1]) – The PB pin is a dedicated digital input and is not part of the DIO system. The CE features pulse counting registers and the CE pulse outputs are directly routed to the pulse interrupt input. Thus, no routing of pulse signals to external pins is required in order to generate pulse interrupts. A 3-bit configuration word, I/O RAM register DIO_Rn[2:0] (I/O RAM 0x2009[2:0] through 0x200E[6:4]) can be used for pins DIO2 through DIO11 (when configured as DIO) and PB to individually assign an internal resource such as an interrupt or a timer control (DIO_RPB[2:0], I/O RAM 0x2450[2:0], configures the PB pin). This way, DIO pins can be tracked even if they are configured as outputs. Table 47 lists the internal resources which can be assigned using DIO_R2[2:0] (also called DIO_RPB[2:0] ) through DIO_R11[2:0] and DIO_RPB[2:0]. If more than one input is connected to the same resource, the resources are combined using a logical OR. T able 47: Selectable Resources using the DIO_Rn[2:0] Bits Value in DIO_Rn[2:0] 0 1 2 3 4 5 Resource Selected for DIOn or PB Pin None Reserved T0 (counter0 clock) T1 (counter1 clock) High priority I/O interrupt (INT0) Low priority I/O interrupt (INT1) W hen driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as shown in Figure 14, right), not source it from V3P3D (as shown in Figure 14, left). This is due to the resistance of the internal switch that connects V3P3D to V3P3SYS. Sourcing current in or out of DIO pins other than those dedicated for wake functions, for example with pull-up or pull-down resistors, should be avoided. Violating this rule leads to increased quiescent current from a battery connected to the VBAT_RTC pin during SLP mode. 56 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H MISSION SLEEP V3P3SYS MISSION SLEEP V3P3SYS V3P3D V3P3D HIGH HIGH-Z LOW DIO HIGH HIGH-Z LOW DIO GNDD GNDD Not recommended Recommended Figure 14: Connecting an External Load to DIO Pins 2.5.11 EEPROM Interface The 71M6545/H provides hardware support for either a two-pin or a three-wire (µ-wire) type of EEPROM interface. The interfaces use the EECTRL (SFR 0x9F) and EEDATA (SFR 0x9E) registers for communication. Two-pin EEPROM Interface The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is multiplexed onto the DIO2 (SDCK) and DIO3 (SDATA) pins and is selected by setting DIO_EEX[1:0] = 01 (I/O RAM 0x2456[7:6]). The MPU communicates with the interface through the SFR registers EEDATA and EECTRL. If the MPU wishes to write a byte of data to the EEPROM, it places the data in EEDATA and then writes the Transmit code to EECTRL. This initiates the transmit operation which is finished when the BUSY bit falls. INT5 is also asserted when BUSY f alls. The MPU can then check the RX_ACK bit to see if the EEPROM acknowledged the transmission. A byte is read by writing the Receive command to EECTRL and waiting for the BUSY bit to fall. Upon completion, the received data is in EEDATA. The serial transmit and receive clock is 78 kHz during each transmission, and then holds in a high state until the next transmission. The EECTRL bits when the two-pin interface is selected are shown in Table 48. T able 48: EECTRL Bits for 2-pin Interface Status Bit 7 6 5 4 Name ERROR BUSY RX_ACK TX_ACK Read/ Write R R R R Reset State 0 0 1 1 Polarity Positive Positive Positive Positive Description 1 when an illegal command is received. 1 when serial data bus is busy. 1 indicates that the EEPROM sent an ACK bit. 1 indicates when an ACK bit has been sent to the EEPROM. CMD[3:0] 0000 3:0 CMD[3:0] W 0000 Positive 0010 0011 0101 v1.0 Operation No-op command. Stops the I2C clock (SDCK). If not issued, SDCK keeps toggling. Receive a byte from the EEPROM and send ACK. Transmit a byte to the EEPROM. Issue a STOP sequence. 57 © 2008–2011 Teridian Semiconductor Corporation Data Sheet 71M6545/H Status Bit Read/ Write Reset State PDS_6545_009 Name Polarity Description 0110 1001 Others Receive the last byte from the EEPROM and do not send ACK. Issue a START sequence. No operation, set the ERROR bit. The EEPROM interface can also be operated by controlling the DIO2 and DIO3 pins directly. The direction of the DIO line can be changed from input to output and an output value can be written with a single write operation, thus avoiding collisions (see Table 14 Port Registers (DIO0-14)). Therefore, no resistor is required in series SDATA to protect against collisions. Three-Wire (µ-Wire) EEPROM Interface with Single Data Pin A 500 kHz three-wire interface, using SDATA, SDCK, and a DIO pin for CS is available. The interface is selected by setting DIO_EEX[1:0] = 10. The EECTRL bits when the three-wire interface is selected are shown in Table 49. When EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM or read from the EEPROM, depending on the values of the EECTRL bits. Three-Wire (µ-Wire/SPI) EEPROM Interface with Separate Di/DO Pins If DIO_EEX[1:0] = 11, the 71M6545/H three-wire interface is the same as above, except DI and DO are separate pins. In this case, DIO3 becomes DO and DIO8 becomes DI. The timing diagrams are the same as for DIO_EEX[1:0] = 10 except that all output data appears on DO and all input data is expected on DI. In this mode, DI is ignored while data is being received on DO. This mode is compatible with SPI modes 0,0 and 1,1 where data is shifted out on the falling edge of the clock and is strobed in on the rising edge of the clock. T able 49: EECTRL Bits for the 3-wire Interface Control Bit Name Read/ Write Description W ait for Ready. If this bit is set, the trailing edge of BUSY is delayed until a rising edge is seen on the data line. This bit can be used during the last byte of a Write command to cause the INT5 interrupt to occur when the EEPROM has finished its internal write sequence. This bit is ignored if HiZ=0. Asserted while the serial data bus is busy. When the BUSY bit falls, an INT5 interrupt occurs. Indicates that the SD signal is to be floated to high impedance immediately after the last SDCK rising edge. Indicates that EEDATA (SFR 0x9E) is to be filled with data from EEPROM. Specifies the number of clocks to be issued. Allowed values are 0 through 8. If RD = 1, CNT bits of data are read MSB first, and right justified into the low order bits of EEDATA. If RD = 0, CNT bits are sent MSB first to the EEPROM, shifted out of the MSB of EEDATA. If CNT[3:0] is zero, SDATA simply obeys the HiZ bit. 7 WFR W 6 5 4 BUSY HiZ RD R W W 3:0 CNT[3:0] W The timing diagrams in Figure 15 through Figure 19 describe the 3-wire EEPROM interface behavior. All commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 15 through Figure 19 are then sent via EECTRL and EEDATA. When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM drives SDATA, but transitions to HiZ (high impedance) when CS falls. The firmware should then 58 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to a low-Z state. EECTRL Byte Written CNT Cycles (6 shown) Write -- No HiZ SCLK (output) SDATA (output) SDATA output Z BUSY (bit) D7 D6 D5 (LoZ) D4 D3 D2 INT5 Figure 15: 3-wire Interface. Write Command, HiZ=0. EECTRL Byte Written CNT Cycles (6 shown) Write -- With HiZ SCLK (output) SDATA (output) SDATA output Z BUSY (bit) D7 D6 D5 (LoZ) D4 D3 D2 (HiZ) INT5 Figure 16: 3-wire Interface. Write Command, HiZ=1 EECTRL Byte Written CNT Cycles (8 shown) READ SCLK (output) SDATA (input) SDATA output Z BUSY (bit) D7 D6 (HiZ) D5 D4 D3 D2 D1 D0 INT5 Figure 17: 3-wire Interface. Read Command. EECTRL Byte Written Write -- No HiZ SCLK (output) SDATA (output) SDATA output Z BUSY (bit) D7 (LoZ) INT5 not issued CNT Cycles (0 shown) EECTRL Byte Written Write -- HiZ SCLK (output) SDATA (output) INT5 not issued CNT Cycles (0 shown) SDATA output Z BUSY (bit) (HiZ) Figure 18: 3-Wire Interface. Write Command when CNT=0 v1.0 © 2008–2011 Teridian Semiconductor Corporation 59 Data Sheet 71M6545/H EECTRL Byte Written CNT Cycles (6 shown) Write -- With HiZ and WFR SCLK (output) SDATA (out/in) SDATA output Z BUSY (bit) D7 D6 D5 (From 6520) (LoZ) D4 D3 D2 BUSY PDS_6545_009 INT5 READY (From EEPROM) (HiZ) Figure 19: 3-wire Interface. Write Command when HiZ=1 and WFR=1. 2.5.12 SPI Slave Port The slave SPI port communicates directly with the MPU data bus and is able to read and write Data RAM and Configuration RAM (I/O RAM) locations. It is also able to send commands to the MPU. The interface to the slave port consists of the SPI_CSZ, SPI_CKI, SPI_DI and SPI_DO pins. Additionally, the SPI interface allows flash memory to be read and to be programmed. To facilitate flash programming, cycling power or asserting RESET causes the SPI port pins to default to SPI mode. The SPI port is disabled by clearing the SPI_E bit (I/O RAM 0x270C[4]). Possible applications for the SPI interface are: 1) An external host reads data from CE locations to obtain metering information. This can be used in applications where the 71M6545/H function as a smart front-end with preprocessing capability. Since the addresses are in 16-bit format, any type of XRAM data can be accessed: CE, MPU, I/O RAM, but not SFRs or the 80515-internal register bank. 2) A communication link can be established via the SPI interface: By writing into MPU memory locations, the external host can initiate and control processes in the 71M6545/H MPU. Writing to a CE or MPU location normally generates an interrupt, a function that can be used to signal to the MPU that the byte that had just been written by the external host must be read and processed. Data can also be inserted by the external host without generating an interrupt. 3) An external DSP can access front-end data generated by the ADC. This mode of operation uses the 71M6545/H as an analog front-end (AFE). 4) Flash programming by the external host (SPI Flash Mode). SPI Transactions A typical SPI transaction is as follows. While SPI_CSZ is high, the port is held in an initialized/reset state. During this state, SPI_DO is held in high impedance state and all transitions on SPI_CLK and SPI_DI are ignored. When SPI_CSZ falls, the port begins the transaction on the first rising edge of SPI_CLK. As shown in Table 50, a transaction consists of an optional 16 bit address, an 8 bit command, an 8 bit status byte, followed by one or more bytes of data. The transaction ends when SPI_CSZ is raised. Some transactions may consist of a command only. When SPI_CSZ rises, SPI command bytes that are not of the form x0000000 cause the SPI_CMD (SFR 0xFD) register to be updated and then cause an interrupt to be issued to the MPU. The exception is if the transaction was a single byte. In this case, the SPI_CMD byte is always updated and the interrupt issued. SPI_CMD is not cleared when SPI_CSZ is high. The SPI port supports data transfers up to 10 Mb/s. A serial read or write operation requires at least 8 clocks per byte, guaranteeing SPI access to the RAM is no faster than 1.25 MHz, thus ensuring that SPI access to DRAM is always possible. 60 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 T able 50: SPI Transaction Fields Field Name Address Required Yes, except single byte transaction Size Description (bytes) 2 Data Sheet 71M6545/H 16-bit address. The address field is not required if the transaction is a simple SPI command. 8-bit command. This byte can be used as a command to the MPU. In multi-byte transactions, the MSB is the R/W bit. Unless the transaction is multi-byte and SPI_CMD is exactly 0x80 or 0x00, the SPI_CMD register is updated and an SPI interrupt is issued. Otherwise, the SPI_CMD register is unchanged and the interrupt is not issued. 8-bit status field, indicating the status of the previous transaction. This byte is also available in the MPU memory map as SPI_STAT (I/O RAM 0x2708). See Table 52 for the contents. The read or write data. Address is auto incremented for each new byte. Command Yes 1 Status Data Yes, if transaction includes DATA Yes, if transaction includes DATA 1 1 or more The SPI_STAT byte is output on every SPI transaction and indicates the parity of the previous transaction and the error status of the previous transaction. Potential error sources are: • • 71M6545/H not ready Transaction not ending on a byte boundary. SPI Safe Mode Sometimes it is desirable to prevent the SPI interface from writing to arbitrary RAM locations and thus disturbing MPU and CE operation. This is especially true in AFE applications. For this reason, the SPI SAFE mode was created. In SPI SAFE mode, SPI write operations are disabled except for a 16 byte transfer region at address 0x400 to 0x40F. If the SPI host needs to write to other addresses, it must use the SPI_CMD register to request the write operation from the MPU. SPI SAFE mode is enabled by the SPI_SAFE bit (I/O RAM 0x270C[3]). Single-Byte Transaction If a transaction is a single byte, the byte is interpreted as SPI_CMD. Regardless of the byte value, single-byte transactions always update the SPI_CMD register and cause an SPI interrupt to be generated. Multi-Byte Transaction As shown in Figure 20, multi-byte operations consist of a 16 bit address field, an 8 bit CMD, a status byte, and a sequence of data bytes. A multi byte transaction is three or more bytes. SERIAL READ 16 bit Address 8 bit CMD Status Byte DATA[ADDR] DATA[ADDR+1] (From Host) SPI_CSZ 0 (From Host) SPI_CK (From Host) SPI_DI (From 6545) SPI_DO A15 A14 A1 A0 HI Z C7 C6 C5 C0 ST7 ST6 ST5 ST0 x D7 D6 D1 D0 15 16 23 24 31 32 39 Extended Read . . . 40 47 D7 D6 D1 D0 SERIAL WRITE 16 bit Address 8 bit CMD Status Byte DATA[ADDR] DATA[ADDR+1] (From Host) SPI_CSZ 0 (From Host) SPI_CK (From Host) SPI_DI (From 6545) SPI_DO x A15 A14 A1 A0 HI Z C7 C6 C5 C0 ST7 ST6 ST5 ST0 D7 D6 D1 D0 15 16 23 24 31 32 39 Extended Write . . . 40 47 D7 D6 D1 D0 x Figure 20: SPI Slave Port - Typical Multi-Byte Read and Write operations v1.0 © 2008–2011 Teridian Semiconductor Corporation 61 Data Sheet 71M6545/H T able 51: SPI Command Sequences Command Sequence ADDR 1xxx xxxx STATUS Byte0 ... ByteN Description PDS_6545_009 0xxx xxxx ADDR Byte0 ... ByteN Read data starting at ADDR. ADDR is auto-incremented until SPI_CSZ is raised. Upon completion, SPI_CMD (SFR 0xFD) is updated to 1xxx xxxx and an SPI interrupt is generated. The exception is if the command byte is 1000 0000. In this case, no MPU interrupt is generated and SPI_CMD is not updated. Write data starting at ADDR. ADDR is auto-incremented until SPI_CSZ is raised. Upon completion, SPI_CMD is updated to 0xxx xxxx and an SPI interrupt is generated. The exception is if the command byte is 0000 0000. In this case, no MPU interrupt is generated and SPI_CMD is not updated. T able 52: SPI Registers Name EX_SPI SPI_CMD SPI_E IE_SPI SPI_SAFE Location 2701[7] SFR FD[7:0] 270C[4] SFR F8[7] 270C[3] Rst 0 – 1 0 0 Wk 0 – 1 0 0 Dir R/W R R/W R/W R/W Description SPI interrupt enable bit. SPI command. The 8-bit command from the bus master. SPI port enable bit. It enables the SPI interface on pins SPI_DI, SPI_DO, SPI_CSZ and SPI_CKI. SPI interrupt flag. Set by hardware, cleared by writing a 0. Limits SPI writes to SPI_CMD and a 16 byte region in DRAM when set. No other write operations are permitted. SPI_STAT contains the status results from the previous SPI transaction Bit 7 - 71M6545/H ready error: the 71M6545/H was not ready to read or write as directed by the previous command. Bit 6 - Read data parity: This bit is the parity of all bytes read from the 71M6545/H in the previous command. Does not include the SPI_STAT byte. Bit 5 - Write data parity: This bit is the overall parity of the bytes written to the 71M6545/H in the previous command. It includes CMD and ADDR bytes. Bit 4:2 - Bottom 3 bits of the byte count. Does not include ADDR and CMD bytes. One, two, and three byte instructions return 111. Bit 1 - SPI FLASH mode: This bit is zero when the TEST pin is zero. Bit 0 - SPI FLASH mode ready: Used in SPI FLASH mode. Indicates that the flash is ready to receive another write instruction. SPI_STAT 2708[7:0] 0 0 R SPI Flash Mode (SFM) In normal operation, the SPI slave interface cannot read or write the flash memory. However, the 71M6545/H supports a special flash mode (SFM) which facilitates initial programming of the flash memory. When the 71M6545/H is in this mode, the SPI can erase, read, and write the flash memory. Other memory elements such as XRAM and IO RAM are not accessible in this mode. In order to protect the flash contents, several operations are required before the SFM mode is successfully invoked. 62 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H In SFM mode, the 71M6545/H supports n byte reads and dual-byte writes to flash memory. See the SPI Transaction description on Page 60 for the format of read and write commands. Since the flash write operation is always based on a two-byte word, the initial address must always be even. Data is written to the 16-bit flash memory bus after the odd word is written. In SFM mode, the MPU is completely halted. For this reason, the interrupt feature described in the SPI Transaction section above is not available in SFM mode. The 71M6545/H must be reset by the WD timer or by the RESET pin in order to exit SFM mode. Invoking SFM The following conditions must be met prior to invoking SFM: • • • • • ICE_E = 1. This disables the watchdog and adds another layer of protection against inadvertent Flash corruption. The external power source (V3P3SYS, V3P3A) is at the proper level (> 3.0 VDC). PREBOOT = 0 (SFR 0xB2[7]). This validates the state of the SECURE bit (SFR 0xB2[6]). SECURE = 0. This I/O RAM register indicates that SPI secure mode is not enabled. Operations are limited to SFM Mass Erase mode if the SECURE bit = 1 (Flash read back is not allowed in Secure mode). FLSH_UNLOCK[3:0] = 0010 (I/O RAM 0x2702[7:4]). The I/O RAM registers SFMM (I/O RAM 0x2080) and SFMS (I/O RAM 0x2081) are used to invoke SFM. Only the SPI interface has access to these two registers. This eliminates an indirect path from the MPU for disabling the watchdog. SFMM and SFMS need to be written to in sequence in order to invoke SFM. This sequential write process prevents inadvertent entering of SFM. The sequence for invoking SFM is: • First, write to SFMM (I/O RAM 0x2080) register. The value written to this register defines the SFM mode. o 0xD1: Mass Erase mode. A Flash Mass erase cycle is invoked upon entering SFM. o 0x2E: Flash Read back mode. SFM is entered for Flash read back purposes. Flash writes are blocked and it is up to the user to guarantee that only previously unwritten locations are written. This mode is not accessible when SPI secure mode is set. o SFM is not invoked if any other pattern is written to the SFMM register. Next, write 0x96 to the SFMS (I/O RAM 0x2081) register. This write invokes SFM provided that the previous write operation to SFMM m et the requirements. Writing any other pattern to this register does not invoke SFM. Additionally, any write operations to this register automatically reset the previously written SFMM register values to zero. • SFM Details The following occurs upon entering SFM. • • • • • The CE is disabled. The MPU is halted. Once the MPU is halted it can only be restarted with a reset. This reset can be accomplished with the RESET pin, a watchdog reset, or by cycling power. The Flash control logic is reset in case the MPU was in the middle of a Flash write operation or Erase cycle. Mass erase is invoked if specified in the SFMM (I/O RAM 0x2080) register (see Invoking SFM, above). The SECURE bit (SFR 0xB2[6]) is cleared at the end of this and all Mass Erase cycles. All SPI read and write operations now refer to Flash instead of XRAM space. The SPI host can access the current state of the pending multi-cycle Flash access by performing a 4-byte SPI write of any address and checking the status field. All SPI write operations in SFM mode must be 6-byte write transactions that write two bytes to an even address. The write transactions must contain a command byte of 0x00 which is the form that does not create an MPU interrupt. Auto incrementing is disabled for write operations. SPI read transactions can make use of auto increment and may access single bytes. The command byte must always be 0x80 in SFM read transactions. v1.0 © 2008–2011 Teridian Semiconductor Corporation 63 Data Sheet 71M6545/H SPI commands in SFM PDS_6545_009 Interrupts are not generated in SFM since the MPU is halted. The format of the commands is shown in the SPI Transactions description on Page 60.SPI Transactions 2.5.13 Hardware Watchdog Timer An independent, robust, fixed-duration, watchdog timer (WDT) is included in the 71M6545/H. It uses the RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least every 1.5 seconds. When not refreshed on time, the WDT overflows and the part is reset as if the RESET pin were pulled high, except that the I/O RAM bits are in the same state as after a wake-up from SLP mode (see the I/O RAM description in 5.2 for a list of I/O RAM bit states after RESET and wake-up). Four thousand, one hundred CK32 cycles (or 125 ms) after the WDT overflow, the MPU is launched from program address 0x0000. The watchdog timer is also reset when the internal signal WAKE=0. The WDT is disabled when the ICE_E pin is pulled high. 2.5.14 Test Ports (TMUXOUT and TMUX2OUT Pins) Two independent multiplexers allow the selection of internal analog and digital signals for the TMUXOUT and TMUX2OUT pins. One of the digital or analog signals listed in Table 53 can be selected to be output on the TMUXOUT pin. The function of the multiplexer is controlled with the I/O RAM register TMUX[4:0] (I/O RAM 0x2502[4:0], as shown in Table 53. One of the digital or analog signals listed in Table 54 can be selected to be output on the TMUX2OUT pin. The function of the multiplexer is controlled with the I/O RAM register TMUX2[4:0] (I/O RAM 0x2503[4:0]), as shown in Table 54. The TMUX and TMUX2 I/O RAM locations are non-volatile and their contents are preserved by battery power and across resets. The TMUXOUT and TMUX2OUT pins may be used for diagnosis purposes or in production test. The RTC 1-second output may be used to calibrate the crystal oscillator. The RTC 4-second output provides even higher precision. T able 53: TMUX[4:0] Selections TMUX[5:0] 1 9 A D Signal Name RTCLK W D_RST CKMPU V3AOK bit Description 32.768 kHz clock waveform Indicates when the MPU has reset the watchdog timer. Can be monitored to determine spare time in the watchdog timer. MPU clock – see Table 8 Indicates that the V3P3A pin voltage is 3.0 V. The V3P3A and ≥ V3P3SYS pins are expected to be tied together at the PCB level. The 71M6545/H monitors the V3P3A pin voltage only. Indicates that the V3P3A pin voltage is 2.8 V. The V3P3A and ≥ V3P3SYS pins are expected to be tied together at the PCB level. The 71M654 monitors the V3P3A pin voltage only. Internal multiplexer frame SYNC signal. See Figure 4 Figure 5. See 2.3.3 on page 25 and Figure 12 on page 45 E 1B 1C 1D 1F V3OK bit MUX_SYNC CE_BUSY interrupt CE_XFER interrupt RTM output from CE and See 2.3.5 on page 26 Note: All TMUX[5:0] values which are not shown are reserved. 64 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H T able 54: TMUX2[4:0] Selections TMUX2[4:0] 0 1 Signal Name W D_OVF PULSE_1S Description Indicates when the watchdog timer has expired (overflowed). One second pulse with 25% Duty Cycle. This signal can be used to measure the deviation of the RTC from an ideal 1 second interval. Multiple cycles should be averaged together to filter out jitter. Four second pulse with 25% Duty Cycle. This signal can be used to measure the deviation of the RTC from an ideal 4 second interval. Multiple cycles should be averaged together to filter out jitter. The 4 second pulse provides a more precise measurement than the 1 second pulse. 32.768 kHz clock waveform C opies the value of the bit stored in 0x2704[1]. For general purpose use. C opies the value of the bit stored in 0x2704[2]. For general purpose use. Indicates when a WAKE event has occurred. Internal multiplexer frame SYNC signal. See Figure 4 and Figure 5. See 2.5.3 on page 48. Digital GND. Use this signal to make the TMUX2OUT pin static. 2 PULSE_4S 3 8 9 A B C E 12 13 14 15 16 17 18 1F RTCLK SPARE[1] bit – I/O RAM 0x2704[1] SPARE[2] bit – I/O RAM 0x2704[2] W AKE MUX_SYNC MCK GNDD INT0 – DIG I/O INT1 – DIG I/O INT2 – CE_PULSE INT3 – CE_BUSY INT4 - VSTAT INT5 – EEPROM/SPI INT6 – XFER, RTC RTM_CK (flash) Interrupt 0. See 2.4.8 on page 38. Also see Figure 12 on page 45. See 2.3.5 on page 26. Note: All TMUX2[4:0] values which are not shown are reserved. v1.0 © 2008–2011 Teridian Semiconductor Corporation 65 Data Sheet 71M6545/H PDS_6545_009 3 3.1 FUNCTIONAL DESCRIPTION Theory of Operation The energy delivered by a power source into a load can be expressed as: E = ∫ V (t ) I (t )dt 0 t Assuming phase angles are constant, the following formulae apply:    P = Real Energy [Wh] = V * A * cos φ* t Q = Reactive Energy [VARh] = V * A * sin φ * t S = Apparent Energy [VAh] = P2 + Q2 For a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic content may change constantly. Thus, simple RMS measurements are inherently inaccurate. A modern solid-state electricity meter IC such as the Teridian 71M6545/H functions by emulating the integral operation above, i.e. it processes current and voltage samples through an ADC at a constant frequency. As long as the ADC resolution is high enough and the sample frequency is beyond the harmonic range of interest, the current and voltage samples, multiplied with the time period of sampling yields an accurate quantity for the momentary energy. Summing-up the momentary energy quantities over time results in accumulated energy. 500 400 300 200 100 0 0 -100 -200 Current [A] 5 10 15 20 -300 -400 -500 Voltage [V] Energy per Interval [Ws] Accumulated Energy [Ws] Figure 21: Voltage, Current, Momentary and Accumulated Energy Figure 21 shows the shapes of V(t), I(t), the momentary power and the accumulated power, resulting from 50 samples of the voltage and current signals over a period of 20 ms. The application of 240 VAC and 100 A results in an accumulation of 480 Ws (= 0.133 Wh) over the 20 ms period, as indicated by the accumulated power curve. The described sampling method works reliably, even in the presence of dynamic phase shift and harmonic distortion. 66 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H 3.2 SLP Mode (Sleep Mode) Shortly after system power (V3P3SYS) is applied, the part will be in mission mode (MSN mode). MSN mode means that the part is operating with system power and that the internal PLL is stable. This mode is the normal operation mode where the part is capable of measuring energy. When system power is not available, the 71M6545/H will be in SLP mode, if a battery is attached to the VBAT_RTC pin. Shortly after system power is removed (V3P3SYS < 3.0 VDC), VSTAT[2:0] will assume the value 001, issuing a warning to the MPU. The IC can still operate in this state, however, the analog functions are not considered accurate. Assuming that the recommended MPU setup code is resident in flash memory (see 2.4.1 MPU Setup Code on page 30), at V3P3SYS < 2.8 VDC, the 71M6545/H will be forced to SLP mode by the MPU setting the SLEEP bit (I/O RAM 0x28B2[7]). When system power is restored, the 71M6545/H will automatically transition from SLP mode back to MSN mode. T able 55: Available Circuit Functions System Power Battery Power MSN SLP CE Yes -FIR Yes -ADC, VREF Yes -PLL Yes Battery measurement Yes Temperature sensor Yes Yes 4.92MHz Maximum MPU clock rate -(from PLL) MPU_DIV clock divider Yes -ICE Yes -DIO Pins Yes -W atchdog Timer Yes -V3P3D Pin Yes -VDD Pin Yes -EEPROM Interface (2-wire) Yes -EEPROM Interface (3-wire) Yes -UART (full speed) Yes -SPI slave port Yes -SPI Special Flash Mode Yes -Optical TX modulation Yes -Flash Read Yes -Flash Page Erase Yes -Flash Write Yes -RAM Read and Write Yes -OSC and RTC Yes Yes RAM data preservation Yes -NV RAM data preservation Yes Yes – indicates not active The SLP mode may be commanded by the MPU whenever main system power is absent by asserting the SLEEP bit. The purpose of the SLP mode is to consume the least power while still maintaining the RTC, temperature compensation of the RTC, and the non-volatile portions of the I/O RAM. Circuit Function In SLP mode, the V3P3D pin is disconnected, removing all sources of leakage from V3P3SYS. The nonvolatile memory domain and the basic functions, such as temperature sensor, oscillator, and RTC, are powered by the VBAT_RTC input. In this mode, the I/O configuration bits and NV RAM values are preserved and RTC and oscillator continue to run. This mode can be exited only by system power up. v1.0 © 2008–2011 Teridian Semiconductor Corporation 67 Data Sheet 71M6545/H PDS_6545_009 If the SLEEP bit is asserted when system power is present, the 71M6545/H will still enter SLP mode. It will drop WAKE, and then will begin the standard wake from sleep procedure. After the transition from SLP mode to MSN mode the PC will be at 0x0000, the XRAM is in an undefined state, and the I/O RAM is only partially preserved (see the description of I/O RAM states in 5.2). The nonvolatile sections of the I/O RAM are preserved unless RESET goes high. The 71M6545/H features a temperature sensor and automatic digital temperature compensation circuitry that can operate from a battery connected to the VBAT_RTC pin, in the event of ac power loss. When ac power loss occurs, the 71M6545/H crystal oscillator, temperature sensor and digital temperature compensation circuitry automatically obtain power from the VBAT_RTC pin. See 2.5.4 Real-Time Clock (RTC) on page 49. 3.3 3.3.1 Fault and Reset Behavior Events at Power-Down Power fault detection is performed by internal comparators that monitor the voltage at the V3P3A pin and also monitor the internally generated VDD pin voltage (2.5 VDC). The V3P3SYS and V3P3A pins must be tied together at the PCB level, so that the comparators, which are internally connected only to the V3P3A pin, are able to simultaneously monitor the common V3P3SYS and V3P3A pin voltage. The following discussion assumes that the V3P3A and V3P3SYS pins are tied together at the PCB level. During a power failure, as V3P3A falls, two thresholds are detected: • • The first threshold, at 3.0 VDC (VSTAT[2:0] = 001, SFR 0xF9[2:0]), warns the MPU that the analog modules are no longer accurate. Other than warning the MPU, the hardware takes no action when this threshold is crossed. This comparison produces an internal bit named V3OKA. The second threshold, at 2.8 VDC, causes the 71M6545/H to switch to battery power. This switching happens while the FLASH and RAM systems are still able to read and write. This comparison produces an internal bit named V3OK. The power quality is reflected by the VSTAT[2:0] register in I/O RAM space, as shown in Table 56. The VSTAT[2:0] register is located at SFR address F9 and occupies bits 2:0. The VSTAT[2:0] field can only be read. In addition to the state of the main power, the VSTAT[2:0] register provides information about the internal VDD voltage under battery power. Note that if system power (V3P3A) is above 2.8 VDC, the 71M6545/H always switches from battery to system power. T able 56: VSTAT[2:0] (SFR 0xF9[2:0]) VSTAT[2:0] 000 001 010 011 101 Description System Power OK. V3P3A > 3.0 VDC. Analog modules are functional and accurate. System Power is low. 2.8 VDC < V3P3A < 3.0 VDC. Analog modules not accurate. VDD is OK. VDD > 2.25 VDC. The IC has full digital functionality. 2.25 VDC > VDD > 2.0 VDC. Flash write operations are inhibited. VDD < 2.0, which means that the MPU is nearly out of voltage. A reset occurs in 4 cycles of the crystal clock CK32. The response to a system power fault is almost entirely controlled by firmware. During a power failure, system power slowly falls. An interrupt notifies the MPU whenever VSTAT[2:0] changes. It is the MPU’s responsibility to reduce power, when necessary, by slowing the clock rate, disabling the PLL, etc. Precision analog components such as the bandgap reference, the bandgap buffer, and the ADC are powered only by the V3P3A pin and become inaccurate and ultimately unavailable as the V3P3A pin voltage continues to drop (i.e., circuits powered by the V3P3A pin are not backed by the VBAT_RTC pin). When the V3P3A pin falls below 2.8 VDC, the ADC clocks are halted and the amplifiers are unbiased. Meanwhile, control bits such as ADC_E bit (I/O RAM 0x2704[4]) are not affected, since their I/O 68 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H RAM storage is powered from the VDD pin (2.5 VDC). The VDD pin is supplied with power through an internal 2.5 VDC regulator that is connected to the V3P3D pin. Note that the V3P3SYS and V3P3A pins are typically tied together at the PCB level. 3.3.2 Reset Sequence W hen the RESET pin is pulled high, all digital activity in the chip stops, with the exception of the oscillator and RTC. Additionally, all I/O RAM bits are forced to their RST state. A reliable reset does not occur until RESET has been high at least for 2 µs. Note that TMUX and the RTC are not reset unless the TEST pin is pulled high while RESET is high. The RESET control bit (I/O RAM 0x 2200[3]) performs an identical reset to the RESET pin except that a significantly shorter reset timer is used. Once initiated, the reset sequence waits until the reset timer times out. The time out occurs in 4100 CE32 cycles (125 ms), at which time the MPU begins executing its pre-boot and boot sequences from address 0x0000. See 2.5.1.1 for a detailed description of the pre-boot and boot sequences. A softer form of reset is initiated when the E_RST pin of the ICE interface is pulled low. This event causes the MPU and other registers in the MPU core to be reset but does not reset the remainder of the 71M6545/H. It does not trigger the reset sequence. This type of reset is intended to reset the MPU program, but not to make other changes to the chip’s state. 3.4 Data Flow and Host Communication The data flow between the Compute Engine (CE) and the host is shown in Figure 22. In a typical application, the 32-bit CE sequentially processes the samples from the voltage inputs on pins IADC0IADC1, VADC8 (VA), IADC2-IADC3, etc., performing calculations to measure active power (Wh), 2 2 reactive power (VARh), A h, and V h for four-quadrant metering. These measurements are then accessed by the host via the SPI interface, processed further and stored and/or displayed. For example, to obtain the RMS current value in phase A, the host reads the I0SQSUM_X register of the CE, scales it with VMAX, IMAX, and the LSB, as given in the CE Interface description (see 5.4 CE Interface Description on page 100), and then performs a square-root operation. Similarly, momentary real power and reactive power available via the WSUM_X and VARSUM_X registers only have to be scaled by the host, while the apparent power has to be post-processed as follows: S = P2 + Q2 Figure 22 illustrates the CE-to-host data flow. v1.0 © 2008–2011 Teridian Semiconductor Corporation 69 Data Sheet 71M6545/H PDS_6545_009 DIO1/interrupt DIO2/interrupt 71M6545/H Pulses TMUX XFER_BUSY XPULSE YPULSE VPULSE WPULSE CE_BUSY Samples Sag Warning Data Ready Interrupt Host MPU MUX Control CE Control XRAM Control SPI I/O RAM (Configuration RAM) 10/7/2010 Figure 22: Data Flow In addition to the four pulse interrupts XPULSE, YPULSE, VPULSE, and WPULSE, the CE outputs two interrupt signals: CE_BUSY and XFER_BUSY. XFER_BUSY signals the end of an accumulation interval where data are ready for the host. This will occur whenever the CE has finished generating a sum by completing an accumulation interval as determined by the number of samples given in SUM_SAMPS. XFER_BUSY can be provided to the host via the test multiplexer output (TMUXOUT) to support synchronization. The YPULSE output can be used to signal a sag event to the host. Refer to 5.4 CE Interface Description on page 100 for additional information on setting up the device by the host. For several reasons, it is necessary to have a small MPU program in flash memory, even when the host takes over all post-processing: • • The MPU has to be prevented from executing code. With the flash mostly empty, the MPU will execute 0xFF op-codes until it runs into the CE code image. Executing the CE code image could have undesired results, e.g., changes to core I/O RAM settings, and must therefore be avoided. The host cannot access the SFRs of the MPU directly. However, SFR access is required for accessing the DIO pins. A small “driver” must exist to support SFR access, if the host needs to control the DIO pins. Sample MPU code that performs the tasks described above is available from Teridian. During operation, the host needs to trigger the watchdog reset periodically in order to avoid watchdog resets. 70 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H 4 4.1 APPLICATION INFORMATION Connecting 5 V Devices All digital input pins of the 71M6545/H are compatible with external 5 V devices. I/O pins configured as inputs do not require current-limiting resistors when they are connected to external 5 V devices. 4.2 Directly Connected Sensors Figure 23 through Figure 26 show voltage-sensing resistive dividers, current-sensing current transformers (CTs) and current-sensing resistive shunts and how they are connected to the voltage and current inputs of the 71M6545/H. All input signals to the 71M6545/H sensor inputs are voltage signals providing a scaled representation of either a sensed voltage or current. The analog input pins of the 71M6545/H are designed for sensors with low source impedance. RC filters with resistance values higher than those implemented in the Teridian Demo Boards must not be used. Please refer to the Demo Board schematics for complete sensor input circuits and corresponding component values. VADCn (n = 8, 9 or 10) VIN ROUT V3P3A Figure 23: Resistive Voltage Divider (Voltage Sensing) IIN IOUT IADCn (n = 0,1,...7) CT RBURDEN VOUT V3P3A Noise Filter 1:N Figure 24. CT with Single-Ended Input Connection (Current Sensing) IIN IOUT IADCn (n = 0, 2, 4 or 6) V3P3A CT RBURDEN VOUT IADCn+1 1:N Bias Network and Noise Filter Figure 25: CT with Differential Input Connection (Current Sensing) IIN IADCn (n = 2, 4 or 6) V3P3A RSHUNT VOUT IADCn+1 Bias Network and Noise Filter Figure 26: Differential Resistive Shunt Connections (Current Sensing) v1.0 © 2008–2011 Teridian Semiconductor Corporation 71 Data Sheet 71M6545/H PDS_6545_009 4.3 Systems Using 71M6xx3 Isolated Sensors and Current Shunts Figure 27 shows a typical connection for current shunt sensors; using the 71M6xx3 (poly-phase) isolated sensors. Note that one shunt current sensor is connected without isolation, which is the neutral current sensor in this example (connected to pins IADC0-IADC1). Each 71M6xx3 device is electrically isolated by a low-cost pulse transformer. The 71M6545/H current sensor inputs must be configured for remote sensor communications, as described in 2.2.8. Flexible remapping using the I/O RAM registers MUXn_SEL[3:0] allows the sequence of analog input pins to be different from the standard configuration (a corresponding CE code must be used). See Figure 2 for the AFE configuration corresponding to Figure 27. C Shunt Resistor Sensors NEUTRAL B LOAD A POWER SUPPLY 71M6xx3 71M6xx3 71M6xx3 This system is referenced to Neutral NEUTRAL Resistor Dividers Pulse Transformers C MUX and ADC IADC0 } IN* IADC1 VADC10 (VC) IADC6 IADC7 } IC VADC9 (VB) IADC4 } IB IADC5 VADC8(VA) IADC2 } IA IADC3 VREF SERIAL PORT RX TX V3P3A V3P3SYS GNDA GNDD PWR MODE CONTROL B TERIDIAN 71M6545/H PB REGULATOR A VBAT_RTC TEMPERATURE SENSOR BATTERY MONITOR OSCILLATOR/ PLL XIN RTC BATTERY RAM 32 kHz XOUT DIO, PULSES, LEDs DIO MPU FLASH MEMORY ICE SPI_CKI SPI_DI SPI_DO SPI_CSZ XFER_BUSY SAG *IN = Optional Neutral Current RTC TIMERS 24 DIO I2C or µWire EEPROM V3P3D SPI INTERFACE HOST T M COMPUTE U ENGINE X WPULSE XPULSE RPULSE YPULSE 10/7/2010 PULSES 3.3 VDC Figure 27: System Using Three-Remotes and One-Local (Neutral) Sensor 72 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H 4.4 System Using Current Transformers Figure 28 shows a poly-phase system using four current transformers to support optional Neutral current sensing for anti-tamper purposes. The Neutral current sensing CT can be omitted if Neutral current sensing is not required. The system is referenced to Neutral (i.e., the Neutral rail is tied to V3P3A and V3P3SYS). PHASE A NEUTRAL PHASE B PHASE C Current Transformers LOAD POWER SUPPLY This system is referenced to Neutral NEUTRAL Resistor Dividers MUX and ADC IADC0 } IA IADC1 VADC8 (VA) IADC2 } IB IADC3 VADC9 (VB) IADC4 } IC IADC5 VADC10 (VC) IADC6 } *IN IADC7 VREF SERIAL PORT RX TX V3P3A V3P3SYS GNDA GNDD PWR MODE CONTROL TERIDIAN 71M6545/H PB REGULATOR VBAT_RTC TEMPERATURE SENSOR BATTERY MONITOR OSCILLATOR/ PLL XIN RTC BATTERY RAM 32 kHz XOUT DIO, PULSES, LEDs DIO MPU FLASH MEMORY ICE SPI_CKI SPI_DI SPI_DO SPI_CSZ XFER_BUSY SAG *IN = Optional Neutral Current RTC TIMERS 24 DIO I2C or µWire EEPROM V3P3D HOST T M COMPUTE SPI INTERFACE U ENGINE X WPULSE XPULSE RPULSE YPULSE 10/7/2010 PULSES 3.3 VDC Figure 28. System Using Current Transformers v1.0 © 2008–2011 Teridian Semiconductor Corporation 73 Data Sheet 71M6545/H PDS_6545_009 4.5 4.5.1 Metrology Temperature Compensation Distinction Between Standard and High-Precision Parts Since the VREF band-gap amplifier is chopper-stabilized, as set by the CHOP_E[1:0] (I/O RAM 0x2106[3:2]) control field, the dc offset voltage, which is the most significant long-term drift mechanism in the voltage references (VREF), is automatically removed by the chopper circuit. Both the 71M6545/H and the 71M6xx3 feature chopper circuits for their respective VREF voltage reference. Since the variation in the bandgap reference voltage (VREF) is the major contributor to measurement error across temperatures, Teridian implements a two step procedure to trim and characterize the VREF voltage reference during the device manufacturing process. The first step in the process is applied to both the 71M6545 and 71M6545H parts. In this first step, the reference voltage (VREF) is trimmed to a target value of 1.195V. During this trimming process, the TRIMT[7:0] (I/O RAM 0x2309) value is stored in non-volatile fuses. TRIMT[7:0] is trimmed to a value that results in minimum VREF variation with temperature. For the 71M6545 device (±0.5% energy accuracy), the TRIMT[7:0] v alue can be read by the MPU during initialization in order to calculate parabolic temperature compensation coefficients suitable for each individual 71M6545 device. The resulting temperature coefficient for VREF in the 71M6545 is ±40 ppm/°C. Considering the factory calibration temperature of VREF to be +22°C and the industrial temperature range (-40°C to +85°C), the VREF error at the temperature extremes for the 71M6545 device can be calculated as: (85o C − 22 o C ) ⋅ 40 ppm / oC = +2520 ppm = +0.252% and (−40 o C − 22 o C ) ⋅ 40 ppm / oC = −2480 ppm = −0.248% The above calculation implies that both the voltage and the current measurements are individually subject to a theoretical maximum error of approximately ±0.25%. When the voltage sample and current sample are multiplied together to obtain the energy per sample, the voltage error and current error combine resulting in approximately ±0.5% maximum energy measurement error. However, this theoretical ±0.5% error considers only the voltage reference (VREF) as an error source. In practice, other error sources exist in the system. The principal remaining error sources are the current sensors (shunts or CTs) and their corresponding signal conditioning circuits, and the resistor voltage divider used to measure the voltage. The 71M6545 0.5% grade device should be used in Class 1% designs, to allow margin for the other error sources in the system. The 71M6545H device (±0.1% energy accuracy) goes through an additional process of characterization during production which makes it suitable to high-accuracy applications. The additional process is the characterization of the voltage reference (VREF) over temperature. The coefficients for the voltage reference are stored in additional non-volatile trim fuses. The MPU can read these trim fuses during initialization and calculate parabolic temperature compensation coefficients suitable for each individual 71M6545H device. The resulting temperature coefficient for VREF in the 71M6545H is ±10 ppm/°C. The VREF error at the temperature extremes for the 71M6545H device can be calculated as: (85o C − 22 o C ) ⋅ 10 ppm / oC = +630 ppm = +0.063% and (−40 o C − 22 o C ) ⋅ 10 ppm / oC = −620 ppm = −0.062% W hen the voltage sample and current sample are multiplied together to obtain the energy per sample, the voltage error and current error combine resulting in approximately ±0.126% maximum energy measurement error. The 71M6545H 0.1% grade device should be used in Class 0.2% and Class 0.5% designs, to allow margin for the other error sources in the system. 74 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H The preceding discussion in this section also applies to the71M6603 (0.5%), 71M6113 (0.5%) and 71M6203 (0.1%) remote sensors. 4.5.2 Temperature Coefficients for the 71M6545 The equations provided below for calculating TC1 and TC2 apply to the 71M6545 (0.5% energy accuracy). In order to obtain TC1 and TC2, the MPU reads TRIMT[7:0] (I/O RAM 0x2309) and uses the TC1 and TC2 equations provided. PPMC and PPMC2 are then calculated from TC1 and TC2, as shown. The resulting tracking of the reference voltage (VREF) is within ±40 ppm/°C, corresponding to a ±0.5% energy measurement accuracy. See 4.5.1 Distinction Between Standard and High-Precision Parts. TC1( µV / °C ) = 275 − 4.95 ⋅ TRIMT TC 2( µV / °C 2 ) = −0.557 + 0.00028 ⋅ TRIMT PPMC = 22.4632 ⋅ TC1 PPMC 2 = 1150.116 ⋅ TC 2 See 4.5.5 and 4.5.6 below for further temperature compensation details. 4.5.3 Temperature Coefficients for the 71M6545H For the 71M6545H, undergoes a two-pass factory trimming process which stores additional trim fuse values. The additional trim fuse values characterize the device’s VREF behavior at various temperatures. The values for TC1 and TC2 are calculated from the values read from the TRIMT[7:0] (I/O RAM 0x2309), TRIMBGB[15:0] (Info Page 0x92 and 0x93) and TRIMBGD[7:0] (Info Page 0x94) non-volatile on-chip fuses using the equations provided. The resulting tracking of the reference voltage is within ±10 ppm/°C, corresponding to a ±0.126% energy measurement accuracy. The equations for deriving PPCM and PPMC2 from TC1 and TC2 are also provided. See 4.5.1 Distinction Between Standard and High-Precision Parts. TC1(µV/℃)=35.091+0.01764∙TRIMT+1.587∙(������������������������������������������ − ������������������������������������������) TC 2( µV / °C 2 ) = −0.557 − 0.00028 ⋅ TRIMT PPMC = 22.4632 ⋅ TC1 PPMC 2 = 1150.116 ⋅ TC 2 TRIMT[7:0] trims the VREF voltage for minimum variation with temperature. The TRIMT[7:0] fuses are read by the MPU directly at I/O RAM address 0x2309[7:0] . During the second pass trim for the 71M6545H, VREF is further characterized at 85°C and 22°C, and the resulting fuse trim values are stored in TRIMBGB[15:0] and TRIMBGD[7:0], respectively. TRIMBGB[15:0] and TRIMBGD[7:0] cannot be read directly by the MPU. See 5.3 Reading the Info Page (71M6545H only) on page 98 for information on how to read the Info Page trim fuses. See 4.5.5 and 4.5.6 below for further temperature compensation details. 4.5.4 Temperature Coefficients for the 71M6603 and 71M6103 (1% Energy Accuracy) Refer to the 71M6xxx Data sheet for the equations that are applicable to each 71M6xx3 part number and the corresponding temperature coefficients. 4.5.5 Temperature Compensation for VREF and Shunt Sensors This section discusses metrology temperature compensation for the meter designs where current shunt sensors are used in conjunction with Teridian’s 71M6xx3 remote isolated sensors, as shown in Figure 27. Sensors that are directly connected to the 71M6545/H are affected by the voltage variation in the 71M6545/H VREF due to temperature. On the other hand, shunt sensors that are connected to 71M6xx3 remote sensor are affected by the VREF in the 71M6xx3. The VREF in both the 71M6545/H and 71M6xx3 can be compensated digitally using a second-order polynomial function of temperature. The 71M6545/H and 71M6xx3 feature temperature sensors for the purposes of temperature compensating their corresponding VREF. The compensation computations must be implemented in MPU firmware. v1.0 © 2008–2011 Teridian Semiconductor Corporation 75 Data Sheet 71M6545/H PDS_6545_009 Referring to Figure 27, the VADC8 (VA), VADC9 (VB) and VADC10 (VC) voltage sensors are always directly connected to the 71M6545/H. Thus, the precision of the voltage sensors is primarily affected by VREF in the 71M6545/H. The temperature coefficient of the resistors used to implement the voltage dividers for the voltage sensors (see Figure 23) determine the behavior of the voltage division ratio with respect to temperature. It is recommended to use resistors with low temperature coefficients, while forming the entire voltage divider using resistors belonging to the same technology family, in order to minimize the temperature dependency of the voltage division ratio. The resistors must also have suitable voltage ratings. The 71M6545/H also may have one local current shunt sensor that is connected directly to it via the IADC0IADC1 input pins, and therefore this local current sensor is also affected by the VREF in the 71M6545/H. The shunt current sensor resistance has a temperature dependency, which also may require compensation, depending on the required accuracy class. The IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7 current sensors are isolated by the 71M6xx3 and depend on the VREF of the 71M6xx3, plus the variation of the corresponding remote shunt current sensor with temperature. The MPU has the responsibility of computing the necessary sample gain compensation values required for each sensor channel based on the sensed temperature. Teridian provides demonstration code that implements the GAIN_ADJx compensation equation shown below. The resulting GAIN_ADJx values are stored by the MPU in five CE RAM locations GAIN_ADJ0-GAIN_ADJ5 (CE RAM 0x40-0x44). The demonstration code thus provides a suitable implementation of temperature compensation, but other methods are possible in MPU firmware by utilizing the on-chip temperature sensors while storing the sample gain adjustment results in the CE RAM GAIN_ADJx storage locations for use by the CE. The demonstration code maintains five separate sets of PPMC and PPMC2 coefficients and computes five separate GAIN_ADJx values based on the sensed temperature using the equation below: GAIN _ ADJx = 16385 + 10 ⋅ TEMP _ X ⋅ PPMC 100 ⋅ TEMP _ X 2 ⋅ PPMC 2 + 214 2 23 The GAIN_ADJx values stored by the MPU in CE RAM are used by the CE to gain adjust (i.e., multiply) the sample in each corresponding sensor channel. A GAIN_ADJx value of 16,384 (i.e., 214)corresponds to unity gain, while values less than 16,384 attenuate the samples and values greater than 16,384 amplify the samples. In the above equation, TEMP_X is the deviation from nominal or calibration temperature expressed in multiples of 0.1 °C. The 10x and 100x factors seen in the above equation are due to 0.1 oC scaling of TEMP_X. For example, if the calibration (reference) temperature is 22 oC and the measured temperature is 27 oC, then 10*TEMP_X = (27-22) x 10 = 50 (decimal), which represents a +5 oC deviation from 22 oC. In the demonstration code, TEMP_X is calculated in the MPU from the STEMP[10:0] temperature sensor reading using the equation provided below and is scaled in 0.1°C units. See 2.5.5 71M6545/H Temperature Sensor on page 53 for the equation to calculate temperature in degrees °C from the STEMP[10:0] value. Table 57 shows the five GAIN_ADJx equation output storage locations and the voltage or current sensor channels for which they compensate for the 1 Local / 3 Remote configuration shown in Figure 27. T able 57: GAIN_ADJn Compensation Channels (Figure 2, Figure 27, Table 1) Gain Adjustment Output CE RAM Address Sensor Channel(s) (pin names) VADC8 (VA) VADC9 (VB) VADC10 (VC) IADC0-IADC1 IADC2-IADC3 IADC4-IADC5 IADC6-IADC7 Compensation For: VREF in 71M6545/H and Voltage Divider Resistors VREF in 71M6545/H and Shunt (Neutral Current) VREF in 71M6xx3 and Shunt (Phase A) VREF in 71M6xx3 and Shunt (Phase B) VREF in 71M6xx3 and Shunt GAIN_ADJ0 GAIN_ADJ1 GAIN_ADJ2 GAIN_ADJ3 GAIN_ADJ4 0x40 0x41 0x42 0x43 0x44 76 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H (Phase C) In the demonstration code, the shape of the temperature compensation second-order parabolic curve is determined by the values stored in the PPMC (1st order coefficient) and PPMC2 (2nd order coefficient), which are typically setup by the MPU at initialization time from values that are stored in EEPROM. To disable temperature compensation in the demonstration code, PPMC and PPMC2 are both set to zero for each of the five GAIN_ADJx channels. To enable temperature compensation, the PPMC and PPMC2 coefficients are set with values that match the expected temperature variation of the shunt current sensor (if required) and the corresponding VREF voltage reference (summed together). The shunt sensor requires a second order polynomial compensation which is determined by the PPMC and PPMC2 coefficients for the corresponding current measurement channel. The corresponding VREF voltage reference also requires the PPMC and PPMC2 coefficients to match the second order temperature behavior of the voltage reference. The PPMC and PPMC2 values associated with the shunt and with the corresponding VREF are summed together to obtain the compensation coefficients for a st nd given current-sensing channel (i.e., the 1 order PPMC coefficients are summed together, and the 2 order PPMC2 coefficients are summed together). In the 71M6545, the required VREF compensation coefficients PPMC and PPMC2 are calculated from readable on-chip non-volatile fuses (see 4.5.2 Temperature Coefficients for the 71M6545). These coefficients are designed to achieve ±40 ppm/°C for VREF in the 71M6545. PPMC and PPMC2 coefficients are similarly calculated for the 71M6xx3 remote sensor (see 4.5.4). For the 71M6545H (±0.1% energy accuracy), coefficients specific to each individual device can be calculated from values read from additional on-chip fuses that characterize the VREF behavior of each individual part across industrial temperatures (see 4.5.3 Temperature Coefficients for the 71M6545H). The resulting tracking of the reference VREF voltage is within ±10 ppm/°C. For the current channels, to determine the PPMC and PPMC2 coefficients for the shunt current sensors, the designer must either know the average temperature curve of the shunt from its manufacturer’s data sheet or obtain these coefficients by laboratory characterization of the shunt used in the design. 4.5.6 Temperature Compensation of VREF and Current Transformers This section discusses metrology temperature compensation for meter designs where Current Transformer (CT) sensors are used, as shown in Figure 28. Sensors that are directly connected to the 71M6545/H are affected by the voltage variation in the 71M6545/H VREF due to temperature. The VREF in the 71M6545/H can be compensated digitally using a second-order polynomial function of temperature. The 71M6545/H features a temperature sensor for the purposes of temperature compensating its VREF. The compensation computations must be implemented in MPU firmware and written to the corresponding GAIN_ADJx CE RAM location. Referring to Figure 28, the VADC8 (VA), VADC9 (VB) and VADC10 (VC) voltage sensors are directly connected to the 71M6545/H. Thus, the precision of the voltage sensors is primarily affected by VREF in the 71M6545/H. The temperature coefficient of the resistors used to implement the voltage dividers for the voltage sensors (see Figure 23) determine the behavior of the voltage division ratio with respect to temperature. It is recommended to use resistors with low temperature coefficients, while forming the entire voltage divider using resistors belonging to the same technology family, in order to minimize the temperature dependency of the voltage division ratio. The resistors must also have suitable voltage ratings. The Current Transformers are directly connected to the 71M6545/H and are therefore primarily affected by the VREF temperature dependency in the 71M6545/H. For best performance, it is recommended to use the differential signal conditioning circuit, as shown in Figure 25, to connect the CTs to the 71M6545/H. Current transformers may also require temperature compensation. The copper wire winding in the CT has dc resistance with a temperature coefficient, which makes the voltage delivered to the burden resistor temperature dependent, and the burden resistor also has a temperature coefficient. Thus, each CT sensor channel needs to compensate for the 71M6545/H VREF, and optionally for the temperature dependency of the CT and its burden resistor depending on the required accuracy class. The MPU has the responsibility of computing the necessary sample gain compensation values required for each sensor channel based on the sensed temperature. Teridian provides demonstration code that implements the GAIN_ADJx compensation equation shown below. The resulting GAIN_ADJx values are v1.0 © 2008–2011 Teridian Semiconductor Corporation 77 Data Sheet 71M6545/H PDS_6545_009 stored by the MPU in five CE RAM locations GAIN_ADJ0-GAIN_ADJ5 (CE RAM 0x40-0x44). The demonstration code thus provides a suitable implementation of temperature compensation, but other methods are possible in MPU firmware by utilizing the on-chip temperature sensor while storing the sample gain adjustment results in the CE RAM GAIN_ADJn storage locations. The demonstration code maintains five separate sets of PPMC and PPMC2 coefficients and computes five separate GAIN_ADJn values based on the sensed temperature using the equation below: 10 ⋅ TEMP _ X ⋅ PPMC 100 ⋅ TEMP _ X 2 ⋅ PPMC 2 GAIN _ ADJx = 16385 + + 214 2 23 The GAIN_ADJn values stored by the MPU in CE RAM are used by the CE to gain adjust (i.e., multiply) the sample in each corresponding sensor channel. A GAIN_ADJx value of 16,384 (i.e., 214)corresponds to unity gain, while values less than 16,384 attenuate the samples and values greater than 16,384 amplify the samples. In the above equation, TEMP_X is the deviation from nominal or calibration temperature expressed in o multiples of 0.1 °C. The 10x and 100x factors seen in the above equation are due to 0.1 C scaling of TEMP_X. For example, if the calibration (reference) temperature is 22 °C and the measured temperature is 27 °C, then 10*TEMP_X = (27-22) x 10 = 50 (decimal), which represents a +5 °C deviation from 22 °C. In the demonstration code, TEMP_X is calculated in the MPU from the STEMP[10:0] temperature sensor reading using the equation provided below and is scaled in 0.1°C units. See 2.5.5 71M6545/H Temperature Sensor on page 53 for the equation to calculate temperature in °C from the STEMP[10:0] reading. Table 58 shows the five GAIN_ADJx equation output storage locations and the voltage or current measurements for which they compensate. T able 58: GAIN_ADJx Compensation Channels (Figure 3, Figure 28, Table 2) Gain Adjustment Output CE RAM Address Sensor Channel(s) (pin names) VADC8 (VA) VADC9 (VB) VADC10 (VC) IADC0-IADC1 IADC2-IADC3 IADC4-IADC5 IADC6-IADC7 Compensation For: VREF in 71M6545/H and Voltage Divider Resistors VREF in 71M6545/H, CT and Burden Resistor (Neutral Current) VREF in 71M6545/H, CT and Burden Resistor (Phase A) VREF in 71M6545/H, CT and Burden Resistor (Phase B) VREF in 71M6545/H, CT and Burden Resistor (Phase C) GAIN_ADJ0 GAIN_ADJ1 GAIN_ADJ2 GAIN_ADJ3 GAIN_ADJ4 0x40 0x41 0x42 0x43 0x44 In the demonstration code, the shape of the temperature compensation second-order parabolic curve is determined by the values stored in the PPMC (1st order coefficient) and PPMC2 (2nd order coefficient), which are typically setup by the MPU at initialization time from values that are stored in EEPROM. To disable temperature compensation in the demonstration code, PPMC and PPMC2 are both set to zero for each of the five GAIN_ADJx channels. To enable temperature compensation, the PPMC and PPMC2 coefficients are set with values that match the expected VREF temperature variation and optionally the corresponding sensor circuit (i.e., the CT and burden resistor for current channels or the resistor divider network for the voltage channels). In the 71M6545 (±0.5% energy accuracy), the required VREF compensation coefficients PPMC and PPMC2 are calculated from readable on-chip non-volatile fuses (see 4.5.2Temperature Coefficients for the 71M6545). These coefficients are designed to achieve ±40 ppm/°C for VREF. 78 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H For the 71M6545H (±0.1% energy accuracy), coefficients specific to each individual device can be calculated from values read from additional on-chip fuses that characterize the VREF behavior of each individual part across industrial temperatures (see 4.5.3 Temperature Coefficients for the 71M6545H). The resulting tracking of the reference VREF voltage is within ±10 ppm/°C. 4.6 Connecting I2C EEPROMs I2C EEPROMs or other I2C compatible devices should be connected to the DIO pins DIO2 and DIO3, as shown in Figure 29. Pull-up resistors of roughly 10 kΩ to V3P3D should be used for both SDCK and SDATA signals. The DIO_EEX (I/O RAM 0x2456[7:6]) field must be set to 01 in order to convert the DIO pins DIO2 and DIO3 to I2C pins SCL and SDATA. 10 kΩ V3P3D 10 kΩ EEPROM DIO2 DIO3 71M6545/H 2 Figure 29: I C EEPROM Connection SDCK SDATA 4.7 Connecting Three-Wire EEPROMs µWire EEPROMs and other compatible devices should be connected to the DIO pins DIO2 and DIO3, as described in 2.5.11 EEPROM Interface on page 57. 4.8 UART (TX/RX) The UART0 RX pin should be pulled down by a 10 kΩ resistor and additionally protected by a 100 pF ceramic capacitor, as shown in Figure 30. 71M6545/H RX 100 pF 10 k Ω RX TX TX Figure 30: Connections for the UART 4.9 Connecting the Reset Pin Even though a functional meter does not necessarily need a reset switch, it is useful to have a reset pushbutton for prototyping as shown in Figure 31, left side. The RESET signal may be sourced from V3P3SYS. v1.0 © 2008–2011 Teridian Semiconductor Corporation 79 Data Sheet 71M6545/H PDS_6545_009 For a production meter, the RESET pin should be protected by the external components shown in Figure 31, right side. R1 should be in the range of 100Ω and mounted as closely as possible to the IC. Since the 71M6545/H generates its own power-on reset, a reset button or circuitry, as shown in Figure 31, is only required for test units and prototypes. V3P3D R2 1k Ω Reset Switch V3P3D 71M6545/H 771M6533 1M6545/H RESET RESET 0.1µF 10k Ω R1 GNDD 100Ω R1 DGND Figure 31: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right) 4.10 Connecting the Emulator Port Pins Even when the emulator is not used, small shunt capacitors to ground (22 pF) should be used for protection from EMI as illustrated in Figure 32. Production boards should have the ICE_E pin connected to ground. V3P3D 62 Ω 62 Ω 71M6545/H ICE_E E_RST E_RXT E_TCLK 62 Ω 22 pF 22 pF 22 pF Figure 32: External Components for the Emulator Interface 4.11 Flash Programming 4.11.1 Flash Programming via the ICE Port Operational or test code can be programmed into the flash memory using either an in-circuit emulator or the Flash Programmer Module (TFP-2) available from Teridian. The flash programming procedure uses the E_RST, E_RXTX, and E_TCLK pins. 4.11.2 Flash Programming via the SPI Port It is possible to erase, read and program the flash memory of the 71M6545/H via the SPI port. See 2.5.12 for a detailed description. 80 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Data Sheet 71M6545/H 4.12 MPU Demonstration Code All application-specific MPU functions mentioned in 4 Application Information are featured in the demonstration C source code supplied by Teridian. The code is available as part of the Demonstration Kit for the 71M6545/H. The Demonstration Kits come with the 71M6545/H preprogrammed with demonstration firmware and mounted on a functional sample meter Demo Board. The Demo Boards allow for quick and efficient evaluation of the IC without having to write firmware or having to supply an in-circuit emulator (ICE). 4.13 Crystal Oscillator The oscillator of the 71M6545/H drives a standard 32.768 kHz watch crystal. The oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to the VBAT_RTC pin. Board layouts with minimum capacitance from XIN to XOUT require less battery current. Good layouts have XIN and XOUT shielded from each other and also keep the XIN and XOUT traces short and away from digital signals. Since the oscillator is self-biasing, an external resistor must not be connected across the crystal. 4.14 Meter Calibration Once the Teridian 71M6545/H energy meter device has been installed in a meter system, it must be calibrated. A complete calibration includes the following: • • • Establishment of the reference temperature for factory calibration (e.g., typically 22 °C). Calibration of the metrology section, i.e., calibration for errors of the current sensors, voltage dividers and signal conditioning components as well as of the internal reference voltage (VREF) at the reference temperature (e.g., typically 22 °C). Calibration of the oscillator frequency using the RTCA_ADJ register (I/O RAM 0x2504). The metrology section can be calibrated using the gain and phase adjustment factors accessible to the CE. The gain adjustment is used to compensate for tolerances of components used for signal conditioning, especially the resistive components. Phase adjustment is provided to compensate for phase shifts introduced by the current sensors or by the effects of reactive power supplies. Due to the flexibility of the MPU firmware, any calibration method, such as calibration based on energy, or current and voltage can be implemented. It is also possible to implement segment-wise calibration (depending on current range). The 71M6545/H supports common industry standard calibration techniques, such as single-point (energy-only), multi-point (energy, Vrms, Irms), and auto-calibration. Teridian provides a calibration spreadsheet file to facilitate the calibration process. Contact your Teridian representative to obtain a copy of the latest calibration spreadsheet file for the 71M6545/H. v1.0 © 2008–2011 Teridian Semiconductor Corporation 81 Data Sheet 71M6545/H PDS_6545_009 5 5.1 FIRMWARE INTERFACE I/O RAM Map –Functional Order In Table 59 and Table 60, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits are identified with a ‘U’. Unimplemented bits have no memory storage, writing them has no effect, and reading them always returns zero. Reserved bits are identified with an ‘R’, and must always be written with a zero. Writing values other than zero to reserved bits may have undesirable side effects and must be avoided. Non-volatile bits are shaded in dark gray. Non-volatile bits are backed-up during power failures if the system includes a battery connected to the VBAT_RTC pin and the pin voltage is within specification. The I/O RAM locations listed in Table 59 have sequential addresses to facilitate reading by the MPU (e.g., in order to verify their contents). These I/O RAM locations are usually modified only at boot-up. The addresses shown in Table 59 are an alternative sequential address to the addresses from Table 60 which are used throughout this document. For instance, EQU[2:0] can be accessed at I/O RAM 0x2000[7:5] or at I/O RAM 0x2106[7:5]. T able 59: I/O RAM Map – Functional Order, Basic Configuration Name CE6 CE5 CE4 CE3 CE2 CE1 CE0 RCE0 RTMUX FOVRD MUX5 MUX4 MUX3 MUX2 MUX1 MUX0 TEMP DIO_R5 DIO_R4 DIO_R3 82 Addr 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 200A 200B 200C 200D 200E 200F 2010 201B 201C 201D Bit 7 Bit 6 EQU[2:0] U U Bit 5 Bit 3 Bit 2 Bit 1 CHOP_E[1:0] RTM_E SUM_SAMPS[12:8] SUM_SAMPS[7:0] CE_LCTN[5:0] PLS_MAXWIDTH[7:0] PLS_INTERVAL[7:0] DIFF0_E RFLY_DIS FIR_LEN[1:0] RMT4_E RMT2_E TMUXR6[2:0] U TMUXR2[2:0] U U U U MUX10_SEL MUX8_SEL MUX6_SEL MUX4_SEL MUX2_SEL MUX0_SEL TEMP_BAT U TEMP_PER[2:0] U U DIO_RPB[2:0] U DIO_R10[2:0] U DIO_R8[2:0] Bit 4 U Bit 0 CE_E U DIFF6_E DIFF4_E DIFF2_E CHOPR[1:0] RMT6_E U TMUXR4[2:0] U U R MUX_DIV[3:0] MUX9_SEL MUX7_SEL MUX5_SEL MUX3_SEL MUX1_SEL R TEMP_PWR OSC_COMP U U U U DIO_R11[2:0] U DIO_R9[2:0] PLS_INV U © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Name Addr Bit 7 Bit 6 U U U DIO_EEX[1:0] DIO_PW DIO_PV DIO_PX DIO_PY EX_EEX EX_XPULSE EX_SPI EX_WPULSE Bit 5 DIO_R7[2:0] DIO_R5[2:0] DIO_R3[2:0] U R U EX_YPULSE EX_VPULSE Bit 4 Bit 3 U U U R U U U Bit 2 Data Sheet 71M6545/H Bit 1 DIO_R6[2:0] DIO_R4[2:0] DIO_R2[2:0] R R U EX_RTC1S R Bit 0 DIO_R2 201E DIO_R1 201F DIO_R0 2020 U R DIO0 2021 R R DIO1 2022 U U DIO2 2023 EX_RTCT EX_RTC1M INT1_E 2024 INT2_E 2025 R R R Reserved 2026 SFMM[7:0]* SFMM 2080 SFMS[7:0]* SFMS 2081 Notes: *SFMM and SFMS are accessible only through the SPI slave port. See 2.5.1.1 Flash Memory f or details. R R U EX_XFER R v1.0 © 2008–2011 Teridian Semiconductor Corporation 83 Data Sheet 71M6545/H PDS_6545_009 Table 60 lists bits and registers that may have to be accessed on a frequent basis. Reserved bits have lighter gray background, and non-volatile bits have a darker gray background. T able 60: I/O RAM Map – Functional Order Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CE and ADC MUX5 2100 MUX4 2101 MUX3 2102 MUX2 2103 MUX1 2104 MUX0 2105 CE6 2106 CE5 2107 CE4 2108 U CE3 2109 CE2 210A CE1 210B DIFF6_E CE0 210C U RTM0 210D RTM0 210E RTM1 210F RTM2 2110 RTM3 2111 CLOCK GENERATION U CKGN 2200 VREF TRIM FUSES TRIMT 2309 DIO U DIO16 2420 U … … U DIO32 243D U … … U DIO38 2443 U … … U DIO42 2447 84 MUX_DIV[3:0] MUX9_SEL[3:0] MUX7_SEL[3:0] MUX5_SEL[3:0] MUX3_SEL[3:0] MUX1_SEL[3:0] EQU[2:0] U U DIFF4_E U DIFF2_E U MUX10_SEL[3:0] MUX8_SEL[3:0] MUX6_SEL[3:0] MUX4_SEL[3:0] MUX2_SEL[3:0] MUX0_SEL[3:0] U CHOP_E[1:0] RTM_E CE_E SUM_SAMPS[12:8] SUM_SAMPS[7:0] CE_LCTN[5:0] PLS_MAXWIDTH[7:0] PLS_INTERVAL[7:0] DIFF0_E RFLY_DIS FIR_LEN[1:0] PLS_INV U U U RTM0[9:8] RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] PLL_FAST RESET MPU_DIV[2:0] U ADC_DIV TRIMT[7:0] U U U U U U U DIO16[5:0] … DIO45[5:0] … DIO51[5:0] … DIO55[5:0] © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Name Addr Bit 7 Bit 6 Bit 5 R DIO_R11[2:0] DIO_R9[2:0] DIO_R7[2:0] DIO_R5[2:0] DIO_R3[2:0] U R U U R U Bit 4 R Bit 3 U U U U U U R U U Bit 2 Data Sheet 71M6545/H Bit 1 DIO_RPB[2:0] DIO_R10[2:0] DIO_R8[2:0] DIO_R6[2:0] DIO_R4[2:0] DIO_R2[2:0] R R U R U U U U TMUX[5:0] TMUX2[4:0] RTCA_ADJ[6:0] RMT_RD[15:8] RMT_RD[7:0] EX_EEX EX_SPI VREF_CAL U IE_EEX IE_SPI U U EX_XPULSE EX_YPULSE EX_WPULSE EX_VPULSE FLSH_UNLOCK[3:0] VREF_DIS PRE_E INT6 IE_XPULSE IE_WPULSE U PERR_RD INT5 IE_YPULSE IE_VPULSE U PERR_WR EX_RTCT U U U R ADC_E BCURR VERSION[7:0] INT4 INT3 IE_RTCT U U U PLL_OK U SPI_CMD[7:0] SPI_STAT[7:0] RMT4_E RMT2_E U EX_RTC1M U FLSH_RDE EX_RTC1S U FLSH_WRE SPARE[2:0] INT1 IE_RTC1S U VSTAT[2:0] EX_XFER U R Bit 0 DIO_R5 2450 DIO_R4 2451 DIO_R3 2452 DIO_R2 2453 DIO_R1 2454 DIO_R0 2455 DIO0 2456 DIO1 2457 DIO2 2458 NV BITS SPARENV 2500 FOVRD 2501 TMUX 2502 TMUX2 2503 RTC1 2504 71M6xx3 Interface REMOTE2 2602 REMOTE1 2603 RBITS INT1_E 2700 INT2_E 2701 SECURE 2702 Analog0 2704 VERSION 2706 INTBITS 2707 FLAG0 SFR E8 FLAG1 SFR F8 STAT SFR F9 REMOTE0 SFR FC SPI1 SFR FD SPI0 2708 RCE0 2709 RTMUX 270A v1.0 U R U U U U U DIO_EEX[1:0] DIO_PW DIO_PV DIO_PX DIO_PY U U U U U U U U U U R U U U R R U R R U INT2 IE_RTC1M U RCMD[4:0] INT0 IE_XFER PB_STATE CHOPR[1:0] U RMT6_E TMUXR4[2:0] TMUXR6[2:0] TMUXR2[2:0] 85 © 2008–2011 Teridian Semiconductor Corporation Data Sheet 71M6545/H Name Addr Bit 7 U U Bit 6 U U Bit 5 U PORT_E Bit 4 U SPI_E Bit 3 U SPI_SAFE Bit 2 U U Bit 1 U U PDS_6545_009 Bit 0 INFO_PG U INFO_PG 270B DIO3 270C NV RAM and RTC 2800NVRAMxx 287F W AKE 2880 STEMP1 2881 STEMP0 2882 BSENSE 2885 LKPADDR 2887 LKPDATA 2888 LKPCTRL 2889 RTC0 2890 RTC2 2892 RTC3 2893 RTC4 2894 RTC5 2895 RTC6 2896 RTC7 2897 RTC8 2898 RTC9 2899 RTC10 289B RTC11 289C RTC12 289D RTC13 289E RTC14 289F TEMP 28A0 Reserved 28B0 Reserved 28B1 MISC 28B2 Reserved 28B3 W DRST 28B4 MPU PORTS 86 NVRAM[0] – NVRAM[7F] – Direct Access WAKE_TMR[7:0] STEMP[10:3] U U U U U BSENSE[7:0] LKPADDR[6:0] LKPDAT[7:0] U U U U LKP_RD LKP_WR U RTC_FAIL U U U U RTC_SBSC[7:0] RTC_SEC[5:0] RTC_MIN[5:0] U RTC_HR[4:0] U U U RTC_DAY[2:0] U RTC_DATE[4:0] U U RTC_MO[3:0] RTC_YR[7:0] U U U RTC_P[16:14] RTC_P[13:6] RTC_P[5:0] RTC_Q[1:0] RTC_TMIN[5:0] U RTC_THR[4:0] OSC_COMP TEMP_BAT TBYTE_BUSY TEMP_PER[2:0] R R R R U U R R R R R R R U U U U U U R R R R R U U U U U U STEMP[2:0] LKPAUTOI U RTC_WR U U U U U U U U RTC_RD U U U U U U U U U R R U SLEEP U WD_RST U U TEMP_PWR R U R U TEMP_START © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Name PORT3 PORT2 PORT1 PORT0 FLASH ERASE FLSHCTL PGADR I2C EEDATA EECTRL Addr SFR B0 SFR A0 SFR 90 SFR 80 SFR 94 SFR B2 SFR B7 SFR 9E SFR 9F Bit 7 Bit 6 Bit 5 DIO_DIR[15:12] DIO_DIR[11:8] DIO_DIR[7:4] DIO_DIR[3:0] Bit 4 Bit 3 Data Sheet 71M6545/H Bit 2 Bit 1 DIO[15:12] DIO[11:8] DIO[7:4] DIO[3:0] Bit 0 PREBOOT SECURE U FLSH_ERASE[7:0] U FLSH_PEND FLSH_PGADR[6:0] EEDATA[7:0] EECTRL[7:0] FLSH_PSTWR FLSH_MEEN FLSH_PWE U v1.0 © 2008–2011 Teridian Semiconductor Corporation 87 Data Sheet 71M6545/H PDS_6545_009 5.2 I/O RAM Map – Alphabetical Order Table 61 lists I/O RAM bits and registers in alphabetical order. Bits with a write direction (W in column Dir) are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The remaining bits are mapped to the address space 0x2XXX. Bits with R (read) direction can be read by the MPU. Columns labeled Rst and Wk describe the bit values upon reset and wake, respectively. No entry in one of these columns means the bit is either read-only or is powered by the NV supply and is not initialized. Write-only bits return zero when they are read. Locations that are shaded in grey are non-volatile (i.e., battery-backed). T able 61: I/O RAM Map – Alphabetical Order Name ADC_E Location 2704[4] Rst Wk Dir 0 0 R/W Description Enables ADC and VREF. When disabled, reduces bias current. ADC_DIV controls the rate of the ADC and FIR clocks. The ADC_DIV setting determines whether MCK is divided by 4 or 8: 0 = MCK/4 1 = MCK/8 The resulting ADC and FIR clock is as shown below. PLL_FAST = 0 PLL_FAST = 1 MCK 6.291456 MHz 19.660800 MHz ADC_DIV = 0 1.572864 MHz 4.9152 MHz ADC_DIV = 1 0.786432 MHz 2.4576 MHz Connects a 100 µA load to the battery (VBAT_RTC pin). The result of the VBAT_RTC pin measurement. See 2.5.7 71M6545/H Battery Monitor on page 55. CE enable. CE program location. The starting address for the CE program is 1024*CE_LCTN. These bytes contain the chip identification. Chop enable for the reference bandgap circuit. The value of CHOP changes on the rising edge of the internal MUXSYNC signal according to the value in CHOP_E[1:0]: 00 = toggle1 01 = positive 10 = reversed 11 = toggle 1 except at the mux sync edge at the end of an accumulation interval. ADC_DIV 2200[5] 0 0 R/W BCURR BSENSE[7:0] CE_E CE_LCTN[5:0] CHIP_ID[15:8] CHIP_ID[7:0] CHOP_E[1:0] 2704[3] 2885[7:0] 2106[0] 2109[5:0] 2300[7:0] 2301[7:0] 2106[3:2] 0 – 0 – R/W R 0 0 R/W 31 31 R/W 00 R 00 R 0 0 R/W 88 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Name Location Rst Wk Dir Description Data Sheet 71M6545/H CHOPR[1:0] 2709[7:6] 00 00 R/W DIFF0_E DIFF2_E DIFF4_E DIFF6_E DIO_R2[2:0] DIO_R3[2:0] DIO_R4[2:0] DIO_R5[2:0] DIO_R6[2:0] DIO_R7[2:0] DIO_R8[2:0] DIO_R9[2:0] DIO_R10[2:0] DIO_R11[2:0] DIO_RPB[2:0] DIO_DIR[14:12] DIO_DIR[11:8] DIO_DIR[7:4] DIO_DIR[3:0] DIO[14:12] DIO[11:8] DIO[7:4] DIO[3:0] 210C[4] 210C[5] 210C[6] 210C[7] 2455[2:0] 2455[6:4] 2454[2:0] 2454[6:4] 2453[2:0] 2453[6:4] 2452[2:0] 2452[6:4] 2451[2:0] 2451[6:4] 2450[2:0] SFR B0[6:4] SFR A0[7:4] SFR 90[7:4] SFR 80[7:4] SFR B0[3:0] SFR A0[3:0] SFR 90[3:0] SFR 80[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F 0 0 0 0 R/W R/W R/W R/W – R/W F R/W F F R/W The CHOP settings for the remote sensor. 00 = Auto chop. Change every MUX frame. 01 = Positive 10 = Negative 11 = Auto chop (same as 00) Enables IADC0-IADC1 differential configuration. Enables IADC2-IADC3 differential configuration. Enables IADC4-IADC5 differential configuration. Enables IADC6-IADC7 differential configuration. Connects PB and dedicated I/O pins DIO2 through DIO11 to internal resources. If more than one input is connected to the same resource, the MULTIPLE column below specifies how they are combined. MULTIPLE DIO_Rx Resource 0 NONE – 1 Reserved OR 2 T0 (Timer0 clock or gate) OR 3 T1 (Timer1 clock or gate) OR 4 IO interrupt (int0) OR 5 IO interrupt (int1) OR Programs the direction of the first 15 DIO pins. 1 indicates output. See DIO_PV and DIO_PW f or special option for DIO0 and DIO1 outputs. See DIO_EEX[1:0] for special option for DIO2 and DIO3. Note that the direction of DIO pins above 14 is set by DIOx[1]. See PORT_E to avoid power up spikes. The value on the first 15 DIO pins. When written, changes data on pins configured as outputs. Pins as input ignore writes. Note that the data for DIO pins above 14 is set by DIOx[0] . W hen set, converts DIO3 and DIO2 to interface with external EEPROM. DIO2 becomes SDCK and DIO3 becomes bi-directional SDATA. DIO_EEX[1:0] Function 00 Disable EEPROM interface 01 2-Wire EEPROM interface 10 3-Wire EEPROM interface 3-Wire EEPROM interface with separate DO (DIO3) and DI (DIO8) 11 pins. © 2008–2011 Teridian Semiconductor Corporation 89 DIO_EEX[1:0] 2456[7:6] 0 – R/W v1.0 Data Sheet 71M6545/H Name DIO_PV DIO_PW DIO_PX DIO_PY EEDATA[7:0] Location 2457[6] 2457[7] 2458[7] 2458[6] SFR 9E Rst 0 0 0 0 0 Wk – – – – 0 Dir R/W R/W R/W R/W R/W Description Causes VPULSE to be output on DIO1. Causes WPULSE to be output on DIO0. Causes XPULSE to be output on DIO6. Causes YPULSE to be output on DIO7. Serial EEPROM interface data. Serial EEPROM interface control. Status Name Bit ERROR 7 BUSY 6 5 RX_ACK Read/ Write R R R PDS_6545_009 EECTRL[7:0] SFR 9F 0 0 R/W Reset Polarity Description State 0 Positive 1 when an illegal command is received. 0 Positive 1 when serial data bus is busy. 1 indicates that the EEPROM sent an 1 Positive ACK bit. Element 0 VA( -IB)/ A(IA-IB)/2 VA IA Specifies the power equation. EQU[2:0] 3 EQU[2:0] 2106[7:5] 0 0 R/W 4 5* Description 2 element, 4W, 3φ el a 2 element, 4W, 3φ W e 3 element, 4W, 3φ ye Element 1 0 VB(IC-IB)/2 VB B Element 2 VC IC 0 VC C Recommended MUX Sequence IA VA IB B C VC IA VA IB V I C A A IB VB IC V N ote: *The available CE codes implements only equation 5. Contact your local Teridian representative to obtain CE code for equations 3 and 4. EX_XFER EX_RTC1S EX_RTC1M EX_RTCT EX_SPI EX_EEX EX_XPULSE EX_YPULSE EX_WPULSE EX_VPULSE 2700[0] 2700[1] 2700[2] 2700[3] 2701[7] 2700[7] 2700[6] 2700[5] 2701[6] 2701[5] 0 0 R/W Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC, etc. The bits are set by hardware and cannot be set by writing a 1. The bits are reset by writing 0. Note that if one of these interrupts is to enabled, its corresponding 8051 EX enable bit must also be set. See 2.4.10 Interrupts, for details. 90 © 2008–2011 Teridian Semiconductor Corporation v1.0 PDS_6545_009 Name Location Rst Wk Dir Data Sheet 71M6545/H Description Determines the number of ADC cycles in the ADC decimation FIR filter. PLL_FAST = 1: FIR_LEN[1:0] ADC Cycles 00 141 01 288 10 384 PLL_FAST = 0: FIR_LEN[1:0] ADC Cycles 00 135 01 276 10 Not Allowed The ADC LSB size and full-scale values depend on the FIR_LEN[1:0] setting. Refer to Table 73 on page 106 and Table 91 on page 122 f or details. Flash Erase Initiate FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for FLSH_ERASE in order to initiate the appropriate Erase cycle. (default = 0x00). 0x55 – Initiate Flash Page Erase cycle. Must be proceeded by a write to FLSH_PGADR[6:0] (SFR 0xB7). 0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a write to FLSH_MEEN (SFR 0xB2) and the debug (CC) port must be enabled. Any other pattern written to FLSH_ERASE has no effect. Mass Erase Enable 0 = Mass Erase disabled (default). 1 = Mass Erase enabled. Must be re-written for each new Mass Erase cycle. Indicates that a posted flash write is pending. If another flash write is attempted, it is ignored. Flash Page Erase Address Flash Page Address (page 0 thru 63) that is erased during the Page Erase cycle. (default = 0x00). Must be re-written for each new Page Erase cycle. Enables posted flash writes. When 1, and if CE_E = 1, flash write requests are stored in a one element deep FIFO and are executed when CE_BUSY falls. FLSH_PEND can be read to determine the status of the FIFO. If FLSH_PSTWR = 0 or if CE_E = 0, flash writes are immediate. FIR_LEN[1:0] 210C[2:1] 0 0 R/W FLSH_ERASE[7:0] SFR 94[7:0] 0 0 W FLSH_MEEN SFR B2[1] 0 0 W FLSH_PEND SFR B2[3] 0 0 R FLSH_PGADR[6:0] SFR B7[7:1] 0 0 W FLSH_PSTWR SFR B2[2] 0 0 R/W v1.0 © 2008–2011 Teridian Semiconductor Corporation 91 Data Sheet 71M6545/H Name Location Rst Wk Dir Description PDS_6545_009 FLSH_PWE SFR B2[0] 0 0 R/W FLSH_RDE FLSH_UNLOCK[3:0] FLSH_WRE IE_XFER IE_RTC1S IE_RTC1M IE_RTCT IE_SPI IE_EEX IE_XPULSE IE_YPULSE IE_WPULSE IE_VPULSE INTBITS LKPADDR[6:0] LKPAUTOI LKPDAT[7:0] LKP_RD LKP_WR 2702[2] 2702[7:4] 2702[1] SFR E8[0] SFR E8[1] SFR E8[2] SFR E8[3] SFR F8[7] SFR E8[7] SFR E8[6] SFR E8[5] SFR F8[4] SFR F8[3] 2707[6:0] 2887[6:0] 2887[7] 2888[7:0] 2889[1] 2889[0] – 0 – – 0 – R R/W R Program Write Enable 0 = MOVX commands refer to External RAM Space, normal operation (default). 1 = MOVX @DPTR,A moves A to External Program Space (Flash) @ DPTR. This bit is automatically reset after each byte written to flash. Writes to this bit are inhibited when interrupts are enabled. Indicates that the flash may be read by ICE or SPI slave. FLSH_RDE = (!SECURE) Must be a 2 to enable any f lash modification. See the description of Flash security f or more details. Indicates that the flash may be written through ICE or SPI slave ports. Interrupt flags for external interrupts 2 and 6. These flags monitor the source of the int6 and int2 interrupts (external interrupts to the MPU core). These flags are set by hardware and must be cleared by the software interrupt handler. The IEX2 (SFR 0xC0[1]) and IEX6 (SFR 0xC0[5]) interrupt flags are automatically cleared by the MPU core when it vectors to the interrupt handler. IEX2 and IEX6 must be cleared by writing zero to their corresponding bit positions in SFR 0xC0, while writing ones to the other bit positions that are not being cleared. Interrupt inputs. The MPU may read these bits to see the input to external interrupts INT0, INT1, up to INT6. These bits do not have any memory and are primarily intended for debug use. The address for reading and writing the RTC lookup RAM. Auto-increment flag. When set, LKPADDR[6:0] auto increments every time LKP_RD or LKP_WR is pulsed. The incremented address can be read at LKPADDR. The data for reading and writing the RTC lookup RAM. Strobe bits for the RTC lookup RAM read and write. When set, the LKPADDR[6:0] and LKPDAT registers is used in a read or write operation. When a strobe is set, it stays set until the operation completes, at which time the strobe is cleared and LKPADDR[6:0] is incremented if LKPAUTOI is set. MPU clock rate is: MPU Rate = MCK Rate * 2-(2+MPU_DIV[2:0]). The maximum value for MPU_DIV[2:0] is 4. Based on the default values of the PLL_FAST bit and MPU_DIV[2:0], the power up MPU rate is 4.92MHz * ¼ = 1.23 MHz. The minimum MPU clock rate is 38.4 kHz when PLL_FAST = 1. Selects which ADC input is to be converted during time slot 0. Selects which ADC input is to be converted during time slot 1. v1.0 0 0 R/W – 0 0 0 0 0 – 0 0 0 0 0 R R/W R/W R/W R/W R/W MPU_DIV[2:0] 2200[2:0] 0 0 R/W MUX0_SEL[3:0] MUX1_SEL[3:0] 92 2105[3:0] 2105[7:4] 0 0 0 0 R/W R/W © 2008–2011 Teridian Semiconductor Corporation PDS_6545_009 Name MUX2_SEL[3:0] MUX3_SEL[3:0] MUX4_SEL[3:0] MUX5_SEL[3:0] MUX6_SEL[3:0] MUX7_SEL[3:0] MUX8_SEL[3:0] MUX9_SEL[3:0] MUX10_SEL[3:0] MUX_DIV[3:0] Reserved Reserved DIO55_EN Reserved Reserved OSC_COMP PB_STATE PERR_RD PERR_WR PLL_OK PLL_FAST Location 2104[3:0] 2104[7:4] 2103[3:0] 2103[7:4] 2102[3:0] 2102[7:4] 2101[3:0] 2101[7:4] 2100[3:0] 2100[7:4] 2457[0] 2457[5:4] 2457[2] 2457[1] 2456[3:0] 28A0[5] SFR F8[0] SFR FC[6] SFR FC[5] SFR F9[4] 2200[4] Rst 0 0 0 0 0 0 0 0 0 0 0 00 0 Wk 0 0 0 0 0 0 0 0 0 0 – – – Dir R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W Data Sheet 71M6545/H Description Selects which ADC input is to be converted during time slot 2. Selects which ADC input is to be converted during time slot 3. Selects which ADC input is to be converted during time slot 4. Selects which ADC input is to be converted during time slot 5. Selects which ADC input is to be converted during time slot 6. Selects which ADC input is to be converted during time slot 7. Selects which ADC input is to be converted during time slot 8. Selects which ADC input is to be converted during time slot 9. Selects which ADC input is to be converted during time slot 10. MUX_DIV[3:0] is the number of ADC time slots in each MUX frame. The maximum number of time slots is 11. Reserved. Must be 0. Reserved. Must be 00. Enables DIO55 DIO55_EN = 0: DIO55 is disabled DIO55_EN = 1: DIO55 is enabled Reserved. Must be 0. Reserved. Must be 0000. Enables the automatic update of RTC_P[16:0] and RTC_Q [1:0]every time the temperature is measured. The de-bounced state of the PB pin. The 71M6545/H sets these bits to indicate that a parity error on the remote sensor has been detected. Once set, the bits are remembered until they are cleared by the MPU. Indicates that the clock generation PLL is settled. Controls the speed of the PLL and MCK. 1 = 19.66 MHz (XTAL * 600) 0 = 6.29 MHz (XTAL * 192) Determines the maximum width of the pulse (low-going pulse). Maximum pulse width is (2*PLS_MAXWIDTH + 1)*TI. Where TI is PLS_INTERVAL. If PLS_INTERVAL = 0 or PLS_MAXWIDTH=255, no width checking is performed and the output pulses have 50% duty cycle. 0– 0000 – 0 0 0 0 0 – 0 0 0 0 PLS_MAXWIDTH[7:0] 210A[7:0] FF FF R/W v1.0 © 2008–2011 Teridian Semiconductor Corporation 93 Data Sheet 71M6545/H Name Location Rst Wk Dir PDS_6545_009 Description Determines the Interval time. The time between FIFO outputs is PLS_INTERVAL[7:0]*4*203ns. If PLS_INTERVAL[7:0] = 0, the FIFO is not used and pulses are output as soon as the CE issues them. Assuming a that the CE code is written to generate 6 pulses in one integration interval, when the FIFO is enabled (i.e., PLS_INTERVAL[7:0] ≠ 0) and SUM_SAMPS = 2520, PLS_INTERVAL[7:0] must be written with 81 so that the six pulses are evenly spaced in time over the integration interval and the last pulse is issued just prior to the end of the interval. Inverts the polarity of WPULSE and VARPULSE. Normally, these pulses are active low. When inverted, they become active high. PLS_INV has no effect on XPULSE or YPULSE. Enables outputs from the DIO0-DIO14 pins. PORT_E = 0 blocks the momentary output pulse that occurs when DIO0-DIO14 are reset on power up. Enables the 8x pre-amplifier. Indicates that pre-boot sequence is active. W hen the MPU writes a non-zero value to RCMD, the 71M6545/H issues a command to the appropriate remote sensor. When the command is complete, the 71M6545/H clears RCMD. W hen set, causes a reset. Controls how the 71M6545/H drives the power pulse f or the 71M6xxx. When set, the power pulse is driven high and low. When cleared, it is driven high followed by an open circuit flyback interval. Enables the remote interface. Response from remote read request. Register for analog RTC frequency adjustment. Indicates that a count error has occurred in the RTC and that the time is not trustworthy. This bit can be cleared by writing a 0. RTC adjust. See 2.5.4 Real-Time Clock (RTC). 0x0FFBF ≤ RTC_P ≤ 0x10040 Note: RTC_P[16:0] and RTC_Q[1:0] f orm a single 19-bit RTC adjustment value. RTC adjust. See 2.5.4 Real-Time Clock (RTC). Note: RTC_P[16:0] and RTC_Q[1:0] f orm a single 19-bit RTC adjustment value. Freezes the RTC shadow register so it is suitable for MPU reads. When RTC_RD is read, it returns the status of the shadow register: 0 = up to date, 1 = frozen. v1.0 PLS_INTERVAL[7:0] 210B[7:0] 0 0 R/W PLS_INV PORT_E PRE_E PREBOOT RCMD[4:0] RESET RFLY_DIS RMT2_E RMT4_E RMT6_E RMT_RD[15:8] RMT_RD[7:0] RTCA_ADJ[6:0] RTC_FAIL RTC_P[16:14] RTC_P[13:6] RTC_P[5:0] RTC_Q[1:0] RTC_RD 210C[0] 270C[5] 2704[5] SFRB2[7] SFR FC[4:0] 2200[3] 210C[3] 2709[3] 2709[4] 2709[5] 2602[7:0] 2603[7:0] 2504[6:0] 2890[4] 289B[2:0] 289C[7:0] 289D[7:2] 289D[1:0] 2890[6] 0 0 0 – 0 0 0 0 0 0 – 0 0 0 R/W R/W R/W R R/W W R/W 0 0 40 0 4 0 0 0 0 0 0 – 0 4 0 0 0 0 R/W R R/W R/W R/W R/W R/W 94 © 2008–2011 Teridian Semiconductor Corporation PDS_6545_009 Name RTC_SBSC[7:0] RTC_TMIN[5:0] RTC_THR[4:0] Location 2892[7:0] 289E[5:0] 289F[4:0] Rst Wk Dir –– R 0 – R/W 0 – R/W Data Sheet 71M6545/H Description Time remaining since the last 1 second boundary. LSB=1/128 second. The target minutes register. See RTC_THR below. The target hours register. The RTC_T interrupt occurs when RTC_MIN [5:0] becomes equal to RTC_TMIN[5:0] and RTC_HR[4:0] becomes equal to RTC_THR[4:0]. Freezes the RTC shadow register so it is suitable for MPU writes. When RTC_WR is cleared, the contents of the shadow register are written to the RTC counter on the next RTC clock (~1 kHz). When RTC_WR is read, it returns 1 as long as RTC_WR is set. It continues to return one until the RTC counter actually updates. The RTC interface. These are the year, month, day, hour, minute and second parameters for the RTC. The RTC is set by writing to these registers. Year 00 and all others divisible by 4 are defined as a leap year. SEC 00 to 59 MIN 00 to 59 HR 00 to 23 (00=Midnight) DAY 01 to 07 (01=Sunday) DATE 01 to 31 MO 01 to 12 YR 00 to 99 Each write operation to one of these registers must be preceded by a write to 0x20A0. Real Time Monitor enable. When 0, the RTM output is low. Four RTM probes. Before each CE code pass, the values of these registers are serially output on the RTM pin. The RTM registers are ignored when RTM_E = 0. Note that RTM0 is 10 bits wide. The others assume the upper two bits are 00. Inhibits erasure of page 0 and flash memory addresses above the beginning of CE code as defined by CE_LCTN[5:0]. Also inhibits the reading of flash memory by external devices (SPI or ICE port). Puts the 71M6545/H to sleep. Ignored if system power is present. The 71M6545/H wakes when the Wake timer times out, when push button is pushed, or when system power returns. SPI command. 8-bit command from the bus master. SPI port enable. Enables the SPI interface on pins SPI_DI, SPI_DO, SPI_CSZ and SPI_CKI. Limits SPI writes to SPI_CMD and a 16 byte region in DRAM. No other writes are permitted. RTC_WR 2890[7] 0 0 R/W RTC_SEC[5:0] RTC_MIN[5:0] RTC_HR[4:0] RTC_DAY[2:0] RTC_DATE[4:0] RTC_MO[3:0] RTC_YR[7:0] 2893[5:0] 2894[5:0] 2895[4:0] 2896[2:0] 2897[4:0] 2898[3:0] 2899[7:0] – – – – – – – – – – – – – – R/W RTM_E RTM0[9:8] RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] SECURE 2106[1] 210D[1:0] 210E[7:0] 210F[7:0] 2110[7:0] 2111[7:0] SFR B2[6] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W SLEEP SPI_CMD SPI_E SPI_SAFE 28B2[7] SFR FD[7:0] 270C[4] 270C[3] 0 – 1 0 0 – 1 0 W R R/W R/W v1.0 © 2008–2011 Teridian Semiconductor Corporation 95 Data Sheet 71M6545/H Name Location Rst Wk Dir Description SPI_STAT contains the status results from the previous SPI transaction PDS_6545_009 SPI_STAT 2708[7:0] 0 0 R Bit 7 - 71M6545/H ready error: the 71M6545/H was not ready to read or write as directed by the previous command. Bit 6 - Read data parity: This bit is the parity of all bytes read from the 71M6545/H in the previous command. Does not include the SPI_STAT byte. Bit 5 - Write data parity: This bit is the overall parity of the bytes written to the 71M6545/H in the previous command. It includes CMD and ADDR bytes. Bit 4:2 - Bottom 3 bits of the byte count. Does not include ADDR and CMD bytes. One, two, and three byte instructions return 111. Bit 1 - SPI FLASH mode: This bit is zero when the TEST pin is zero. Bit 0 - SPI FLASH mode ready: Used in SPI FLASH mode. Indicates that the flash is ready to receive another write instruction. STEMP[10:3] STEMP[2:0] SUM_SAMPS[12:8] SUM_SAMPS[7:0] TBYTE_BUSY TEMP_22[10:8] TEMP_22[7:0] TEMP_BAT Reserved 2881[7:0] 2882[7:5] 2107[4:0] 2108[7:0] 28A0[3] 230A[2:0] 230B[7:0] 28A0[4] 28A0[7] – – 0 0 0 0 0 – – 0 0 – – – R R R/W R R R/W R/W The result of the temperature measurement. The number of multiplexer cycles (frames) per XFER_BUSY interrupt. Maximum value is 8191 cycles. Indicates that hardware is still writing the 0x28A0 byte. Additional writes to this byte are locked out while it is one. Write duration could be as long as 6 ms. Storage location for STEMP[10:0] at 22C. STEMP[10:0] is an 11 bit word. Causes VBAT _RTC to be measured whenever a temperature measurement is performed. Reserved. Must always be zero. Sets the period between temperature measurements. Automatic measurements can be enabled in any mode (MSN or SLP). TEMP_PER = 0 disables automatic temperature updates, in which case TEMP_START may be used by the MPU to initiate a one-shot temperature measurement. TEMP_PER 0 1-6 7 Time (seconds) No temperature updates 2 (3 + TEMP _ PER ) TEMP_PER[2:0] 28A0[2:0] 0 – R/W Continuous updates TEMP_PWR 28A0[6] 0 – R/W Selects the power source for the temp sensor: 1 = V3P3D, 0 = VBAT_RTC. This bit is ignored in SLP mode, where the temp sensor is always powered by VBAT_RTC. v1.0 96 © 2008–2011 Teridian Semiconductor Corporation PDS_6545_009 Name TEMP_START TMUX[5:0] TMUX2[4:0] TMUXR2[2:0] TMUXR4[2:0] TMUXR6[2:0] Location 28B4[6] 2502[5:0] 2503[4:0] 270A[2:0] 270A[6:4] 2709[2:0] Rst Wk Dir 0 – – 0 – – R/W R/W R/W Data Sheet 71M6545/H Description W hen TEMP_PER = 0 automatic temperature measurements are disabled, and TEMP_START may be set by the MPU to initiate a one-shot temperature measurement. TEMP_START i s ignored in SLP mode. Hardware clears TEMP_START when the temperature measurement is complete. Selects one of 32 signals for TMUXOUT. See 2.5.14 for details. Selects one of 32 signals for TMUX2OUT. See 2.5.14 f or details. The TMUX setting for the remote isolated sensors (71M6xx3). The silicon version index. This word may be read by firmware to determine the silicon version. VERSION[7:0] Silicon Version 0001 0001 A01 0001 0011 A03 0001 0011 B01 Brings the ADC reference voltage out to the VREF pin. This feature is disabled when VREF_DIS=1. Disables the internal ADC v oltage reference. This word describes the source of power and the status of the VDD. VSTAT[2:0] 000 001 Description System Power OK. V3P3A>3.0v. Analog modules are functional and accurate. [V3AOK,V3OK]=11 System Power Low. 2.8v2.0. Flash writes are inhibited. If the TRIMVDD[5] fuse is blown, PLL_FAST is cleared. [V3AOK,V3OK]=00, [VDDOK,VDDgt2]=01 VDD