78M6631

19-6039; Rev 1; 1/12 78M6631 3-Phase PowerMeasurement IC DATA SHEET DS_6631_056 DESCRIPTION The Teridian™ 78M6631 is a highly integrated 3-phase power measurement and monitoring system-on-chip (SoC), with a 10 MHz 8051-compatible MPU core and Single Converter Technology® containing a 22-bit deltasigma converter and 32-bit compute engine (CE). The 78M6631 has been designed specifically for a wide variety of applications requiring 3-phase power and quality measurements. It supports both Delta and Wye configurations. At the measurement interface, the device provides six analog inputs including three differential current and three voltage for interfacing to current and voltage sensors. The device provides better than 0.5% accuracy over a wide 2000:1 dynamic range. The integrated MPU core and 128 KB of flash memory provide a flexible means of configuration, postprocessing, data formatting, interfacing to host processor via a UART or SPI interface, or using DIO pins for LEDs or relay control. Complete firmware is available from Maxim and can be loaded into the IC during manufacturing test. FEATURES • < 0.5% Watt Accuracy Over 2000:1 Current Range and Over Temperature • Exceeds IEC 62053/ANSI C12.20 Standards • Voltage Reference < 40 ppm/°C • Six Analog Inputs Supporting 3-Phase Voltage and Current Measurement Inputs • Pin- or Biselectable Delta or Wye Configuration • 22-Bit Delta-Sigma ADC with Independent 32Bit Compute Engine (CE) • 8-Bit MPU (80515), One Clock Cycle per Instruction with 4 KB MPU XRAM • 128 KB Flash with Security • 32 kHz Time Base with Hardware Watchdog Timer • UART, I2C, and High-Speed Slave SPI Host Interface Options • 17 General-Purpose 5 V Tolerant I/O Pins • Packaged in a RoHS-Compliant (6/6) Lead(Pb)-Free 56-Pin TQFN • Application Firmware Includes (per Phase): o True RMS Current and Voltage Calculations o Active, Reactive, Apparent, Fundamental, and Harmonic Power Calculations o Fundamental and Harmonic Current and Voltage Calculations o Line Frequency and Power Factor Calculations o Phase Compensation (±18° at 60 Hz) o Built-In Calibration Routines o Programmable Alarm Thresholds o Command Line (UART) Communications o High-Speed SPI Communications Teridian is a trademark and S ingle Converter Technology is a registered trademark of Maxim Integrated Products, Inc. Rev 1 1 78M6631 Data Sheet DS_6631_056 Table of Contents 1 Hardware Functional Description ................................................................................................. 5 1.1 Hardware Overview................................................................................................................. 5 1.2 Device Reset .......................................................................................................................... 7 1.3 Power Management ................................................................................................................ 7 1.3.1 Voltage Regulator........................................................................................................ 7 1.3.2 Power Fault Management............................................................................................ 7 1.4 Analog Front-End (AFE) .......................................................................................................... 8 1.4.1 Analog Current and Voltage Inputs .............................................................................. 8 1.5 Digital Computation Engine (CE) ............................................................................................. 9 1.6 80515 MPU Core .................................................................................................................. 10 1.6.1 SFRs......................................................................................................................... 10 1.7 RAM ..................................................................................................................................... 10 1.8 IORAM.................................................................................................................................. 10 1.9 Flash..................................................................................................................................... 10 1.9.1 Program Security....................................................................................................... 10 1.10 Oscillator............................................................................................................................... 11 1.11 PLL and Internal Clock Generation ........................................................................................ 11 1.12 Real-Time Clock (RTC) ......................................................................................................... 11 1.13 Hardware Watchdog Timer.................................................................................................... 11 1.14 Temperature Sensor ............................................................................................................. 12 1.15 General Purpose Digital I/O................................................................................................... 12 1.16 D/Y Selection Pin .................................................................................................................. 12 1.17 EEPROM Interface................................................................................................................ 12 1.18 SPI Slave Port ...................................................................................................................... 12 1.19 Test Port ............................................................................................................................... 13 1.20 UART.................................................................................................................................... 13 1.21 In Circuit Emulator (ICE) Port ................................................................................................ 14 Electrical Specifications .............................................................................................................. 15 2.1 Absolute Maximum Ratings ................................................................................................... 15 2.2 Recommended External Components ................................................................................... 16 2.3 Recommended Operating Conditions .................................................................................... 16 2.4 Performance Specifications ................................................................................................... 17 2.4.1 Input Logic Levels ..................................................................................................... 17 2.4.2 Output Logic Levels................................................................................................... 17 2.4.3 Power-Fault Comparator ........................................................................................... 17 2.4.4 Power Supply Monitor ............................................................................................... 18 2.4.5 Supply Current .......................................................................................................... 18 2.4.6 Crystal Oscillator ....................................................................................................... 18 2.4.7 Temperature Sensor.................................................................................................. 19 2.4.8 VREF ........................................................................................................................ 19 2.4.9 ADC Converter, V3P3A Referenced .......................................................................... 20 2.5 Timing Specifications ............................................................................................................ 21 2.5.1 Flash Memory ........................................................................................................... 21 2.5.2 EEPROM Interface .................................................................................................... 21 2.5.3 RESET ...................................................................................................................... 21 2.5.4 SPI Slave Port ........................................................................................................... 22 Packaging .................................................................................................................................... 23 3.1 56-Pin QFN Package ............................................................................................................ 23 3.2 Pinout ................................................................................................................................... 23 3.2.1 56-Pin QFN Package Outline..................................................................................... 24 3.2.2 Recommended PCB Land Pattern for the QFN-56 Package ...................................... 25 Pin Descriptions .......................................................................................................................... 26 Rev 1 2 3 4 2 DS_6631_056 4.1 4.2 4.3 5 6 7 78M6631 Data Sheet Power and Ground Pins ........................................................................................................ 26 Analog Pins........................................................................................................................... 26 Digital Pins............................................................................................................................ 27 I/O Equivalent Circuits................................................................................................................. 28 Ordering Information ................................................................................................................... 29 Contact Information ..................................................................................................................... 29 Revision History .................................................................................................................................. 30 Rev 1 3 78M6631 Data Sheet DS_6631_056 Figures Figure 1: 78M6631 IC Functional Block Diagram ..................................................................................... 6 Figure 2: AFE Block Diagram................................................................................................................... 8 Figure 3: Functions Defined by V1 ......................................................................................................... 11 Figure 4: SPI Slave Port: Typical Read and Write Operations ................................................................ 13 Figure 5: SPI Slave Port Timing ............................................................................................................. 22 Figure 6: Pinout for QFN-56 Package .................................................................................................... 23 Figure 7: PCB Land Pattern for QFN-56 Package .................................................................................. 25 Figure 8: I/O Equivalent Circuits............................................................................................................. 28 Tables Table 1: SPI Command Description ....................................................................................................... 13 Table 2: Absolute Maximum Ratings ...................................................................................................... 15 Table 3: Recommended External Components ...................................................................................... 16 Table 4: Recommended Operating Conditions ....................................................................................... 16 Table 5: Input Logic Levels .................................................................................................................... 17 Table 6: Output Logic Levels ................................................................................................................. 17 Table 7: Power-Fault Comparator Performance Specifications ............................................................... 17 Table 8: Power Supply Monitor Performance Specifications (BME= 1).................................................... 18 Table 9: Supply Current Performance Specifications.............................................................................. 18 Table 10: Crystal Oscillator Performance Specifications......................................................................... 18 Table 11: Temperature Sensor Performance Specifications ................................................................... 19 Table 12: VREF Performance Specifications.......................................................................................... 19 Table 13: ADC Converter Performance Specifications ........................................................................... 20 Table 14: Flash Memory Timing Specifications ...................................................................................... 21 Table 15: EEPROM Interface Timing ..................................................................................................... 21 Table 16: RESET Timing ....................................................................................................................... 21 Table 17: SPI Slave Port Timing ............................................................................................................ 22 Table 19: Power and Ground Pins ......................................................................................................... 26 Table 20: Analog Pins............................................................................................................................ 26 Table 21: Digital Pins............................................................................................................................. 27 Table 22: Ordering Information .............................................................................................................. 29 4 Rev 1 DS_6631_056 78M6631 Data Sheet 1 Hardware Functional Description 1.1 Hardware Overview The Teridian 78M6631 single-chip power measurement and monitoring device integrates all the primary AC measurement and control blocks required to implement the 3-phase power measurement and monitoring system. The 78M6631 includes: • • • • • • • • Six input analog front-end (AFE) (3 Differential Current/3 Voltage) Independent digital computation engine (CE) 8051-compatible microprocessor (MPU) which executes one instruction per clock cycle (80515) Precision voltage reference Temperature sensor RAM and flash memory A variety of I/O pins 2 Communication Interfaces: UART, SPI, and I C (Master) Various current sensor technologies are supported including Current Transformers (CT), Resistive Shunts, and Rogowski coils. The 32-bit compute engine (CE) of the 78M6631 sequentially process the samples from the analog inputs on pins IA, IB, IC, VA, VB, and VC and performs calculations to measure active power (Watts), reactive power (VARs), apparent power (VAs), power factor, fundamental power, and harmonic power for three independent phases. RMS, fundamental, and harmonic currents and voltages are also computed for each phase. Totals are available for most results. Figure 1 provides a block diagram of the 78M6631 IC. A detailed description of the various functional blocks follows. Refer to the applicable Firmware Description Document for additional supported functionality. Rev 1 5 78M6631 Data Sheet VREF IAP IAN IBP IBN ICP ICN VA VB VC 16 V3P3D TEMP 80MHz OSC (32. 768kHz) CE_ PROG VBIAS VADC CE VREF VREF RPULSE WPULSE XPULSE YPULSE YPULSE XPULSE WPULSE RPULSE DS_6631_056 V3P3A ∆Σ ADC CONVERTER VBIAS FIR RTM to TMUX VOLT REG GNDA V3P3SYS V3P3D VBAT MUXP GNDD 2.5V to Logic MULTI PURPOSE IO 32 CE_ DATA MCK PLL CK_CE CK_ MPU FLASH 128KB XRAM 4kB XIN XOUT RTC CKTESTI CKTEST DIO3 DIO4/SDCK DIO5/SDATA DIO6 DIO8 DIO9 D/Y DIO11 DIO17 CKTEST TEST MODE EEPROM /IF SDATA SDCK DIO24 DIO25 DIO29 DIO30 DIO45 DIO47 RX TX DIGITAL / O I UART XRAM BUS 8 SPI SLAVE DIO_4... PCSZ PCLK PSDI PSDO DIO51 DIO53 DIO55 PSDI PCSZ PSDO PCLK 80515 MPU E_ RST E_ TCLK E_ RXTX SFR EMULATOR E_ RXTX E_ TCLK E_ RSTZ V1 POWER FAULT FAULTZ ICE_E TEST MUX TMUXOUT RESET ICE_E Figure 1: 78M6631 IC Functional Block Diagram 6 Rev 1 DS_6631_056 78M6631 Data Sheet 1.2 Device Reset W hen the RESET pin is pulled high, all digital activity stops. Only the oscillator and RTC module continue to run. Additionally, all IORAM bits are set to their default states. As long as V1 (the input voltage at the power fault block) is greater than VBIAS, the internal 2.5 V regulator continues to provide power to the digital section. Once initiated, the reset mode persists until the reset timer times out. This occurs in 4096 cycles of the crystal clock after RESET goes low, at which time the MPU begins executing its preboot and boot sequences from address 0x0000. 1.3 Power Management 1.3.1 Voltage Regulator The 78M6631 provides an on-chip voltage regulator to create a 2.5 V supply for the digital logic. This regulator can be run off of the V3P3SYS or VBAT inputs depending upon power availability. 1.3.2 Power Fault Management The 78M6631 provides for both hardware and software controlled power fault management. The V1 pin is connected to a comparator to monitor system power fault conditions. When the input to the comparator falls (V1 < VBIAS) the device can enter a BROWNOUT mode, if supported in firmware and there is sufficient voltage on VBAT, that reduces the MPU rate to 32 kHz and disables all the measurement frontend circuits. If the overhead on VBAT is insufficient to maintain a BROWNOUT mode, then the device can also attempt to enter a SLEEP mode where only RTC functions are active. If there is not sufficient voltage on VBAT (or it is not supported), then the part enters RESET mode when the comparator fails. Rev 1 7 78M6631 Data Sheet DS_6631_056 1.4 Analog Front-End (AFE) The AFE functions as a data acquisition system, controlled by the MPU. The main blocks in the AFE consist of an input multiplexer, a delta-sigma A/D converter, a FIR decimation filter and a voltage reference. The metrology input signals (IAP, IAN, IBP, IBN, ICP, ICN, VA, VB, VC, and TEMP) are multiplexed before being sampled by the ADC. The ADC output is decimated by the FIR filter and the results are stored in RAM where they can be accessed by the CE and the MPU. The functionality of the AFE is established for various system requirements with different CE code. AFE programmability includes, but is not limited to: • • • • Input multiplexer settings Voltage supply and temperature monitor inputs ADC sampling rate FIR length/resolution IAP IAN IBP IBN ICP ICN VA VB VC + - VREF ∆Σ ADC CONVERTER VBIAS VBIAS V3P3A + VREF FIR + + - MUX V3P3D VREF CROSS MUX CTRL CK32 FIR_DONE FIR_START TEMP MUX 4.9152 MHz Figure 2: AFE Block Diagram 1.4.1 Analog Current and Voltage Inputs W ith all CE code implementations for the 78M6631, pins IAP, IAN, IBP, IBN, ICP, ICN, VA, VB, and VC are analog inputs to the AFE for measuring current and voltage. Various current sensor technologies can be supported including Current Transformers, Resistive Shunts, and Rogowski coils. 8 Rev 1 DS_6631_056 78M6631 Data Sheet 1.5 Digital Computation Engine (CE) The CE, a dedicated 32-bit digital signal processor, performs the back-end computations. CE calculations include: • • • • • • • • • • Gain and offset compensation Delay compensation on all channels 90° phase shift for VAR calculations Frequency measurement Accumulation for voltage and current RMS and power computation Active, reactive, apparent, fundamental, and harmonic power calculation Fundamental and harmonic current and voltage calculations Monitoring of the input signal frequency (for frequency and phase information) Monitoring of the input signal amplitude (for sag detection) Temperature acquisition Due to the custom nature and complexity of the CE, the CE code is part of the installed firmware and is not modified by the user. Contact Maxim support for more information regarding CE code. Rev 1 9 78M6631 Data Sheet DS_6631_056 1.6 80515 MPU Core The 78M6631 includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Normally, a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte instructions are performed in a single machine cycle (MPU clock cycle). This leads to an 8x average performance improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency. 1.6.1 SFRs Several custom Special Function Registers (SFR) are implemented in the 78M6631’s 80515 MPU. Refer to the 78M6631 Programmer’s Reference Manual f or more information regarding the mapping of functionality to specific SFR and IORAM addresses. 1.7 RAM The CE and MPU share a single, general purpose 4KB RAM (also referred to as XRAM) for data. The XRAM is natively accessible as 32-bit words from the CE and on 8-bit boundaries from the CPU. The XRAM is accessed by the CPU through addresses 0x0000 to 0x0FFF. 1.8 IORAM The MPU accesses most of its external input and output functionality as well as programmable functionality through memory mapped IO (IORAM). The IORAM is accessed by the CPU as data addresses 0x2000 to 0x20FF. 1.9 Flash The 78M6631 includes 128 KB of on-chip flash memory. For read/write access from the CPU, the flash is broken into four 32 KB banks that are managed by SFR settings. For erasing of the flash memory from the CPU, the flash is segmented into individual 1024-byte pages and also controlled by SFR settings. 1.9.1 Program Security The 78M6631 has functionality to guarantee the security of the user’s MPU and CE program code. When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE operations are blocked. Security is enabled by MPU code that is executed in a pre-boot interval before the primary boot sequence begins. Once security is enabled, the only way to disable it is to perform a global erase of the flash, followed by a chip reset. 10 Rev 1 DS_6631_056 78M6631 Data Sheet 1.10 Oscillator The 78M6631 oscillator drives a standard 32.768 kHz quartz crystal. These crystals are accurate and do not require a high-current oscillator circuit. The 78M6631 oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. The oscillator is powered directly and only from V3P3D, which therefore must be connected to a DC voltage source not to exceed 4 V. Since the oscillator is self-biasing, an external resistor must not be connected across the crystal. 1.11 PLL and Internal Clock Generation Timing for the device is derived from the 32.768 kHz crystal oscillator output. The PLL and on-chip timing functions provide several clocks which include: • • • • The MPU clock (CKMPU) The emulator clock (2 x CKMPU) The clock for the CE (CKCE) The delta-sigma ADC and FIR clock(CKADC, CKFIR) These internal clocks can be adjusted for various programmable rates which affect device functionality. Refer to the 78M6631 Programmer’s Reference Manual f or more information regarding the programmability of the 78M6631 PLL and internal clock generation modules. 1.12 Real-Time Clock (RTC) The RTC circuit is driven directly by the crystal oscillator. The RTC consists of a counter chain and output registers. The counter chain consists of registers for seconds, minutes, hours, day of week, day of month, month, and year (including leap years). Refer to the 78M6631 Programmer’s Reference Manual f or more information regarding the use of the 78M6631 RTC. 1.13 Hardware Watchdog Timer V1 V3P3 V3P3 - 10mV V3P3 400mV Normal operation, WDT enabled VBIAS WDT disabled In addition to the basic watchdog timer included in the 80515 MPU, an independent, robust, fixed-duration, watchdog timer (WDT) is included in the device. It uses the crystal oscillator as its time base and must be refreshed by the MPU firmware at least every 1.5 seconds. When not refreshed on time the WDT overflows, and the part is reset as if the RESET pin were pulled high, except that the IORAM bits are maintained. 4096 oscillator cycles (or 125 ms) after the WDT overflow, the MPU is launched from program address 0x0000. Asserting ICE_E deactivates the WDT. The WDT can also be disabled by connecting the V1 pin to V3P3D. This also deactivates V1 power fault detection. Since there is no method in firmware to disable the crystal oscillator or the WDT, it is guaranteed that whatever state the part might find itself in, upon watchdog overflow, the part is reset to a known state. Battery modes 0V Figure 3: Functions Defined by V1 Rev 1 11 78M6631 Data Sheet DS_6631_056 1.14 Temperature Sensor The device includes an on-chip temperature sensor for determining the temperature of the bandgap reference. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system. 1.15 General-Purpose Digital I/O The 78M6631 includes 17 general-purpose digital I/O pins. As inputs, these pins are 5V compatible (no current-limiting resistors are needed). On reset or power-up, all DIO pins are inputs. Their input/output directions are subsequently set by the MPU. The digital I/O pins can be categorized as follows: • • • • • • • • • • DIO3 DIO4, DIO5 DIO6 DIO8, DIO9, DIO11 DIO17 DIO24, DIO25 DIO29, DIO30 DIO45, DIO47 DIO51 DIO53, DIO55 (1 (2 (1 (3 (1 (2 (2 (2 (1 (2 pin) pins) pin) pins) pin) pins) pins) pins) pin) pins) DIO pin DIO/EEPROM DIO pin (multifunction) DIO pins DIO pin DIO pins DIO pins DIO pins DIO pin DIO pins 1.16 D/Y Selection Pin The D/Y pin selects either the Delta or the Wye configuration. At power-on, the Delta/Wye selection register assumes the state of the D/Y pin. The register value can be modified by the software overriding the state of the D/Y pin. 1.17 EEPROM Interface The 78M6631 provides hardware support for an optional 2-pin or a 3-wire (MICROWIRE™) EEPROM interface. 2-Pin EEPROM Interface The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is multiplexed onto the DIO4 (SDCK) and DIO5 (SDATA) pins. 3-Wire (MICROWIRE) EEPROM Interface A 500 kHz three-wire interface, using SDATA, SDCK and a DIO pin for CS, is also available. 1.18 SPI Slave Port The slave SPI port communicates directly with the MPU data bus and is able to directly read and write XRAM and IORAM locations. It is also able to send commands to the MPU. The interface to the slave port consists of the PCSZ, PCLK, PSDI, and PSDO pins. A typical SPI transaction is as follows. While PCSZ is high, the port is held in an initialized/reset state. During this state, PSDO is held in high-Z state and all transitions on PCLK and PSDI are ignored. When PCSZ falls, the port begins the transaction on the first rising edge of PCLK. A transaction consists of an 8-bit command, a 16-bit address, and then one or more bytes of data. The transaction ends when PCSZ is raised. Some transactions can consist of a command only. The last SPI command and address (if part of the command) are available in the IORAM. The SPI port supports data transfers at up to 1 Mbps. The SPI commands are described in Table 1 and Figure 4 illustrates the SPI Interface read and write timing. MICROWIRE is a trademark of National Semiconductor. 12 Rev 1 DS_6631_056 T able 1: SPI Command Description Command 11xx xxxx ADDR D0 ... DN 1100 0000 ADDR D0 ... DN 10xx xxxx ADDR D0 ... DN 1000 0000 ADDR D0 ... DN CMD ADDR D0 ... DN 78M6631 Data Sheet Description Output data on PSDO is read from RAM starting with byte at ADDR. ADDR auto increments until PCSZ is raised. MPU SPI interrupt is generated. Output data on PSDO is read from RAM starting with byte at ADDR. ADDR auto increments until PCSZ is raised. No MPU SPI interrupt is generated. Input data on PSDI is written to RAM starting with byte at ADDR. ADDR auto increments until PCSZ is raised. MPU SPI interrupt is generated. Input data on PSDI is written to RAM starting with byte at ADDR. ADDR auto increments until PCSZ is raised. No MPU SPI interrupt is generated. CMD and ADDR are available to the CPU in IORAM. D0… DN are ignored. MPU SPI interrupt is generated. 16 bit Address DATA[ADDR] DATA[ADDR+1] SERIAL READ PCSZ 0 PSCK (From Host) PSDI (From 6531) PSDO x C7 C6 8 bit CMD Extended Read . . . 7 8 23 24 31 32 39 C5 C0 HI Z A15 A14 A1 A0 x D7 D6 D1 D0 D7 D6 D1 D0 SERIAL WRITE PCSZ PSCK (From Host) PSDI (From 6531) PSDO x 0 8 bit CMD 16 bit Address DATA[ADDR] DATA[ADDR+1] Extended Write . . . 7 8 23 24 31 32 39 C7 C6 C5 C0 A15 A14 A1 A0 HI Z D7 D6 D1 D0 D7 D6 D1 D0 x Figure 4: SPI Slave Port: Typical Read and Write Operations Since the addresses are in 16-bit format, any type of XRAM data can be accessed: CE, MPU, or IORAM but not SFRs or the 80515-internal register bank. 1.19 Test Port One out of 16 digital or eight analog signals can be selected to be output on the TMUXOUT pin. Refer to the 78M6631 Programmer’s Reference Manual f or more information regarding the use of TMUXOUT. 1.20 UART The 78M6631 includes one UART (UART0) that can be programmed to communicate with a variety of external devices. The UART is a dedicated 2-wire serial interfaces (no hardware flow control/handshaking), which can communicate at rates up to 38,400 bps. All UART transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38,400 bps. Refer to the 78M6631 Programmer’s Reference Manual f or more information regarding the use of the UART resources. Rev 1 13 78M6631 Data Sheet DS_6631_056 1.21 In-Circuit Emulator (ICE) Port The 78M6631 implements an In-Circuit Emulator (ICE) port for debug and programming of the device. To enable the use of the port the ICE_E pin must be pulled high. In this mode the E_RST, E_TCLK, and E_RXTX pins are enabled. Contact Maxim support for more information regarding the use of the ICE interface for device programming and debug. 14 Rev 1 DS_6631_056 78M6631 Data Sheet 2 Electrical Specifications 2.1 Absolute Maximum Ratings Table 2 shows the absolute maximum ranges for the device. Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation at these or any other conditions beyond those indicated under recommended operating conditions (Section 2.3) is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GNDA. T able 2: Absolute Maximum Ratings Voltage and Current Supplies and Ground Pins V3P3D, V3P3A GNDD Analog Output Pins VREF Analog Input Pins IAP, IAN, IBP, IBN, ICP, ICN, VA, VB, VC XIN, XOUT All Other Pins Configured as Digital Inputs Configured as Digital Outputs All Other Pins T emperature and ESD Stress Operating Junction Temperature (peak, 100 ms) Operating Junction Temperature (continuous) Storage Temperature Lead Temperature (soldering, 10 s) Soldering Temperature (reflow) ESD Stress on All Pins +140°C +125°C -45°C to +165°C +250°C +260°C ±4 kV -10 mA to +10 mA, -0.5 to +6 V -15 mA to +15 mA, -0.5 V to (V3P3D + 0.5 V) -0.5 V to (V3P3D + 0.5 V) -10 mA to +10 mA -0.5 V to (V3P3A + 0.5 V) -10 mA to +10 mA -0.5 V to 3.0 V -10 mA to +10 mA, -0.5 V to (V3P3A + 0.5 V) -0.5 V to 4.0 V -0.5 V to +0.5 V Rev 1 15 78M6631 Data Sheet DS_6631_056 2.2 Recommended External Components T able 3: Recommended External Components From V3P3A V3P3D XIN XIN XOUT To AGND DGND XOUT AGND AGND Function Bypass capacitor for 3.3 V supply Bypass capacitor for V3P3D 32.768 kHz crystal, electrically similar to ECS .327-12.5-17X or Vishay XT26T, load capacitance 12.5 pF Load capacitor for crystal (depends on crystal specs and board parasitics) Load capacitor for crystal (depends on crystal specs and board parasitics) Value ≥ 0.1 ±20% ≥ 1.0 ±30% 32.768 33 ±10% 15 ±10% Unit µF µF kHz pF pF Name C1 C3 XTAL CXS CXL Notes: 1. AGND and DGND should be connected together. 2. V3P3Ds and V3P3A should be connected together. 2.3 Recommended Operating Conditions T able 4: Recommended Operating Conditions Parameter Condition Normal operation Min 3.0 -40 T yp 3.3 Max 3.6 +85 Unit V ºC V3P3D, V3P3A: 3.3 V Supply Voltage (V3P3A and V3P3D must be at the same voltage) Operating Temperature Range 16 Rev 1 DS_6631_056 78M6631 Data Sheet 2.4 Performance Specifications T able 5: Input Logic Levels 2.4.1 Input Logic Levels Parameter Digital high-level input voltage , VIH Digital low-level input voltage , VIL Input pullup current, IIL E_RXTX, E_RST, CKTEST Other digital inputs Input pulldown current, IIH ICE_E RESET Other digital inputs 1 1 1 Condition Min 2 T yp Max 0.8 Unit V V µA µA µA µA µA µA VIN = 0 V, ICE_E = 1 10 10 -1 10 10 -1 0 100 100 +1 100 100 +1 VIN = V3P3D 0 To reduce power consumption, digital inputs should be below 0.3 V or above 2.5 V to minimize supply current. 2.4.2 Output Logic Levels T able 6: Output Logic Levels Parameter Digital high-level output voltage VOH Condition ILOAD = 1 mA ILOAD = 15 mA Digital low-level output voltage VOL ILOAD = 1 mA ILOAD = 15 mA Min V3P3D 0.4 V3P3D 0.6 0 0.4 0.8 T yp Max Unit V V V V 2.4.3 Power-Fault Comparator T able 7: Power-Fault Comparator Performance Specifications Parameter Offset Voltage: V1 - VBIAS Hysteresis Current: V1 Response Time: V1 VIN = VBIAS – 100 mV +100 mV overdrive Voltage at V1 rising Voltage at V1 falling Condition Min -20 0.8 8 37 Typ Max +15 1.2 100 100 -10 Unit mV µA µs µs mV 10 -400 W DT Disable Threshold: V1 - V3P3A Rev 1 17 78M6631 Data Sheet DS_6631_056 2.4.4 Power Supply Monitor T able 8: Power Supply Monitor Performance Specifications (BME= 1) Parameter Load Resistor LSB Value Offset Error Condition – [M40MHZ, M26MHZ] = [00], [10], or [11] [M40MHZ, M26MHZ] = [01] FIR_LEN=0(L=138) FIR_LEN=1(L=288) FIR_LEN=0(L=186) FIR_LEN=1(L=384) Min 27 (-10%) (-10%) -200 T yp 45 -48.7 -5.35 -19.8 -2.26 0 Max 63 (+10%) (+10%) +100 Unit kΩ µV µV µV µV mV 2.4.5 Supply Current T able 9: Supply Current Performance Specifications Parameter V3P3D current (CE off) V3P3D current (CE on) V3P3A current Condition Normal Operation, V3P3A = V3P3SYS = 3.3 V CKMPU = 614 kHz No flash memory write RTM_E=0, ECK_DIS=1, ADC_E=1, ICE_E=0 Normal operation as above, except write flash at maximum rate, CE_E = 0, ADC_ E = 0 Min T yp 4.2 8.4 3.3 Max 6.35 9.6 3.8 Unit mA mA mA V3P3D current, Write Flash 9.1 12 mA 2.4.6 Crystal Oscillator T able 10: Crystal Oscillator Performance Specifications Parameter Maximum Output Power to Crystal XIN to XOUT Capacitance Capacitance to DGND XIN XOUT 1 1 4 Condition Crystal connected RTCA_ADJ = 0 Min Typ Max 1 3 5 5 Unit µW pF pF pF 18 Rev 1 DS_6631_056 78M6631 Data Sheet 2.4.7 Temperature Sensor Table 11 shows the performance for the temperature sensor. The LSB values do not include the 8-bit left shift at CE input. T able 11: Temperature Sensor Performance Specifications Parameter Nominal Sensitivity (Sn) L S n = −0.00107 ⋅   3 3 Condition [M26MHZ, M40MH] = [00], [01], or [11] [M26MHZ, M40MHZ] = [10] [M26MHZ, M40MH] = [00], [01], or [11] 3 Min T yp -104 -947 -255 49641 451200 121500 Max Unit Nominal relationship: N(T) = Sn*(T-Tn) + Nn, Tn = 22ºC FIR_LEN= 0 (L=138) FIR_LEN=1 (L=288) FIR_LEN=0 (L=186) LSB/ºC Nominal Offset 4 (Nn) L N n = 0.510 ⋅   3 FIR_LEN=0 (L=138) FIR_LEN=1 (L=288) FIR_LEN=0 (L=186) [M26MHZ, M40MHZ] = [10] LSB Temperature Error 2  ( N (T ) − N n )  + Tn  ERR = T −  Sn   1 2 Tn = 22°C, T = -40ºC to +85ºC -101 +101 ºC Guaranteed by design; not production tested. Nn is measured at Tn during measurement calibration and is stored in MPU or CE for use in temperature calculations. 2.4.8 VREF Table 12 shows the performance specifications for VREF. Unless otherwise specified, VREF_DIS = 0. T able 12: VREF Performance Specifications Parameter VREF output voltage, VREF(22) VREF chop step VREF power supply sensitivity ΔVREF/ΔV3P3A VREF input impedance VREF output impedance VNOM definition2 VNOM temperature coefficients: TC1 TC2 VREF(T) deviation from VNOM(T) VREF (T ) − VNOM (T ) 10 6 max( T − 22 ,40) VNOM (T ) Condition TA = +22ºC V3P3A = 3.0 to 3.6 V VREF_DIS = 1, VREF = 1.3 to 1.7 V CAL =1, ILOAD = 10 µA, -10 µA Min 1.193 T yp 1.195 Max 1.197 40 Unit V mV mV/V kΩ -1.5 100 +1.5 2.5 kΩ V µV/ºC µV/°C2 VNOM (T ) = VREF (22) + (T − 22)TC1 + (T − 22) 2 TC 2 3.18·(52.46-TRIMT) -0.444 -401 ±25 +40 1 ppm/ºC ppm/year VREF aging 1 2 Guaranteed by design; not production tested. This relationship describes the nominal behavior of VREF at different temperatures. 19 Rev 1 78M6631 Data Sheet DS_6631_056 2.4.9 ADC Converter, V3P3A Referenced Table 13 shows the performance specifications for the ADC converter, V3P3A referenced. For this data, FIR_LEN = 0, VREF_DIS = 0 and LSB values do not include the 9-bit left shift at the CE input. T able 13: ADC Converter Performance Specifications Parameter Recommended Input Range (VIN - V3P3A) Voltage to Current Crosstalk 10 *Vcrosstalk cos(∠Vin − ∠Vcrosstalk ) Vin 6 Condition Min -250 Typ Max +250 Unit mV peak µV/V VIN = 200 mV peak, 65 Hz, on VA. Vcrosstalk = largest measurement on IA or IB VIN = 65 Hz, 64 kpts FFT, BlackmanHarris window CKCE = 5 MHz VIN = 65 Hz VIN = 65 Hz -101 +101 THD (First 10 harmonics) : 250 mV-pk 20 mV-pk Input Impedance Temperature coefficient of Input Impedance LSB size 1.25  3  VLSB = VREF ⋅ ⋅  4.75  L  L = FIR length 3 1 -75 -901 40 1.7 90 1 dB dB kΩ Ω/°C nV/ LSB nV/ LSB LSB LSB [M40MHZ, M26MHZ] = [00], [10], or [11] [M40MHZ, M26MHZ] = [01] Digital Full Scale [M40MHZ, 3 M26MHZ] =  L  [00], [10], or [11]  3 L = FIR length [M40MHZ, M26MHZ] = [01] ADC Gain Error versus %Power Supply Variation 10 6 ∆Nout PK 357 nV / VIN 100 ∆V 3P3 A / 3.3 VIN = 200 mV pk, 65 Hz, V3P3A=3.0 V, 3.6 V -10 50 +10 ppm/% mV Input Offset (VIN - V3P3A) 1 Guaranteed by design; not production tested. 20 Rev 1 DS_6631_056 78M6631 Data Sheet 2.5 Timing Specifications T able 14: Flash Memory Timing Specifications 2.5.1 Flash Memory Parameter Flash write cycles Flash data retention Flash data retention Flash byte write operations between page or mass erase operations W rite Time per Byte Page Erase (1024 bytes) Mass Erase +25°C +85°C Condition -40°C to +85°C Min 20,000 100 10 2 42 20 200 T yp Max Unit Cycles Years Years Cycles µs ms ms 2.5.2 EEPROM Interface T able 15: EEPROM Interface Timing Parameter W rite Clock frequency (I C) W rite Clock frequency (3-wire) 2 Condition CKMPU = 4.9152 MHz, using interrupts CKMPU = 4.9152 MHz, bit-banging DIO4/5 CKMPU = 4.9152 MHz Min T yp 78 150 500 Max Unit kHz kHz kHz 2.5.3 RESET T able 16: RESET Timing Parameter Reset pulse width Reset pulse fall time 1 Condition Min 5 Typ Max 1 1 Unit µs µs Guaranteed by design; not production tested. Rev 1 21 78M6631 Data Sheet DS_6631_056 2.5.4 SPI Slave Port T able 17: SPI Slave Port Timing Parameter tSPIcycPCLK cycle time tSPILead Enable lead time tSPILag Enable lag time tSPIW PCLK pulse width High Low Ignore if PCLK is low when PCSZ falls Condition Min 1 15 0 40 40 2 0 15 10 5 ns ns ns ns ns T yp Max Unit µs ns ns ns tSPISCK PCSZ to first PCLK fall tSPIDISDisable time tSPIEV PCLK to Data Out tSPISUData input setup time tSPIH Data input hold time PCSZ tSPILead PCLK PSDO PSDI tSPISCK tSPIW MSB OUT tSPIH MSB IN LSB IN Figure 5: SPI Slave Port Timing tSPIcyc tSPIEV tSPIW tSPILag LSB OUT tSPIDIS 22 Rev 1 DS_6631_056 78M6631 Data Sheet 3 Packaging 3.1 3.2 56-Pin QFN Package Pinout E_RST E_TCLK GNDD E_RXTX TMUXOUT TX PCLK V3P3D CKTEST V3P3SYS PSDO PCSZ DIO17 DIO3 56 55 54 53 52 51 50 49 48 47 46 45 44 43 XOUT GNDD XIN V1 VRE F IAP IAN IBP IBN ICP ICN VA VB VC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Teridian 78M 6631 42 41 40 39 38 37 36 35 34 33 32 31 30 29 V3P3A GNDA GNDD RESET VBAT RX DIO11 D/Y DIO9 DIO8 DIO6 DIO5/SDATA DIO4/SDCK ICE_E 15 Rev 1 DIO47 N/C N/C N/C DIO29 PSDI DIO30 DIO45 GNDD DIO25 DIO24 DIO51 DIO53 DIO55 Figure 6: Pinout for QFN-56 Package 16 17 18 19 20 21 22 23 24 25 26 27 28 23 78M6631 Data Sheet DS_6631_056 3.2.1 56-Pin QFN Package Outline 24 Rev 1 DS_6631_056 78M6631 Data Sheet 3.2.2 Recommended PCB Land Pattern for the QFN-56 Package Figure 7: PCB Land Pattern for QFN-56 Package Rev 1 25 78M6631 Data Sheet DS_6631_056 4 Pin Descriptions 4.1 Power and Ground Pins T able 18: Power and Ground Pins Name GNDA GNDD V3P3A V3P3D T ype P P P P Circuit – – – – Description Analog ground: This pin should be connected directly to the ground plane. Digital ground: This pin should be connected directly to the ground plane. Analog power supply: A 3.3 V power supply should be connected to this pin, must be the same voltage as V3P3SYS. System 3.3 V supply. This pin should be connected to a 3.3 V power supply. 4.2 Analog Pins T able 19: Analog Pins T ype I Circuit 6 Description Line Current Sense Inputs: These pins are voltage inputs to the internal A/D converter. Typically, they are connected to the outputs of current sensors. Unused pins must be connected to V3P3A. Name IAP, IAN, IBP, IBN, ICP, ICN VA, VB, VC V1 I 6 Line Voltage Sense Inputs: These pins are voltage inputs to the internal A/D converter. Typically, they are connected to the outputs of resistor dividers. Unused pins must be connected to V3P3A. Comparator Input: This pin is a voltage input to the internal comparator. The voltage applied to the pin is compared to the internal BIAS voltage (1.6 V). If the input voltage is above VBIAS, the comparator output is high (1). If the comparator output is low, a voltage fault occurs. A series 5 kΩ resistor should be connected from V1 to the resistor divider. Voltage Reference for the ADC. Normally disabled and left unconnected. If enabled, a 0.1 µF capacitor to V3P3A should be connected to this pin. Crystal Inputs: A 32 kHz crystal should be connected across these pins. Typically, a 33 pF capacitor is also connected from XIN to GNDA and a 15 pF capacitor is connected from XOUT to GNDA. It is important to minimize the capacitance between these pins. Refer to the crystal manufacturer data sheet for details. If an external clock is used, a 150 mVP-P clock signal should be applied to XIN, and XOUT should be left unconnected. I 7 VREF XIN XOUT O I 9 8 Pin types: P = Power, O = Output, I = Input, I/O = Input/Output The circuit number denotes the equivalent circuit, as specified under Section 5 I/O Equivalent Circuits. 1) 26 Rev 1 DS_6631_056 78M6631 Data Sheet 4.3 Name DIO3 Digital Pins T able 20: Digital Pins Type Circuit I/O I/O 3, 4 Dedicated DIO pin. Description DIO4,DIO5,DIO6 DIO8, DIO9, DIO11 DIO17 DIO24, DIO25 DIO29, DIO30 DIO45, DIO47 DIO51, DIO53 DIO55 D/Y PCLK PSDO PCSZ PSDI E_RXTX E_RST E_TCLK ICE_E CKTEST TMUXOUT RESET 3, 4, 5 Multi-use pins, DIO. (DIO4 = SCK, DIO5 = SDA when configured as EEPROM interface; If unused, these pins must be configured as DIOs and set to outputs by the firmware. I I/O – Selects either the Delta or the Wye configuration. 3, 4, 5 SPI PORT. I/O I/O O I I/O O I 1, 4, 5 Port pins (when ICE_E pulled high). 1, 4, 5 4, 5 2 3, 4 4 2 ICE enable. When zero, E_RST, E_TCLK and E_RXTX SEG32 For production units, this pin should be pulled to GND to disable the emulator port. Test clock. Digital test multiplexer output. Controlled by TMUX[3:0]. Chip reset: This input pin is used to reset the chip into a known state. For normal operation, this pin is pulled low. To reset the chip, this pin should be pulled high. This pin has an internal 30 µA (typ) current source pulldown. No external reset circuitry is necessary. UART input. If this pin is unused, it must be terminated to V3P3D or GNDD. UART output. Enables Production Test. This pin must be grounded in normal operation. RX TX GNDD (pin 55) I O I 3 4 7 Pin types: P = Power, O = Output, I = Input, I/O = Input/Output. The circuit number denotes the equivalent circuit, as specified in Section 5, I/O Equivalent Circuits. Rev 1 27 78M6631 Data Sheet DS_6631_056 5 I/O Equivalent Circuits V3P3D V3P3D 110K CMOS Input GNDD LCD Driver GNDD LCD Output Equivalent Circuit Type 5: LCD SEG or pin configured as LCD SEG V3P3A V3P3D Analog Input Pin GNDA Analog Input Equivalent Circuit Type 6: ADC Input V3P3A LCD SEG Output Pin from internal reference GNDA VREF Equivalent Circuit Type 9: VREF V3P3A Digital Input Pin VREF Pin Digital Input Equivalent Circuit Type 1: Standard Digital Input or pin configured as DIO Input with Internal Pull-Up V3P3D Digital Input Pin GNDD CMOS Input 110K GNDD To MUX from internal reference V2P5 Pin GNDD V2P5 Equivalent Circuit Type 10: V2P5 Digital Input Type 2: Pin configured as DIO Input with Internal Pull-Down V3P3D Comparator Input Pin To Comparator GNDA VLCD Pin GNDD LCD Drivers Digital Input Pin GNDD CMOS Input Comparator Input Equivalent Circuit Type 7: Comparator Input VLCD Equivalent Circuit Type 11: VLCD Power Digital Input Type 3: Standard Digital Input or pin configured as DIO Input V3P3D V3P3D Oscillator Pin GNDD To Oscillator VBAT Pin GNDD Power Down Circuits Oscillator Equivalent Circuit Type 8: Oscillator I/O Digital Output Pin from V3P3SYS 10 VBAT Equivalent Circuit Type 12: VBAT Power CMOS Output GNDD GNDD V3P3D Pin from VBAT 40 Digital Output Equivalent Circuit Type 4: Standard Digital Output or pin configured as DIO Output V3P3D Equivalent Circuit Type 13: V3P3D Figure 8: I/O Equivalent Circuits 28 Rev 1 DS_6631_056 78M6631 Data Sheet 6 Ordering Information Table 21: Ordering Information Part 78M6631 Part Description (Package) 56-pin QFN, Lead(Pb)Free Flash Size 128 KB Packaging Bulk Tape and Reel Order Number 78M6631-IM/F 78M6631-IMR/F Package Marking 78M6631-IM 7 Contact Information For more information about Maxim products or to check the availability of the 78M6631, contact technical support at www.maxim-ic.com/support. Rev 1 29 DS_6631_056 78M6631 Data Sheet Revision History REVISION NUMBER 0 1 REVISION DATE 9/11 1/12 Initial release Removed information about programmed devices from Table 21. Ordering Information DESCRIPTION PAGES CHANGED  29 30 Rev 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r iv e , S u n n y v a le , C A 9 4 0 8 6 4 0 8- 7 3 7 - 7 6 0 0  2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products.