MAX1069AEUD

19-2652; Rev 2; 12/10 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP General Description The MAX1069 is a low-power, 14-bit successiveapproximation analog-to-digital converter (ADC). The device features automatic power-down, an on-chip 4MHz clock, a +4.096V internal reference, and an I2Ccompatible 2-wire serial interface capable of both fast and high-speed modes. The MAX1069 operates from a single supply and consumes 5mW at the maximum conversion rate of 58.6ksps. AutoShutdown™ powers down the device between conversions, reducing supply current to less than 50µA at a 1ksps throughput rate. The option of a separate digital supply voltage allows direct interfacing with +2.7V to +5.5V digital logic. The MAX1069 performs a unipolar conversion on its single analog input using its internal 4MHz clock. The full-scale analog input range is determined by the internal reference or by an externally applied reference voltage ranging from 1V to VAVDD. The four address select inputs (ADD0–ADD3) allow up to 16 MAX1069 devices on the same bus. The MAX1069 is packaged in a 14-pin TSSOP and offers both commercial and extended temperature ranges. Refer to the MAX1169 for a 16-bit device in a pin-compatible package. Features o High-Speed I2C-Compatible Serial Interface 400kHz Fast Mode 1.7MHz High-Speed Mode o +4.75V to +5.25V Single Supply o +2.7V to +5.5V Adjustable Logic Level o Internal +4.096V Reference o External Reference: 1V to VAVDD o Internal 4MHz Conversion Clock o 58.6ksps Sampling Rate o AutoShutdown Between Conversions o Low Power 5.0mW at 58.6ksps 4.2mW at 50ksps 2.0mW at 10ksps 0.23mW at 1ksps 3µW in Shutdown o Small 14-Pin TSSOP Package MAX1069 Applications Hand-Held Portable Applications Medical Instruments Battery-Powered Test Equipment Solar-Powered Remote Systems Receive Signal Strength Indicators System Supervision TOP VIEW DGND 1 SCL SDA 2 3 Ordering Information PART TEMP RANGE PINPACKAGE 14 TSSOP 14 TSSOP INL (LSB) ±1 ±2 MAX1069AEUD+ -40°C to +85°C MAX1069BEUD+ -40°C to +85°C +Denotes a lead(Pb)-free/RoHS-compliant package. Pin Configuration 14 ADD3 13 REF 12 REFADJ AutoShutdown is a trademark of Maxim Integrated Products, Inc. ADD2 4 ADD1 5 ADD0 6 DVDD 7 MAX1069 11 AGNDS 10 AIN 9 8 AGND AVDD TSSOP ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP MAX1069 ABSOLUTE MAXIMUM RATINGS AVDD to AGND.........................................................-0.3V to +6V DVDD to DGND ........................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V AGNDS to AGND...................................................-0.3V to +0.3V AIN, REF, REFADJ to AGND ..................-0.3V to (VAVDD + 0.3V) SCL, SDA, ADD_ to DGND.......................................-0.3V to +6V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +85°C) 14-Pin TSSOP (derate 9.1mW/°C above +85°C) .........864mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VAVDD = +4.75V to +5.25V, VDVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied to REF, REFADJ = AVDD, CREF = 10µF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) D ifferential Nonlinearity Offset Error Offset-Error Temperature Coefficient Gain Error Gain Temperature Coefficient DYNAMIC PERFORMANCE (fIN(sine wave) = 1kHz, VIN = VREF(P-P), fSAMPLE = 5 8.6ksps) Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious-Free Dynamic Range Signal-to-Noise Ratio Full-Power Bandwidth Full-Linear Bandwidth CONVERSION RATE (Figure 11) Conversion Time (SCL Stretched Low) Throughput Rate (Note 4) Internal Clock Frequency Track/Hold Acquisition Time tCONV f SAMPLE fCLK tACQ (Note 5) 1100 Fast mode High-speed mode Fast mode H igh-speed mode 4 7.1 5.8 7.5 6 19 58.6 µs ksps MHz ns SINAD THD SFDR SNR FPBW -3dB point SINAD > 81dB Up to the 5th harmonic 87 82 81 84 -99 102 84 4 20 -86 dB dB dB dB MHz kHz (Note 3) INL DNL MAX1069A MAX1069B M AX1069A, no missing codes MAX1069B, no missing codes 2 1.0 ±0.25 0.1 ±0.5 14 ±1 ±2 ±1 ±1 5 Bits LSB LSB mV ppm/°C %FSR ppm/°C SYMBOL CONDITIONS MIN TYP MAX UNITS 2 _______________________________________________________________________________________ 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +4.75V to +5.25V, VDVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied to REF, REFADJ = AVDD, CREF = 10µF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Aperture Delay (Figure 11c) (Note 6) Aperture Jitter (Figure 11c) ANALOG INPUT (AIN) Input Voltage Range Input Leakage Current Input Capacitance REF Output Voltage Reference Temperature Coefficient Reference Short-Circuit Current REFADJ Output Voltage REFADJ Input Range E XTERNAL REFERENCE (REFADJ = AVDD) REFADJ Buffer Disable Voltage REFADJ Buffer Enable Voltage Reference Input Voltage Range REF Input Current IREF Pull REFADJ high to disable the internal bandgap reference and reference buffer (Note 7) VREF = + 4.096V, VIN = VREF(P-P) f IN(sine wave) = 1 kHz, f SAMPLE = 62.1ksps VREF = + 4.096V, shutdown DIGITAL INPUTS/OUTPUTS (SCL, SDA) Input High Voltage Input Low Voltage Input Hysteresis Input Current Input Capacitance Output Low Voltage Input High Voltage Input Low Voltage Input Hysteresis Input Current Input Capacitance 15 0.1 VIH VIL VHYST I IN CIN VOL I SINK = 3 mA 0.7 VDVDD 0.3 VDVDD ±10 VDVDD 15 0.4 0.1 0.7 VDVDD 0.3 VDVDD ± 10 VDVDD V V V µA pF V V V V µA pF VAVDD - 0.1 VAVDD - 0.4 1.0 27 0.1 VAVDD V V V µA For small adjustments, from 4.096V CIN VREF TCREF IREFSC 4.056 TA = -40°C to +85°C 4.056 VAIN On/off-leakage current, VAIN = 0V or VAVDD, no clock, f SCL = 0Hz 0 ±0.01 35 4.096 ±35 10 4.096 ±60 4.136 4.000 4.136 VREF ±10 V µA pF V ppm/°C mA V mV SYMBOL tAD tAJ Fast mode High-speed mode Fast mode H igh-speed mode CONDITIONS MIN TYP 50 30 100 100 MAX UNITS ns ps MAX1069 INTERNAL REFERENCE (Bypass REFADJ with 0.1µF to AGND and REF with 10µF to AGND) ADDRESS SELECT INPUTS (ADD3, ADD2, ADD1, ADD0) _______________________________________________________________________________________ 3 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP MAX1069 ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +4.75V to +5.25V, VDVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied to REF, REFADJ = AVDD, CREF = 10µF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Analog Supply Voltage D igital Supply Voltage SYMBOL VAVDD VDVDD Internal reference (powered down between conversions, R/W = 0) f SAMPLE = 5 8.6ksps f SAMPLE = 1 0ksps f SAMPLE = 1 ksps Shutdown f SAMPLE = 5 8.6ksps Analog Supply Current IAVDD Internal reference (always on, R/W = 1) f SAMPLE = 1 0ksps f SAMPLE = 1 ksps Shutdown f SAMPLE = 5 8.6ksps External reference (REFADJ = AVDD) f SAMPLE = 5 8.6ksps D igital Supply Current IDVDD f SAMPLE = 1 0ksps f SAMPLE = 1 ksps Shutdown Power-Supply Rejection Ratio Serial Clock Frequency Bus Free Time Between a STOP and a START Condition Hold Time for Start Condition Low Period of the SCL Clock H igh Period of the SCL Clock Setup Time for a Repeated START Condition (Sr) Data Hold Time Data Setup Time R ise Time of Both SDA and SCL Signals, Receiving Fall Time of SDA Transmitting Setup Time for STOP Condition Capacitive Load for Each Bus Pulse Width of Spike Suppressed PSRR f SCL tBUF tHD,STA tLOW tHIGH t SU,STA tHD,DAT t SU,DAT tR tF t SU,STO CB t SP (Note 10) (Note 10) (Note 9) 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 400 50 300 300 900 VAVDD = 5V ±5%, full-scale input (Note 8) TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figure 1a and Figure 2) 400 kHz µs µs µs µs µs ns ns ns ns µs pF ns f SAMPLE = 1 0ksps f SAMPLE = 1 ksps Shutdown CONDITIONS MIN 4.75 2.7 1.8 0.7 40 0.4 1.8 1.4 1.1 0.4 0.90 0.36 40 0.4 260 65 6 0.2 2 5 6 LSB/V 5 400 µA 5 1.8 µA mA µA 5.0 2.5 mA TYP MAX 5.25 5.5 2.5 UNITS V V mA µA POWER REQUIREMENTS (AVDD, AGND, DVDD, DGND) 4 _______________________________________________________________________________________ 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +4.75V to +5.25V, VDVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied to REF, REFADJ = AVDD, CREF = 10µF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Serial Clock Frequency Hold Time, (Repeated) Start Condition Low Period of the SCL Clock H igh Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time R ise Time of SCL Signal (Current Source Enabled) R ise Time of SCL Signal After Acknowledge Bit Fall Time of SCL Signal R ise Time of SDA Signal Fall Time of SDA Signal Setup Time for STOP Condition Capacitive Load for Each Bus Pulse Width of Spike Suppressed SYMBOL f SCLH tHD,STA tLOW tHIGH t SU,STA tHD,DAT t SU,DAT tRCL tRCL1 tFCL tRDA tFDA t SU,STO CB t SP (Note 10) (Note 10) (Note 10) (Note 10) (Note 10) (Note 9) (Note 11) 160 320 120 160 0 10 10 20 20 20 20 160 400 10 80 160 80 160 160 150 CONDITIONS MIN TYP MAX 1.7 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns pF ns MAX1069 TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figure 1b and Figure 2) Note 1: DC accuracy is tested at VAVDD = +5.0V and VDVDD = +3.0V. Performance at power-supply tolerance limits is guaranteed by power-supply rejection test. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offset have been calibrated. Note 3: Offset nullified. Note 4: One sample is achieved every 18 clocks in continuous conversion mode. ⎛ 18 clocks ⎞ fSAMPLE = ⎜ + t CONV ⎟ ⎝ fSCL ⎠ -1 Note 5: The track/hold acquisition time is two SCL cycles as illustrated in Figure 11. ⎛1⎞ t ACQ = 2 × ⎜ ⎟ ⎝ fSCL ⎠ Note 6: A filter on SDA and SCL delays the sampling instant and suppresses noise spikes less than 10ns in high-speed mode and 50ns in fast mode. Note 7: ADC performance is limited by the converter’s noise floor, typically 480µVP-P. Note 8: PSRR = [VFS (5.25V)- VFS (4.75V)] × 5.25V - 4.75V 2N VREF where N is the number of bits (14). _______________________________________________________________________________________ 5 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP MAX1069 ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +4.75V to +5.25V, VDVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied to REF, REFADJ = AVDD, CREF = 10µF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) Note 9: A master device must provide a data hold time for SDA (referred to VIL of SCL) in order to bridge the undefined region of SCL’s falling edge (see Figure 1). Note 10: CB = total capacitance of one bus line in pF. tR and tF measured between 0.3  VDVDD and 0.7  VDVDD. Note 11: fSCL must meet the minimum clock low time plus the rise/fall times. A. F/S-MODE I2C SERIAL INTERFACE TIMING tR tF SDA tSU,DAT tLOW tHD,DAT tSU,STA tHD,STA tSU,STO tBUF SCL tHD,STA S B. HS-MODE I2C SERIAL INTERFACE TIMING tHIGH tR tF Sr A tRDA P S tFDA SDA tSU,DAT tLOW SCL tHD,STA tRCL S HS-MODE PARAMETERS ARE MEASURED FROM 30% TO 70%. tHD,DAT tSU,STA tHD,STA tBUF tSU,STO tHIGH tFCL Sr A tRCL1 P S F/S-MODE Figure 1. I2C Serial Interface Timing VDD IOL = 3mA DIGITAL I/O VOUT 400pF IOH = 0mA Figure 2. Load Circuit 6 _______________________________________________________________________________________ 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP Typical Operating Characteristics (VDVDD = +3.0V, VAVDD = +5.0V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied to REF, REFADJ = AVDD, CREF = 10µF, TA = +25°C, unless otherwise noted.) ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE (INTERNAL REFERENCE) MAX1069 toc01 MAX1069 ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE (EXTERNAL REFERENCE) MAX1069 toc02 ANALOG SHUTDOWN CURRENT vs. ANALOG SUPPLY VOLTAGE VDVDD = 3V fSAMPLE = 0 R/W = 0 MAX1069 toc03 1.75 VDVDD = 3V 1.73 1.71 IAVDD (mA) 830 820 810 IAVDD (µA) 800 790 780 770 760 VDVDD = 3V 700 600 500 IAVDD (nA) 400 300 200 100 0 1.69 1.67 1.65 1.63 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V) TA = +85°C TA = +70°C TA = +25°C TA = 0°C TA = -40°C TA = +85°C TA = +70°C TA = +25°C TA = 0°C TA = -40°C 4.75 4.85 4.95 5.05 5.15 5.25 TA = +85°C TA = +70°C TA = +25°C TA = 0°C TA = -40°C 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V) VAVDD (V) DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE MAX1069 toc04 DIGITAL SHUTDOWN CURRENT vs. DIGITAL SUPPLY VOLTAGE VAVDD = 5V fSAMPLE = 0 R/W = 0 MAX1069 toc05 280 260 240 220 IDVDD (µA) 200 180 160 140 120 100 2.7 3.1 3.5 3.9 4.3 4.7 5.1 TA = -40°C TA = +85°C VAVDD = 5V 350 300 250 IDVDD (nA) TA = -40°C TA = 0°C 200 150 100 50 0 TA = +25°C TA = +70°C TA = +85°C 5.5 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDVDD (V) VDVDD (V) OFFSET ERROR vs. TEMPERATURE MAX1069 toc06 GAIN ERROR vs. TEMPERATURE 0.006 GAIN ERROR (%FSR) 0.004 0.002 0 -0.002 -0.004 -0.006 -0.008 MAX1069 toc07 800 600 OFFSET ERROR (µV) 400 200 0 -200 -400 -600 -800 -40 -15 10 35 60 0.008 85 -40 -15 10 35 60 85 TEMPERATURE (°C) TEMPERATURE (°C) _______________________________________________________________________________________ 7 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP MAX1069 Typical Operating Characteristics (continued) (VDVDD = +3.0V, VAVDD = +5.0V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied to REF, REFADJ = AVDD, CREF = 10µF, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. CONVERSION RATE (HIGH-SPEED MODE, EXTERNAL REFERENCE) 800 SUPPLY CURRENT (µA) 700 600 500 400 300 200 100 0 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 CONVERSION RATE (ksps) CONVERSION RATE (ksps) IDVDD, R/W = 1 OR 0 EXTERNAL REFERENCE, fSCL = 1.7MHz MAX1069 toc09 SUPPLY CURRENT vs. CONVERSION RATE (HIGH-SPEED MODE, INTERNAL REFERENCE) 1800 1600 SUPPLY CURRENT (µA) 1400 1200 1000 800 600 400 200 0 IDVDD, R/W = 1 OR 0 IAVDD, R/W = 0 INTERNAL REFERENCE, fSCL = 1.7MHz IAVDD, R/W = 1 MAX1069 toc08 2000 900 IAVDD, R/W = 1 OR 0 SUPPLY CURRENT vs. CONVERSION RATE (FAST MODE, INTERNAL REFERENCE) MAX1069 toc10 SUPPLY CURRENT vs. CONVERSION RATE (FAST MODE, EXTERNAL REFERENCE) EXTERNAL REFERENCE, fSCL = 400kHz MAX1069 toc11 1800 1600 SUPPLY CURRENT (µA) 1400 1200 1000 800 600 400 200 0 0 INTERNAL REFERENCE, fSCL = 400kHz IAVDD, R/W = 1 600 500 SUPPLY CURRENT (µA) IAVDD, R/W = 1 OR 0 400 300 200 IDVDD, R/W = 1 OR 0 100 0 IAVDD, R/W = 0 IDVDD, R/W = 1 OR 0 5 10 15 20 25 0 5 10 15 20 25 CONVERSION RATE (ksps) CONVERSION RATE (ksps) 8 _______________________________________________________________________________________ 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP Typical Operating Characteristics (continued) (VDVDD = +3.0V, VAVDD = +5.0V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied to REF, REFADJ = AVDD, CREF = 10µF, TA = +25°C, unless otherwise noted.) INTERNAL +4.096V REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE MAX1069 toc12 MAX1069 INTERNAL REFERENCE VOLTAGE vs. REF LOAD fSCL = 0 INTERNAL REFERENCE MODE LOAD APPLIED TO REF MAX1069 toc13 4.100 VDVDD = 3V 4.095 TA = +85°C TA = +70°C TA = +25°C 4.085 TA = 0°C 4.20 4.15 4.10 VREF (V) 4.05 4.00 3.95 VREF (V) 4.090 4.080 TA = -40°C 4.075 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V) 3.90 0 1 2 3 IREF (mA) 4 5 6 EXTERNAL REFERENCE CURRENT vs. EXTERNAL REFERENCE VOLTAGE AIN = AGNDS 30 25 IREF (µA) 20 15 10 5 0 0 1 2 3 VREF (V) 4 5 6 58.6ksps fSCL = 1.7MHz 19ksps fSCL = 400kHz MAX1069 toc14 EXTERNAL REFERENCE CURRENT AND REFERENCE VOLTAGE vs. VREFADJ 30 AIN = AGNDS 20 10 0 -10 VREF -20 -30 3.95 4.00 4.05 4.10 VREFADJ (V) 4.15 4.20 4.25 4.00 3.95 IREFADJ 4.20 4.15 4.10 4.05 VREF (V) MAX1069 toc15 35 4.25 _______________________________________________________________________________________ IREFADJ (µA) 9 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP MAX1069 Typical Operating Characteristics (continued) (VDVDD = +3.0V, VAVDD = +5.0V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied to REF, REFADJ = AVDD, CREF = 10µF, TA = +25°C, unless otherwise noted.) SPURIOUS-FREE DYNAMIC RANGE vs. FREQUENCY MAX1069 toc17 MAX1069 toc16 SIGNAL-TO-NOISE RATIO vs. FREQUENCY 120 110 100 90 80 SFDR (dB) SNR (dB) 70 60 50 40 30 20 10 0 1 10 FREQUENCY (kHz) 100 120 110 100 90 80 70 60 50 40 30 20 10 0 1 DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 MAX1069 toc18 1.0 10 FREQUENCY (kHz) 100 0 4096 8192 12288 16384 DIGITAL OUTPUT CODE TOTAL HARMONIC DISTORTION vs. FREQUENCY MAX1069 toc19 SINAD vs. FREQUENCY MAX1069 toc20 INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE 0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 MAX1069 toc21 0 -10 -20 -30 -40 120 110 100 90 80 SINAD (dB) 70 60 50 40 30 20 10 0 1.0 THD (dB) -50 -60 -70 -80 -90 -100 -110 -120 1 10 FREQUENCY (kHz) 100 1 10 FREQUENCY (kHz) 100 0 4096 8192 12288 16384 DIGITAL OUTPUT CODE FFT fSAMPLE = 58.6ksps fIN(SINE WAVE) = 1kHz VIN = VREF(P-P) MAX1069 toc22 0 -20 MAGNITUDE (dB) -40 -60 -80 -100 -120 -140 0 5.86 11.72 17.56 23.44 29.30 FREQUENCY (kHz) 10 ______________________________________________________________________________________ 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP Pin Description PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NAME DGND SCL SDA ADD2 ADD1 ADD0 DVDD AVDD AGND AIN AGNDS REFADJ REF ADD3 Digital Ground Clock Input Data Input/Output Address Select Input 2 Address Select Input 1 Address Select Input 0 Digital Power Input. Bypass to DGND with a 0.1µF capacitor. Analog Power Input. Bypass to AGND with a 0.1µF capacitor. Analog Ground Analog Input Analog Signal Ground. Negative reference for analog input. Connect to AGND. Internal Reference Output and Reference Buffer Input. Bypass to AGND with a 0.1µF capacitor. Connect REFADJ to AVDD to disable the internal bandgap reference and reference-buffer amplifier. Reference Buffer Output and External Reference Input. Bypass to AGND with a 10µF capacitor when using the internal reference. Address Select Input 3 FUNCTION MAX1069 Detailed Description The MAX1069 analog-to-digital converter (ADC) uses successive-approximation conversion (SAR) techniques and on-chip track-and-hold (T/H) circuitry to capture and convert an analog signal to a serial 14-bit digital output. The MAX1069 performs a unipolar conversion on its single analog input using its internal 4MHz clock. The full-scale analog input range is determined by the internal reference or by an externally applied reference voltage ranging from 1V to VAVDD. The flexible 2-wire serial interface provides easy connection to microcontrollers (µCs) and supports data rates up to 1.7MHz. Figure 3 shows the simplified functional diagram for the MAX1069 and Figure 4 shows the typical application circuit. from +2.7V to +5.5V to ensure compatibility with lowvoltage ASICs. The MAX1069 wakes up in shutdown mode when power is applied irrespective of the VAVDD and VDVDD sequence. Analog Input and Track/Hold The MAX1069 analog input contains a track-and-hold (T/H) capacitor, T/H switches, comparator, and a switched capacitor digital-to-analog converter (DAC) (Figure 5). As shown in Figure 11c, the MAX1069 acquisition period is the two clock cycles prior to the conversion period. The T/H switches are normally in the hold position. During the acquisition period the T/H switches are in the track position and CT/H charges to the analog input signal. Before a conversion begins, the T/H switches move to the hold position retaining the charge on CT/H as a sample of the analog input signal. During the conversion interval, the switched capacitive DAC adjusts to restore the comparator input voltage to zero within the limits of 14-bit resolution. This is equivalent to transferring a charge of 35pF × (VAIN - VAGNDS) from C T/H to the binary-weighted capacitive DAC, Power Supply To maintain a low-noise environment, the MAX1069 provides separate analog and digital power-supply inputs. The analog circuitry requires a +5V supply and consumes only 900µA at sampling rates up to 58.6ksps. The digital supply voltage accepts voltages ______________________________________________________________________________________ 11 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP MAX1069 6 5 4 14 3 2 4MHz INTERNAL OSCILLATOR CLOCK T/H IN SAR ADC OUT REF 5kΩ AV = 1.0 MAX1069 OUTPUT SHIFT REGISTER ADD0 ADD1 ADD2 ADD3 SDA SCL CONTROL LOGIC AVDD AGND 8 9 7 DVDD 1 DGND AIN AGNDS 10 11 +4.096V REFERENCE 12 REFADJ 13 REF Figure 3. MAX1069 Simplified Functional Diagram 5.0V MAX1069 AVDD DVDD ADD0 ADD1 13 ADD2 REF 8 12 0.1µF ANALOG SOURCE 10 11 REFADJ 7 6 5 4 3.0V µC VDD 0.1µF 0.1µF RP RP SDA SCL 10µF SDA 3 2 SCL AIN AGNDS AGND 9 ADD3 DGND 1 I2C ADDRESS IS 0110111 14 VSS Figure 4. Typical Application Circuit forming a digital representation of the analog input signal. During the conversion period, the MAX1069 holds SCL low (clock stretching). The time required for the T/H to acquire an input signal is a function of the analog input source impedance. If the input signal source impedance is high, lengthen the acquisition time by reducing fSCL. The MAX1069 provides two SCL cycles (tACQ), in which the track-andhold capacitance must acquire a charge representing the input signal. Minimize the input source impedance (RSOURCE) to allow the track-and-hold capacitance to charge within the allotted time. RSOURCE should be less than 12.9kΩ for fSCL = 400kHz and less than 2.4kΩ 12 ______________________________________________________________________________________ 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP for fSCL = 1.7MHz. RSOURCE is calculated with the following equation: RSOURCE ≤ 2 − RIN (2 × 2N ) × CIN fSCL × In Internal Clock The MAX1069 contains an internal 4MHz oscillator that drives the SAR conversion clock. During conversion, SCL is held low (clock stretching). An internal register stores data when the conversion is in progress. When the MAX1069 releases SCL, the master reads the conversion results at any clock rate up to 1.7MHz (Figure 11). MAX1069 where RSOURCE is the analog input source impedance, fSCL is the maximum system SCL frequency, N is 14 (the number of bits of resolution), CIN is 35pF (the sum of CT/H and input stray capacitance), and RIN is 800Ω (the T/H switch resistances). To improve the input-signal bandwidth under AC conditions, drive AIN with a wideband buffer (> 4MHz) that can drive the ADC’s input capacitance and settle quickly (see the Input Buffer section). An RC filter at AIN reduces the input track-and-hold switching transient by providing charge for CT/H. Digital Interface The MAX1069 features an I2C-compatible, 2-wire serial interface consisting of a bidirectional serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX1069 and the master at rates up to 1.7MHz. The master (typically a microcontroller) initiates data transfer on the bus and generates SCL. SDA and SCL require pullup resistors (500Ω or greater, Figure 4). Optional resistors (24Ω) in series with SDA and SCL protect the device inputs from high-voltage spikes on the bus lines. Series resistors also minimize crosstalk and undershoot of the bus signals. Analog Input Bandwidth The MAX1069 features input-tracking circuitry with a 4MHz small-signal bandwidth. The 4MHz input bandwidth makes it possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. Use anti-alias filtering to avoid high-frequency signals being aliased into the frequency band of interest. Analog Input Range and Protection Internal ESD (electrostatic discharge) protection diodes clamp AIN, REF, and REFADJ to AV DD and AGNDS/AGND (Figure 6). These diodes allow the analog inputs to swing from (VAGND - 0.3V) to (VAVDD + 0.3V) without causing damage to the device. For accurate conversions, the inputs must not go more than 50mV beyond their rails. If the analog inputs exceed 300mV beyond their rails, limit the current to 2mA. Bit Transfer One data bit is transferred during each SCL clock cycle. Nine clock cycles are required to transfer the data into or out of the MAX1069. The data on SDA must remain stable during the high period of the SCL clock pulse as changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). Both SDA and SCL idle high. START and STOP Conditions The master initiates a transmission with a START condition (S), a high-to-low transition on SDA with SCL high. The master terminates a transmission with a STOP condition (P), a low-to-high transition on SDA while SCL is high (Figure 7). The STOP condition frees the bus and places all devices in F/S mode (see the Bus Timing section). Use a repeated START condition (Sr) in place *RSOURCE HOLD AIN TRACK CT/H REF MAX1069 CAPACITIVE DAC AVDD AIN MAX1069 REF REFADJ AGNDS TRACK ANALOG SIGNAL SOURCE HOLD TRACK AGNDS HOLD *MINIMIZE RSOURCE TO ALLOW THE TRACK-AND-HOLD CAPACITANCE (CT/H) TO CHARGE TO THE ANALOG SIGNAL SOURCE VOLTAGE WITHIN THE ALLOTTED TIME (tACQ). AGND Figure 5. Equivalent Input Circuit Figure 6. Internal Protection Diodes 13 ______________________________________________________________________________________ 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP MAX1069 S SDA Sr P SCL Figure 7. START and STOP Conditions S SDA NOT ACKNOWLEDGE ACKNOWLEDGE SCL 1 2 8 9 Figure 8. Acknowledge Bits of a STOP condition to leave the bus active and in its current timing mode (see the HS-Mode section). Acknowledge Bits Successful data transfers are acknowledged with an acknowledge bit (A) or a not-acknowledge bit (A). Both the master and the MAX1069 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (Figure 8). To generate a not acknowledge, the receiver allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves it high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the master should reattempt communication at a later time. Slave Address A master initiates communication with a slave device by issuing a START condition followed by a slave address byte. As shown in Figure 9, the slave address byte consists of 7 address bits and a read/write bit (R/W). When idle, the MAX1069 continuously waits for a START condition followed by its slave address. When the MAX1069 recognizes its slave address, it acquires the analog input signal and prepares for conversion. The 14 first three bits (MSBs) of the slave address have been factory programmed and are always 011. Connecting ADD3–ADD0 to DVDD or DGND, programs the last four bits (LSBs) of the slave address high or low. Since the MAX1069 does not require setup or configuration, the least significant bit (LSB) of the address byte (R/W) controls power-down. In external reference mode (REFADJ = AVDD), R/W is a don’t care. In internal reference mode, setting R/W = 1 places the device in normal operation and setting R/W = 0 powers down the internal reference following the conversion (see the Internal Reference Shutdown section). After receiving the address, the MAX1069 (slave) issues an acknowledge by pulling SDA low for one clock cycle. Bus Timing At power-up, the MAX1069 bus timing defaults to fast mode (F/S-mode), allowing conversion rates up to 19ksps. The MAX1069 must operate in high-speed mode (HS-mode) to achieve conversion rates up to 58.6ksps. Figure 1 shows the bus timing for the MAX1069 2-wire interface. HS-Mode At power-up, the MAX1069 bus timing is set for F/Smode. The master selects HS-mode by addressing all devices on the bus with the HS-mode master code 0000 1XXX (X = don’t care). After successfully receiving the HS-mode master code, the MAX1069 issues a not acknowledge allowing SDA to be pulled high for one ______________________________________________________________________________________ 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP MAX1069 S SDA 0 1 1 ADD3 ADD2 ADD1 ADD0 R/W ACKNOWLEDGE SCL 1 2 3 4 5 6 7 8 9 A Figure 9. MAX1069 Slave Address Byte S SDA 0 0 0 0 1 X X X A Sr 1 2 3 4 5 6 7 8 9 F/S-MODE HS-MODE Figure 10. F/S-Mode to HS-Mode Transfer clock cycle (Figure 10). After the not acknowledge, the MAX1069 is in HS-mode. The master must then send a repeated START followed by a slave address to initiate HS-mode communication. If the master generates a STOP condition, the MAX1069 returns to F/S-mode. Applications Information Power-On Reset When power is first applied, internal power-on reset circuitry activates the MAX1069 in shutdown. When the internal reference is used, allow 12ms for the reference to settle when CREF = 10µF and CREFADJ = 0.1µF. Data Byte (Read Cycle) Initiate a read cycle to begin a conversion. A read cycle begins with the master issuing a START condition followed by seven address bits and a read bit (R/W). The standard I2C-compatible interface requires that R/ W = 1 to read from a device, however, since the MAX1069 does not require setup or configuration, the read mode is inherent and R/W controls power-down (see the Internal Reference Shutdown section). If the address byte is successfully received, the MAX1069 (slave) issues an acknowledge and begins conversion. As seen in Figure 11, the MAX1069 holds SCL low during conversion. When the conversion is complete, SCL is released and the master can clock data out of the device. The most significant byte of the conversion is available first and contains D13 to D6. The least significant byte contains D5 to D0 plus two trailing sub bits S1 and S0. Data can be continuously converted as long as the master acknowledges the conversion results. Issuing a not acknowledge frees the bus allowing the master to generate a STOP or repeated START. Automatic Shutdown The MAX1069 automatic shutdown reduces the supply current to less than 0.6µA between conversions. The MAX1069 I2C-compatible interface is always active. When the MAX1069 receives a valid slave address the device powers up. The device is then powered down again when the conversion is complete. The automatic shutdown function does not change with internal or external reference. When the internal reference is chosen, the internal reference remains active between conversions unless internal reference shutdown is requested (see the Internal Reference Shutdown section). Internal Reference Shutdown The R/W bit of the slave address controls the MAX1069 internal reference shutdown. In external reference mode (REFADJ = AVDD), R/W is a don’t care. In internal reference mode, setting R/W = 1 places the device in normal operation and setting R/W = 0 prepares the internal reference for shutdown. ______________________________________________________________________________________ 15 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP MAX1069 MASTER TO SLAVE SLAVE TO MASTER A. SINGLE CONVERSION 1 S 7 SLAVE ADDRESS 11 RA CLOCK STRETCH 8 RESULT 1 A 8 RESULT 1 1 NUMBER OF BITS A P OR Sr (MOST SIGNIFICANT BYTE) (LEAST SIGNIFICANT BYTE) tACQ tCONV B. CONTINUOUS CONVERSIONS 1 7 S SLAVE ADDRESS 11 RA CLOCK STRETCH 8 RESULT #1 1 A 8 RESULT #1 1 A CLOCK STRETCH 8 RESULT #2 (MOST SIGNIFICANT BYTE) tCONV 1 A NUMBER OF BITS (MOST SIGNIFICANT BYTE) (LEAST SIGNIFICANT BYTE) tACQ tCONV tACQ 8 RESULT #2 1 A CLOCK STRETCH 8 RESULT #N 1 A 8 RESULT #N 1 1 NUMBER OF BITS A P OR Sr (LEAST SIGNIFICANT BYTE) tACQ C. ACQUISITION DETAIL tCONV (MOST SIGNIFICANT BYTE) (LEAST SIGNIFICANT BYTE) SDA BIT3 BIT2 BIT1 BIT0 A D13 D12 D11 D10 SCL 5 6 7 8 9 CLOCK STRETCH tAJ tAD tCONV 1 2 3 4 tACQ ANALOG INPUT TRACK AND HOLD HOLD TRACK HOLD Figure 11. Read Cycle If the internal reference is used and R/W = 0, shutdown occurs when the master issues a not-acknowledge bit while reading the conversion results. The internal reference and internal reference buffer are disabled during shutdown, reducing the analog supply current to less than 1µA. A dummy conversion is required to power up the internal reference. The MAX1069 internal reference begins powering up from shutdown on the 9th falling edge of a 16 valid address byte. Allow 12ms for the internal reference to settle before obtaining valid conversion results. Reference Voltage The MAX1069 provides an internal or accepts an external reference voltage. The ADC input range is from VAGNDS to VREF (see the Transfer Function section). ______________________________________________________________________________________ 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP Internal Reference The MAX1069 contains an internal 4.096V bandgap reference. This bandgap reference is connected to REFADJ through a 5kΩ resistor. Bypass REFADJ with a 0.1µF capacitor to AGND. The MAX1069 reference buffer has a unity gain to provide +4.096V at REF. Bypass REF with a 10µF capacitor to AGND when the internal reference is used (Figure 12). The internal reference is adjustable to ±1.5% using the Figure 13 circuit. 4.096V SAR REF ADC AV = 1.0 REFADJ 12 MAX1069 5kΩ 4.096V BANDGAP REFERENCE DGND 1 AGND 9 0.1µF REF 13 10µF MAX1069 External Reference For external reference operation, disable the internal reference by connecting REFADJ to AVDD. During conversion, an external reference at REF must deliver up to 100µA of DC load current and have an output impedance of less than 10Ω. For optimal performance, buffer the reference through an op amp and bypass REF with a 10µF capacitor. Consider the MAX1069’s equivalent input noise (80µVRMS) when choosing a reference. Figure 12. Internal Reference Transfer Function The MAX1069 has a standard unipolar transfer function with a valid analog input voltage range from VAGNDS to V REF . Output data coding is binary with 1LSB = (VREF/2N) where ‘N’ is the number of bits (14). Code transitions occur halfway between successive-integer LSB values. Figure 14 shows the MAX1069 input/output (I/O) transfer function. Input Buffer Most applications require an input buffer amplifier to achieve 14-bit accuracy. If the input signal is multiplexed, the input channel should be switched immediately after acquisition, rather than near the end of or 5.0V AVDD MAX1069 8 0.1µF 4.096V SAR REF ADC AV = 1.0 REF 13 10µF REFADJ 12 5kΩ 4.096V BANDGAP REFERENCE DGND 1 AGND 9 68kΩ 0.1µF 100kΩ POTENTIOMETER 150kΩ Figure 13. Adjusting the Internal Reference ______________________________________________________________________________________ 17 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP VREF 1...111 1...110 1...101 1...100 V 1LSB = REF 16384 0...011 0...010 0...001 0...000 grounds to the star analog ground. Connect the digital grounds to the star digital ground. Connect the digital ground plane to the analog ground plane at one point. For lowest-noise operation, make the ground return to the star ground’s power-supply low impedance and make it as short as possible. High-frequency noise in the AVDD power supply degrades the ADC’s high-speed comparator performance. Bypass AVDD to AGND with a 0.1µF ceramic surface-mount capacitor. Make bypass capacitor connections as short as possible. If the power supply is very noisy, connect a 10Ω resistor in series with AVDD and a 4.7µF capacitor from AVDD to AGND to create a lowpass RC filter. MAX1069 BINARY OUTPUT CODE (LSB) VREF 0123 INPUT VOLTAGE (LSB) 16381 16383 Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function once offset and gain errors have been nullified. The MAX1069 INL is measured using the endpoint method. AGNDS Figure 14. Unipolar Transfer Function after a conversion. This allows more time for the input buffer amplifier to respond to a large step-change in input signal. The input amplifier must have a high enough slew rate to complete the required output voltage change before the beginning of the acquisition time. At the beginning of acquisition, the internal sampling capacitor array connects to AIN (the amplifier output), causing some output disturbance. Ensure that the sampled voltage has settled to within the required limits before the end of the acquisition time. If the frequency of interest is low, AIN can be bypassed with a large enough capacitor to charge the internal sampling capacitor with very little ripple. However, for AC use, AIN must be driven by a wideband buffer (at least 4MHz), which must be stable with the ADC’s capacitive load (in parallel with any AIN bypass capacitor used) and also settle quickly. Refer to Maxim’s website at www.maxim-ic.com for application notes on how to choose the optimum buffer amplifier for your ADC application. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples (Figure 11). Aperture Delay Aperture delay (tAD) is the time from the falling edge of SCL to the instant when an actual sample is taken (Figure 11). Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analogto-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR = ((6.02  N) + 1.76)dB In reality, noise sources besides quantization noise exist, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Layout, Grounding, and Bypassing Careful printed circuit (PC) layout is essential for the best system performance. Boards should have separate analog and digital ground planes and ensure that digital and analog signals are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the device package. Figure 4 shows the recommended system ground connections. Establish an analog ground point at AGND and a digital ground point at DGND. Connect all analog 18 ______________________________________________________________________________________ 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to RMS equivalent of all other ADC output signals. ⎛ SignalRMS ⎞ SINAD(db) = 20 × log ⎜ ⎟ ⎝ NoiseRMS ⎠ Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component. MAX1069 Chip Information PROCESS: BiCMOS Effective Number of Bits Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the ADC’s full-scale range, calculate the ENOB as follows: ⎛ SINAD - 1.76 ⎞ ENOB = ⎜ ⎟ ⎝ ⎠ 6.02 Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 14 TSSOP PACKAGE CODE U14+1 OUTLINE NO. 21-0066 LAND PATTERN NO. 90-0113 Total Harmonic Distortion Total harmonic distortion (THD) is the RMS sum ratio of the input signal’s first five harmonics to the fundamental itself, expressed as: ⎛ V22 + V32 + V4 2 + V52 THD = 20 × log ⎜ ⎜ V1 ⎝ ⎞ ⎟ ⎟ ⎠ where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. ______________________________________________________________________________________ 19 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP MAX1069 Revision History REVISION NUMBER 0 1 2 REVISION DATE 10/02 11/09 12/10 Initial release Remove the grade C devices from the Ordering Information a nd Electrical Characteristics tables Add lead-free, remove 0 to +70 temp range parts, update pin names for AVDD and DVDD, style edits DESCRIPTION PAGES CHANGED — 1, 2 1–15, 17–20 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.