MAX108CHC

19-1492; Rev 0; 9/99 KIT ATION EVALU BLE AVAILA ±5V, 1.5Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier General Description Features o 1.5Gsps Conversion Rate o 2.2GHz Full-Power Analog Input Bandwidth o 7.5 Effective Bits at fIN = 750MHz (Nyquist Frequency) o ±0.25LSB INL and DNL o 50Ω Differential Analog Inputs o ±250mV Input Signal Range o On-Chip, +2.5V Precision Bandgap Voltage Reference o Latched, Differential PECL Digital Outputs o Selectable 8:16 Demultiplexer o Internal Demux Reset Input with Reset Output o 192-Contact ESBGA Package o Pin Compatible with MAX104 (1Gsps) and MAX106 (600Msps) MAX108 The MAX108 PECL-compatible, 1.5Gsps, 8-bit analogto-digital converter (ADC) allows accurate digitizing of analog signals with bandwidths to 2.2GHz. Fabricated on Maxim’s proprietary advanced GST-2 bipolar process, the MAX108 integrates a high-performance track/hold (T/H) amplifier and a quantizer on a single monolithic die. The innovative design of the internal T/H, which has an exceptionally wide 2.2GHz full-power input bandwidth, results in high performance (typically 7.5 effective bits) at the Nyquist frequency. A fully differential comparator design and decoding circuitry reduce out-of-sequence code errors (thermometer bubbles or sparkle codes) and provide excellent metastable performance. Unlike other ADCs that can have errors resulting in false fullor zero-scale outputs, the MAX108 limits the error magnitude to 1LSB. The analog input is designed for either differential or single-ended use with a ±250mV input voltage range. Dual, differential, positive-referenced emitter-coupled logic (PECL)-compatible output data paths ensure easy interfacing and include an 8:16 demultiplexer feature that reduces output data rates to one-half the sampling clock rate. The PECL outputs can be operated from any supply between +3V to +5V for compatibility with +3.3V or +5V referenced systems. Control inputs are provided for interleaving additional MAX108 devices to increase the effective system sampling rate. The MAX108 is packaged in a 25mm x 25mm, 192-contact Enhanced Super Ball-Grid Array (ESBGA™) and is specified over the commercial (0°C to +70°C) temperature range. For pin-compatible, lower speed versions of the MAX108, see the MAX104 (1Gsps) and the MAX106 (600Msps) data sheets. Ordering Information PART MAX108CHC TEMP. RANGE 0°C to +70°C PIN-PACKAGE 192 ESBGA 192-Contact ESBGA Ball Assignment Matrix TOP VIEW Applications Digital RF/IF Signal Processing Direct RF Downconversion High-Speed Data Acquisition Digital Oscilloscopes High-Energy Physics Radar/ECM Systems ATE Systems Typical Operating Circuit appears at end of data sheet. ESBGA PCB land pattern appears at end of data sheet. 1 MAX108 ESBGA is a trademark of Amkor/Anam. ________________________________________________________________ Maxim Integrated Products For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. ±5V, 1.5Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier MAX108 ABSOLUTE MAXIMUM RATINGS VCCA to GNDA .........................................................-0.3V to +6V VCCD to GNDD.........................................................-0.3V to +6V VCCI to GNDI ............................................................-0.3V to +6V VCCO to GNDD ........................................-0.3V to (VCCD + 0.3V) AUXEN1, AUXEN2 to GND .....................-0.3V to (VCCD + 0.3V) VEE to GNDI..............................................................-6V to +0.3V Between GNDs......................................................-0.3V to +0.3V VCCA to VCCD .......................................................-0.3V to +0.3V VCCA to VCCI.........................................................-0.3V to +0.3V PECL Digital Output Current ...............................................50mA REFIN to GNDR ........................................-0.3V to (VCCI + 0.3V) REFOUT Current ................................................+100µA to -5mA ICONST, IPTAT to GNDI .......................................-0.3V to +1.0V TTL/CMOS Control Inputs (DEMUXEN, DIVSELECT) ......................-0.3V to (VCCD + 0.3V) RSTIN+, RSTIN- ......................................-0.3V to (VCCO + 0.3V) VOSADJ Adjust Input ................................-0.3V to (VCCI + 0.3V) CLK+ to CLK- Voltage Difference..........................................±3V CLK+, CLK-.....................................(VEE - 0.3V) to (GNDD + 1V) CLKCOM.........................................(VEE - 0.3V) to (GNDD + 1V) VIN+ to VIN- Voltage Difference ............................................±2V VIN+, VIN- to GNDI................................................................±2V Continuous Power Dissipation (TA = +70°C) 192-Contact ESBGA (derate 61mW/°C above +70°C) ....4.88W (with heatsink and 200 LFM airflow, derate 106mW/°C above +70°C) .....................................8.48W Operating Temperature Range MAX108CHC.........................................................0°C to +70°C Operating Junction Temperature.....................................+150°C Storage Temperature Range .............................-65°C to +150°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCCA = VCCI = VCCD = +5.0V ±5%, VEE = -5.0V ±5%, VCCO = +3.0V to VCCD, REFIN connected to REFOUT, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER ACCURACY Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity (Note 1) Missing Codes ANALOG INPUTS Full-Scale Input Range Common-Mode Input Range Input Resistance Input Resistance Temperature Coefficient VOS ADJUST CONTROL INPUT Input Resistance (Note 2) Input VOS Adjust Range REFERENCE INPUT AND OUTPUT Reference Output Voltage Reference Output Load Regulation Reference Input Resistance REFOUT Driving REFIN input only 2.475 2.50 2.525 5 4 5 V mV kΩ RVOS VOSADJ = 0 to 2.5V 14 ±4 25 ±5.5 kΩ LSB VFSR VCM RIN TCR Note 1 Signal + offset w.r.t. GNDI VIN+ and VIN- to GNDI, TA = +25°C 49 475 500 ±0.8 50 150 51 525 mVp-p V Ω ppm/°C RES INL DNL TA = +25°C TA = +25°C No missing codes guaranteed 8 -0.5 -0.5 ±0.25 ±0.25 0.5 0.5 None Bits LSB LSB Codes SYMBOL CONDITIONS MIN TYP MAX UNITS ∆REFOUT 0 < ISOURCE < 2.5mA RREF Referenced to GNDR 2 _______________________________________________________________________________________ ±5V, 1.5Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier DC ELECTRICAL CHARACTERISTICS (continued) (VCCA = VCCI = VCCD = +5.0V ±5%, VEE = -5.0V ±5%, VCCO = +3.0V to VCCD, REFIN connected to REFOUT, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER CLOCK INPUTS (Note 3) Clock Input Resistance Input Resistance Temperature Coefficient High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current DEMUX RESET INPUT (Note 4) Digital Input High Voltage Digital Input Low Voltage PECL DIGITAL OUTPUTS (Note 5) Digital Output High Voltage Digital Output Low Voltage POWER REQUIREMENTS Positive Analog Supply Current Positive Input Supply Current Negative Input Supply Current Digital Supply Current Output Supply Current (Note 6) Power Dissipation (Note 6) Common-Mode Rejection Ratio (Note 7) Positive Power-Supply Rejection Ratio (Note 8) Negative Power-Supply Rejection Ratio (Note 8) ICCA ICCI IEE ICCD ICCO PDISS CMRR PSRR+ PSRRVIN+ = VIN- = ±0.1V (Note 9) (Note 10) 40 40 40 -290 480 108 -210 205 75 5.25 68 73 68 340 115 780 150 mA mA mA mA mA W dB dB dB VOH VOL -1.025 -1.810 -0.880 -1.620 V V VIH VIL -1.165 -1.475 V V RCLK TCR CLK+ and CLK- to CLKCOM, TA = +25°C 48 50 150 52 Ω ppm/°C SYMBOL CONDITIONS MIN TYP MAX UNITS MAX108 TTL/CMOS CONTROL INPUTS (DEMUXEN, DIVSELECT) VIH VIL IIH IIL VIH = 2.4V VIL = 0 -1 2.0 0.8 50 1 V V µA µA _______________________________________________________________________________________ 3 ±5V, 1.5Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier MAX108 AC ELECTRICAL CHARACTERISTICS (VCCA = VCCI = VCCD = +5.0V, VEE = -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS = 1.5Gsps, fIN at -1dBFS, TA = +25°C, unless otherwise noted.) PARAMETER ANALOG INPUT Analog Input Full-Power Bandwidth Analog Input VSWR Transfer Curve Offset DYNAMIC SPECIFICATIONS ENOB1500 Effective Number of Bits (Note 11) ENOB750 ENOB250 SNR1500 Signal-to-Noise Ratio (No Harmonics) SNR750 SNR250 THD1500 Total Harmonic Distortion (Note 12) THD750 THD250 SFDR1500 Spurious-Free Dynamic Range SFDR750 SFDR250 SINAD1500 Signal-to-Noise Ratio and Distortion (Note 11) SINAD750 SINAD250 Two-Tone Intermodulation IMD fIN = 1500MHz fIN = 750MHz fIN = 250MHz fIN = 1500MHz fIN = 750MHz fIN = 250MHz fIN = 1500MHz fIN = 750MHz fIN = 250MHz fIN = 1500MHz fIN = 750MHz fIN = 250MHz fIN = 1500MHz fIN = 750MHz fIN = 250MHz Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended 45.7 44.5 55.0 50.0 -55.5 -49.0 44.2 43.3 7.3 7.1 7.07 7.07 7.51 7.53 7.71 7.71 44.8 44.9 46.8 46.9 47.4 47.4 -44.5 -44.2 -52.1 -52.8 -60.2 -61.3 44.6 45.5 54.0 54.1 61.6 61.7 44.3 44.4 47.0 47.1 48.2 48.2 -66.8 dB dB dB dB dB Bits BW-3dB VSWR VOS fIN = 500MHz VOSADJ control input open -2.0 2.2 1.1:1 0 +2.0 GHz V/V LSB SYMBOL CONDITIONS MIN TYP MAX UNITS fIN1 = 247MHz, fIN2 = 253MHz, at -7dB below full-scale 4 _______________________________________________________________________________________ ±5V, 1.5Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier AC ELECTRICAL CHARACTERISTICS (continued) (VCCA = VCCI = VCCD = +5.0V, VEE = -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS = 1.5Gsps, fIN at -1dBFS, TA = +25°C, unless otherwise noted.) PARAMETER TIMING CHARACTERISTICS Maximum Sample Rate Clock Pulse Width Low Clock Pulse Width High Aperture Delay Aperture Jitter Reset Input Data Setup Time (Note 13) Reset Input Data Hold Time (Note 13) CLK to DREADY Propagation Delay DREADY to DATA Propagation Delay (Note 14) DATA Rise Time DATA Fall Time DREADY Rise Time DREADY Fall Time Primary Port Pipeline Delay Auxiliary Port Pipeline Delay Note 1: fMAX tPWL tPWH tAD tAJ tSU tHD tPD1 tPD2 tRDATA tFDATA tRDREADY tFDREADY tPDP tPDA Figure 17 Figure 17 Figure 4 Figure 4 Figure 15 Figure 15 Figure 17 Figure 17 20% to 80%, CL = 3pF 20% to 80%, CL = 3pF 20% to 80%, CL = 3pF 20% to 80%, CL = 3pF Figures 6, 7, 8 Figures 6, 7, 8 DIV1, DIV2 modes DIV4 mode DIV1, DIV2 modes DIV4 mode -50 0 0 2.2 150 420 360 220 180 7.5 7.5 8.5 9.5 350 1.5 0.3 0.3 100