MAX109EHF-D

19-0795; Rev 0; 4/07 KIT ATION EVALU BLE AVAILA 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs General Description The MAX109, 2.2Gsps, 8-bit, analog-to-digital converter (ADC) enables the accurate digitizing of analog signals with frequencies up to 2.5GHz. Fabricated on an advanced SiGe process, the MAX109 integrates a highperformance track/hold (T/H) amplifier, a quantizer, and a 1:4 demultiplexer on a single monolithic die. The MAX109 also features adjustable offset, full-scale voltage (via REFIN), and sampling instance allowing multiple ADCs to be interleaved in time. The innovative design of the internal T/H amplifier, which has a wide 2.8GHz full-power bandwidth, enables a flat-frequency response through the second Nyquist region. This results in excellent ENOB performance of 6.9 bits. A fully differential comparator design and decoding circuitry reduce out-of-sequence code errors (thermometer bubbles or sparkle codes) and provide excellent metastability performance (1014 clock cycles). This design guarantees no missing codes. The analog input is designed for both differential and single-ended use with a 500mVP-P input-voltage range. The output data is in standard LVDS format, and is demultiplexed by an internal 1:4 demultiplexer. The LVDS outputs operate from a supply-voltage range of 3V to 3.6V for compatibility with single 3V-reference systems. Control inputs are provided for interleaving additional MAX109 devices to increase the effective system-sampling rate. The MAX109 is offered in a 256-pin Super Ball-Grid Array (SBGA) package and is specified over the extended industrial temperature range (-40°C to +85°C). Features ♦ Ultra-High-Speed, 8-Bit, 2.2Gsps ADC ♦ 2.8GHz Full-Power Analog Input Bandwidth ♦ Excellent Signal-to-Noise Performance 44.6dB SNR at fIN = 300MHz 44dB SNR at fIN = 1600MHz ♦ Superior Dynamic Range at High-IF 61.7dBc SFDR at fIN = 300MHz 50.3dBc SFDR at fIN = 1600MHz -60dBc IM3 at fIN1 = 1590MHz and fIN2 = 1610MHz ♦ 500mVP-P Differential Analog Inputs ♦ 6.8W Typical Power Including the Demultiplexer ♦ Adjustable Range for Offset, Full-Scale, and Sampling Instance ♦ 50Ω Differential Analog Inputs ♦ 1:4 Demultiplexed LVDS Outputs ♦ Interfaces Directly to Common FPGAs with DDR and QDR Modes MAX109 Ordering Information PART MAX109EHF-D TEMP RANGE -40°C to +85°C PINPACKAGE 256 SBGA PKG CODE H256-1 D = Dry pack. Applications Radar Warning Receivers (RWR) Light Detection and Ranging (LIDAR) Digital RF/IF Signal Processing Electronic Warfare (EW) Systems High-Speed Data-Acquisition Systems Digital Oscilloscopes High-Energy Physics Instrumentation ATE Systems TOP VIEW 1 A B C D E F G H J K L M N P R T U V W Y 2 3 4 5 6 7 8 Pin Configuration 9 10 11 12 13 14 15 16 17 18 19 20 MAX109 256-PIN SBGA PACKAGE 256-PIN SUPER BALL-GRID ARRAY ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs MAX109 A[0:7] B[0:7] C[0:7] D[0:7] DOR DCO RSTOUT DEMUX RESET OUTPUT DEMUX CLOCK DRIVER PORTC PORTD PORTA PORTB DCO DOR QDR DEMUX CLOCK GENERATOR DDR DELAYED RESET LOGIC CLOCK DRIVER REFERENCE AMPLIFIER 8-BIT ADC CORE RESET PIPELINE REFIN QUANTIZER CLOCK DRIVER RESET INPUT DUAL LATCH T/H AMPLIFIER INPUT CLOCK BUFFER REFOUT BANDGAP REFERENCE RSTINN RSTINP GNDI 50Ω 50Ω 50Ω 50Ω TEMPERATURE MONITOR TEMPMON VOSADJ INP INN SAMPADJ CLKP CLKCOM CLKN Figure 1. Functional Diagram of the MAX109 2 _______________________________________________________________________________________ 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs ABSOLUTE MAXIMUM RATINGS VCCA to GNDA ....................................................... -0.3V to +6V VCCD to GNDD ....................................................... -0.3V to +6V VCCI to GNDI ........................................................... -0.3V to +6V VCCO to GNDO ................................................... -0.3V to +3.9V VEE to GNDI ............................................................ -6V to +0.3V Between Grounds (GNDA, GNDI, GNDO, GNDD, GNDR) ................................................ -0.3V to +0.3V VCCA to VCCD ..................................................... -0.3V to +0.3V VCCA to VCCI ....................................................... -0.3V to +0.3V Differential Voltage between INP and INN ........................... ±1V INP, INN to GNDI ................................................................. ±1V Differential Voltage between CLKP and CLKN..................... ±3V CLKP, CLKN, CLKCOM to GNDI ............................... -3V to +1V Digital LVDS Outputs to GNDO .............. -0.3V to (VCCO - 0.3V) REFIN, REFOUT to GNDR ........................-0.3V to (VCCI + 0.3V) REFOUT Current ...............................................-100µA to +5mA RSTINP, RSTINN to GNDA .....................-0.3V to (VCCO + 0.3V) RSTOUTP, RSTOUTN to GNDO .............-0.3V to (VCCO + 0.3V) VOSADJ, SAMPADJ, TEMPMON to GNDI...............................-0.3V to (VCCI + 0.3V) PRN, DDR, QDR to GNDD.......................-0.3V to (VCCD + 0.3V) DELGATE0, DELGATE1 to GNDA ...........-0.3V to (VCCA + 0.3V) Continuous Power Dissipation (TA = +70°C) 256-Ball SBGA (derate 74.1mW/°C above +70°C for a multilayer board) ................................................. 5925.9mW Operating Temperature Range MAX109EHF ...................................................-40°C to +85°C Thermal Resistance θJA (Note 1) .......................................3°C/W Operating Junction Temperature.....................................+150°C Storage Temperature Range .............................-65°C to +150°C MAX109 Note 1: Thermal resistance is based on a 5in x 5in multilayer board. The data sheet assumes a thermal environment of 3°C/W. Thermal resistance may be different depending on airflow and heatsink cooling capabilities. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDO = GNDD = GNDR = 0V, VOSADJ = SAMPADJ = open, digital output pins differential RL = 100Ω. Specifications ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER DC ACCURACY Resolution Integral Nonlinearity (Note 2) Differential Nonlinearity (Note 2) Transfer Curve Offset (Note 2) ANALOG INPUTS (INN, INP) Common-Mode Input-Voltage Range Common-Mode Rejection Ratio (Note 3) Full-Scale Input Range (Note 2) Input Resistance Input Resistance Temperature Coefficient Input Resistance (Note 4) Input Offset Voltage VCM CMRR VFS RIN TCR VREFIN = 2.5V 470 45 Signal and offset with respect to GNDI ±1 50 500 50 150 535 55 V dB mVP-P Ω ppm/°C RES INL DNL VOS (Note 8) Guaranteed no missing codes, TA = +25°C (Note 8) VOSADJ control input open (Note 8) 8 -0.8 -0.8 -5.5 ±0.25 ±0.25 0 +0.8 +0.8 +5.5 Bits LSB LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS VOS ADJUST CONTROL INPUT (VOSADJ) RVOSADJ VOS VOSADJ = 0V VOSADJ = 2.5V 25 SAMPADJ = 0 to 2.5V 25 50 -20 20 50 30 75 75 kΩ mV mV kΩ ps SAMPLE ADJUST CONTROL INPUT (SAMPADJ) Input Resistance Aperture Time Adjust Range RSAMPADJ tAD _______________________________________________________________________________________ 3 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs MAX109 DC ELECTRICAL CHARACTERISTICS (continued) (VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDO = GNDD = GNDR = 0V, VOSADJ = SAMPADJ = open, digital output pins differential RL = 100Ω. Specifications ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN 2.460 TYP 2.500 < 7.5 2.500 ±0.25 4 5 200 to 2000 -2 to +2 45 50 150 55 MAX 2.525 UNITS V mV V kΩ REFERENCE INPUT AND OUTPUT (REFIN, REFOUT) Reference Output Voltage REFOUT Reference Output Load Regulation Reference Input Voltage Reference Input Resistance CLOCK INPUTS (CLKP, CLKN) Clock Input Amplitude Clock Input Common-Mode Range Clock Input Resistance Input Resistance Temperature Coefficient High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current LVDS INPUTS (RSTINP, RSTINN) Differential Input High Voltage Differential Input Low Voltage Minimum Common-Mode Input Voltage Maximum Common-Mode Input Voltage TEMPERATURE MEASUREMENT OUTPUT (TEMPMON) Temperature Measurement Accuracy Output Resistance Differential Output Voltage Output Offset Voltage VOD VOS T (°C) = [(VTEMPMON - VGNDI) x 1303.5] 371 Measured between TEMPMON and GNDI RLOAD = 100Ω RLOAD = 100Ω 250 1.10 ±7 0.725 400 1.28 °C kΩ mV V 1 VCCO 0.15 0.2 -0.2 V V V V RCLK TCR Peak-to-peak differential (Figure 13b) Signal and offset referenced to CLKCOM CLKP and CLKN to CLKCOM mV V Ω ppm/°C ∆REFOUT REFIN RREFIN 0 < ISOURCE < 2.5mA CMOS CONTROL INPUTS (DDR, QDR, PRN, DELGATE0, DELGATE1) VIH VIL IIH IIL Threshold voltage = 1.2V Threshold voltage = 1.2V VIH = 3.3V VIL = 0V -50 1.4 3.3 0.8 50 V V µA µA LVDS OUTPUTS (PortA, PortB, PortC, PortD, DORP, DORN, DCOP, DCON, RSTOUTP, RSTOUTN) (Note 9) 4 _______________________________________________________________________________________ 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs DC ELECTRICAL CHARACTERISTICS (continued) (VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDO = GNDD = GNDR = 0V, VOSADJ = SAMPADJ = open, digital output pins differential RL = 100Ω. Specifications ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER POWER REQUIREMENTS Analog Supply Current Positive Input Supply Current Negative Input Supply Current Digital Supply Current Output Supply Current Power Dissipation Positive Power-Supply Rejection Ratio Negative Power-Supply Rejection Ratio IVCCA IVCCI 556 125 181 291 222 6.50 (Note 5) VEE = -5.25V to -4.75V 50 50 744 168 240 408 300 8.79 mA mA mA mA mA W dB dB SYMBOL CONDITIONS MIN TYP MAX UNITS MAX109 IIVEEI IVCCD IVCCO PDISS PSRRP PSRRN AC ELECTRICAL CHARACTERISTICS (VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.2Gsps, analog input amplitude at -1dBFS differential, clock input amplitude 400mVP-P differential, digital output pins differential RL = 100Ω. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER ANALOG INPUT Analog Input Full-Power Bandwidth (Note 6) Gain Flatness DYNAMIC SPECIFICATIONS SNR300 SNR1000 Signal-to-Noise Ratio SNR1600 SNR2500 SNR500 SNR1600 THD300 THD1000 Total Harmonic Distortion (Note 7) THD1600 THD2500 THD500 THD1600 fIN = 300MHz, fCLK = 2.2Gsps fIN = 1000MHz, fCLK = 2.2Gsps (Note 8) fIN = 1600MHz, fCLK = 2.2Gsps (Note 8) fIN = 2500MHz, fCLK = 2.2Gsps fIN = 500MHz, fCLK = 2.5Gsps fIN = 1600MHz, fCLK = 2.5Gsps fIN = 300MHz, fCLK = 2.2Gsps fIN = 1000MHz, fCLK = 2.2Gsps (Note 8) fIN = 1600MHz, fCLK = 2.2Gsps (Note 8) fIN = 2500MHz, fCLK = 2.2Gsps fIN = 500MHz, fCLK = 2.5Gsps fIN = 1600MHz, fCLK = 2.5Gsps 43.6 42.2 44.6 44.5 44.0 42.9 44.4 44.0 -55.6 -48.5 -46.6 -43.7 -49.0 -43.1 -42.5 -39.6 dBc dB BW-3dB GF 1100MHz to 2200MHz 2.8 ±0.3 GHz dB SYMBOL CONDITIONS MIN TYP MAX UNITS _______________________________________________________________________________________ 5 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs MAX109 AC ELECTRICAL CHARACTERISTICS (continued) (VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.2Gsps, analog input amplitude at -1dBFS differential, clock input amplitude 400mVP-P differential, digital output pins differential RL = 100Ω. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL SFDR300 SFDR1000 Spurious Free Dynamic Range SFDR1600 SFDR2500 SFDR500 SFDR1600 SINAD300 Signal-to-Noise-Plus-Distortion Ratio CONDITIONS fIN = 300MHz, fCLK = 2.2Gsps fIN = 1000MHz, fCLK = 2.2Gsps (Note 8) fIN = 1600MHz, fCLK = 2.2Gsps (Note 8) fIN = 2500MHz, fCLK = 2.2Gsps fIN = 500MHz, fCLK = 2.5Gsps fIN = 1600MHz, fCLK = 2.5Gsps fIN = 300MHz, fCLK = 2.2Gsps 40.4 37.9 44.4 43.7 MIN TYP 61.7 51.1 50.3 45.0 53.7 44.6 44.1 43.1 42.1 40.1 43.1 40.5 -60 10-14 fCLK(MAX) tPWL tPWH tAD tAJ tSU tHD tPD1 CLK-to-DCO Propagation Delay tPD1DDR tPD1QDR tPD2 DCO-to-Data Propagation Delay tPD2DDR tPD2QDR DCO Duty Cycle (Note 8) (Note 8) DCO = fCLK / 4, CLK fall to DCO rise time DCO = fCLK / 8, DDR mode, CLK fall to DCO rise time DCO = fCLK / 16, QDR mode, CLK fall to DCO rise time DCO = fCLK / 4, DCO rise to data transition (Note 8) DCO = fCLK / 8, DDR mode, DCO rise to data transition (Note 8) DCO = fCLK / 16, QDR mode, DCO rise to data transition (Note 8) Clock mode independent -520 -520 + 2tCLK -520 + 2tCLK 2tCLK 2tCLK 45 to 55 300 250 1.6 1.6 1.6 +520 520 + 2tCLK 520 + 2tCLK % ps ns tCLK = tPWL + tPWH (Note 8) tCLK = tPWL + tPWH (Note 8) 2.2 180 180 200 0.2 Gsps ps ps ps ps ps ps dBc dB dBc MAX UNITS SINAD1000 fIN = 1000MHz, fCLK = 2.2Gsps (Note 8) SINAD1600 fIN = 1600MHz, fCLK = 2.2Gsps (Note 8) SINAD2500 fIN = 2500MHz, fCLK = 2.2Gsps SINAD500 Third-Order Intermodulation Metastability Probability TIMING CHARACTERISTICS Maximum Sample Rate Clock Pulse-Width Low Clock Pulse-Width High Aperture Delay Aperture Jitter Reset Input Data Setup Time Reset Input Data Hold Time IM3 fIN = 500MHz, fCLK = 2.5Gsps fIN1 = 1590MHz, fIN2 = 1610MHz at -7dBFS SINAD1600 fIN = 1600MHz, fCLK = 2.5Gsps 6 _______________________________________________________________________________________ 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs AC ELECTRICAL CHARACTERISTICS (continued) (VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.2Gsps, analog input amplitude at -1dBFS differential, clock input amplitude 400mVP-P differential, digital output pins differential RL = 100Ω. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER LVDS Output Rise Time LVDS Output Fall Time LVDS Differential Skew PortD Data Pipeline Delay PortC Data Pipeline Delay PortB Data Pipeline Delay PortA Data Pipeline Delay SYMBOL tRDATA tFDATA tSKEW1 tPDD tPDC tPDB tPDA CONDITIONS 20% to 80%, CL < 2pF 20% to 80%, CL < 2pF Any two LVDS output signals, except DCO MIN TYP 500 500