MAX11040

19-4302; Rev 0; 5/09 KIT ATION EVALU ABLE AVAIL 24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC General Description Features ♦ Four Fully Differential Simultaneously Sampled Channels ♦ Cascadable for Up to 32 Channels of Simultaneous Sampling ♦ 106dB SNR at 16ksps ♦ 117dB SNR at 1ksps ♦ 0.25% Error Over a 1000:1 Dynamic Range, Processed Over 16.7ms ♦ ±2.2V Full-Scale Input Range ♦ ±6V Overvoltage Protected Inputs ♦ Internal Crystal Oscillator ♦ 2.5V, 50ppm/°C Internal Reference or External Reference ♦ Programmable Output Data Rate 0.25ksps to 64ksps Range 0.065% Resolution ♦ Programmable Sampling Phase 0 to 333µs Delay in 1.33µs Steps ♦ SPI-/QSPI-/MICROWIRE-/DSP-Compatible 4-Wire Serial Interface ♦ Cascadable Interface Allows Control of Up to Eight Devices with a Single CS Signal ♦ 3.0V to 3.6V Analog Supply Voltage ♦ 2.7V to VAVDD Digital Supply Voltage ♦ 38-Pin TSSOP Package MAX11040 The MAX11040 is a 24-bit, 4-channel, simultaneoussampling, sigma-delta analog-to-digital converter (ADC). The device allows simultaneous sampling of as many as 32 channels using a built-in cascade feature to synchronize as many as eight devices. The serial interface of the MAX11040 allows reading data from all the cascaded devices using a single command. Four modulators simultaneously convert each fully differential analog input with a programmable data output rate ranging from 0.25ksps to 64ksps. The device achieves 106dB SNR at 16ksps and 117dB SNR at 1ksps. The MAX11040 operates from a single +3V supply. The differential analog input range is ±2.2V when using the internal reference, an external reference is optional. Each input is overvoltage protected up to ±6V without damage. The device uses an internal crystal oscillator or an external source for clock. The MAX11040 is compatible with SPI™, QSPI™, MICROWIRE™, and DSP-compatible 4-wire serial interfaces. An on-board interface logic allows one serial interface (with a single chip select) to control up to eight cascaded devices or 32 simultaneous sampling analog input channels. The MAX11040 is ideally suited for power-management systems. Each channel includes an adjustable sampling phase enabling internal compensation for phase shift due to external dividers, transformers, or filters at the inputs. The output data rate is adjustable with a 0.065% resolution (at 16ksps or below) to track the varying frequency of a periodic input. A SYNC input allows periodic alignment of the conversion timing of multiple devices with a remote timing source. The MAX11040 is available in a 38-pin TSSOP package specified over the -40°C to +105°C industrial temperature range. Functional Diagram OVRFLW FAULT AIN0+ AIN0REF0 AIN1+ AIN1REF1 AIN2+ AIN2REF2 AIN3+ AIN3REF3 24-BIT ADC DIGITAL FILTER SYNC DRDYIN Applications Power Protection Relay Equipment Multiphase Power Systems Industrial Data-Acquisition Systems Medical Instrumentation 24-BIT ADC DIGITAL FILTER DRDYOUT REGISTERS AND DIGITAL CONTROL SERIAL INTERFACE CASCIN CASCOUT CS SCLK 24-BIT ADC DIGITAL FILTER 24-BIT ADC DIGITAL FILTER DIN DOUT Ordering Information MAX11040 PART MAX11040GUU+ TEMP RANGE -40°C to +105°C PIN-PACKAGE 38 TSSOP REFIO 2.5V REFERENCE CRYSTAL OSCILLATOR +Denotes a lead(Pb)-free/RoHS-compliant package. AGND XIN XOUT CLKOUT DGND MICROWIRE is a trademark of National Semiconductor Corp. SPI/QSPI are trademarks of Motorola Inc. Pin Configuration appears at end of data sheet. 1 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC MAX11040 ABSOLUTE MAXIMUM RATINGS AVDD to AGND ........................................................-0.3V to +4V DVDD to DGND ......................................-0.3V to (VAVDD + 0.3V) AGND to DGND.....................................................-0.3V to +0.3V DIN, SCLK, CS, XIN, SYNC, DRDYIN, CASCIN to DGND..............................-0.3V to (VDVDD + 0.3V) DOUT, DRDYOUT, CASCOUT, CLKOUT, XOUT to DGND..................................-0.3V to (VDVDD + 0.3V) FAULT, OVRFLW to DGND ...................................-0.3V to +4.0V AIN_+ to AIN_- ......................................................-6.0V to +6.0V AIN_ _to AGND (VAVDD ≥ 3V, VDVDD ≥ 2.7V, FAULTDIS = 0, SHDN = 0, fXIN CLOCK ≥ 20MHz)....................-6.0V to +6.0V AIN_ _ to AGND (VAVDD < 3V or VDVDD < 2.7V or FAULTDIS = 1 or SHDN = 1 or fXIN CLOCK < 20MHz)........................................-3.5V to +3.5V REFIO, REF_ to AGND............................-0.3V to (VAVDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70°C) 38-Pin TSSOP (derated 13.7mW/°C above +70°C) ...1096mW Operating Temperature Range .........................-40°C to +105°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 = CREF3 = 1µF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER DC ACCURACY (Note 2) Resolution Differential Nonlinearity Integral Nonlinearity (Note 3) Offset Error Gain Error Offset-Error Drift Gain-Error Drift Change in Gain Error vs. fOUT Channel-to-Channel Gain Matching DYNAMIC SPECIFICATIONS (62.5Hz sine-wave input, 2.17VP-P) Signal-to-Noise Ratio Total Harmonic Distortion Signal-to-Noise Plus Distortion Spurious-Free Dynamic Range Relative Accuracy (Note 7) Bandwidth Latency Passband Flatness Amplitude-Dependent Phase Error Channel-to-Channel Phase Matching Phase-Error Drift SNR THD SINAD SFDR (Note 6) TA = +25°C and +105°C TA = -40°C TA = +25°C and +105°C TA = -40°C TA = +25°C and +105°C TA = -40°C 0.1% FS input 6.0% FS input -3dB (Note 8) From DC to 1.4kHz FS vs. 0.1% FS 3.4 405 < 0.1 < 0.01 0.0001 0.001 0.12 93 89 94 89 0.25 0.005 100 98 103 106 -94 -90 dB dB dB dB % kHz µs dB Deg Deg Deg (Note 4) (Note 5) (Note 5) fOUT = 0.25ksps to 64ksps DNL INL 24-bit no missing code TA = +25°C and +105°C TA = -40°C -1 -1 0.5 10 < 0.025 0.03 24 0.1 0.001 0.004 0.006 +1 +1 Bits LSB % FS mV % FS ppm/°C ppm/°C % FS % FS SYMBOL CONDITIONS MIN TYP MAX UNITS 2 _______________________________________________________________________________________ 24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 = CREF3 = 1µF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Channel-to-Channel Isolation Comon-Mode Rejection ANALOG INPUTS (AIN_+, AIN_-) Differential FS Input Range Positive Fault Threshold Negative Fault Threshold Fault Pin Response Time Input Impedance DC Leakage Current Input Sampling Rate Input Sampling Capacitance INTERNAL REFERENCE REFIO Output Voltage REFIO Output Resistance REFIO Temp Drift REFIO Long-Term Stability REFIO Output Noise REFIO Power-Supply Rejection EXTERNAL REFERENCE REFIO Input Voltage REFIO Sink Current REFIO Source Current REFIO Input Capacitance CRYSTAL OSCILLATOR (XIN, XOUT) Tested Resonant Frequency Maximum Crystal ESR Oscillator Startup Time Oscillator Stability Maximum Oscillator Load Capacitance DIGITAL INPUTS (SCLK, CS, DIN, SYNC, CASCIN, DRDYIN, XIN) Input Low Voltage Input High Voltage Input Hysteresis Input Leakage Current Input Capacitance VIL VIH VHYS IL CIN VDVDD = 3.0V 0.7 x VDVDD 100 ±0.01 15 ±1 0.3 x VDVDD V V mV µA pF VDVDD = 3.3V, excluding crystal (Note 10) 24.576 30 VPFT VAIN_+ = VAIN_fS = fXINCLOCK/8 VIN VPFT VNFT VAIN_+ - VAIN_VAIN_+ or VAIN_- (Note 9) VAIN_+ or VAIN_- (Note 9) -2.2 2.25 -2.65 2.5 130 > 0.5 ±0.01 3.072 4.0 ±1 +2.2 2.65 -2.25 V V V µs kΩ µA Msps pF CMRR SYMBOL CONDITIONS MIN TYP -130 109 MAX UNITS dB dB MAX11040 _______________________________________________________________________________________ 3 24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC MAX11040 ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 = CREF3 = 1µF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 0.15 x VDVDD 0.85 x VDVDD ±1 15 0.15 x VDVDD 0.85 x VDVDD 30 AVDD DVDD IAVDD IDVDD Normal operation Shutdown and f XINCLOCK = 0Hz Normal operation Shutdown and f XINCLOCK = 0Hz VAVDD = 3 .3V + 100mVP-P at 1kHz VAVDD = VDVDD = 3 .0V to 3.6V ESD tSCP tPW tSU tHD tDOT tDOE tDOD tCSW tSC tCOT CLOAD = 100pF CLOAD = 30pF CLOAD = 100pF CLOAD = 30pF CLOAD = 30pF 0.3 0.7 16 16 20 Human Body Model 50 20 10 0 1.5 10 < 16 20 16 16 3.0 2.7 25 0.1 11 0.3 70 75 2.5 3.6 VAVDD 35 5 15 UNITS CMOS DIGITAL OUTPUTS (DOUT, CASCOUT, DRDYOUT, CLKOUT) Output Low Voltage Output High Voltage Three-State Leakage Current Three-State Capacitance VOL VOH ILT COUT I SINK = 5 mA I SOURCE = 1 mA V V μA pF OPEN-DRAIN DIGITAL OUTPUTS (OVRFLW, FAULT) Output Low Voltage Output High Voltage Internal Pullup Resistance POWER REQUIREMENTS Analog Supply Voltage D igital Supply Voltage Analog Supply Current (Note 11) D igital Supply Current (Note 11) AC Positive-Supply Rejection DC Positive-Supply Rejection E SD PROTECTION A ll Pins SCLK Clock Period SCLK Pulse Width (High and Low) DIN or CS to SCLK Fall Setup SCLK Fall to DIN or CS Hold SCLK Rise to DOUT Valid CS Fall to DOUT Enable CS Rise to DOUT Disable CS Pulse Width C ASCIN to SCLK Rise Setup SCLK Rise to CASCOUT Valid kV ns ns ns ns ns ns ns ns ns ns TIMING CHARACTERISTICS (Figures 7–10) V V mA μA mA μA dB dB VOL VOH I SINK = 5 mA Internal pullup only V V k 4 _______________________________________________________________________________________ 24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 = CREF3 = 1µF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYNC Pulse Width XIN Clock Pulse Width D RDYIN to D RDYOUT XIN Clock to D RDYOUT Delay XIN Clock Period XIN Clock to SYNC Setup SYNC to XIN Clock Hold XIN to CLKOUT Delay Power-On Reset Delay SYMBOL tSYN tXPW tDRDY tXDRDY tXP tSS tHS tXCD (Note 13)