MAX11042

19-3984; Rev 2; 11/08 Wired Remote Controllers General Description The MAX11041/MAX11042 wired remote controllers convert up to six or 30 different pushbuttons into an I2C register. Together with low-cost pushbutton switches and 1% resistors, the MAX11041/MAX11042 are total solutions over a single-wire interface. A wired remote controller easily piggybacks to a standard 3.5mm headphone jack using a fourth contact or one of the audio signals. To conserve battery life, the MAX11041/MAX11042 consume only 5µA (typ) while reading keypresses in real time without microprocessor (µP) polling. The devices send the debounced keypress along with key duration to the application processor over the I2C interface. An 8-word FIFO buffer records up to four keypress events to allow plenty of time for the application processor to respond to the MAX11041/MAX11042. The MAX11041/MAX11042 include ±15kV ESD protection devices on the FORCE and SENSE inputs to ensure IEC 61000-4-2 compliance without any external ESD devices. The MAX11041/MAX11042 are available in a 12-pin TQFN package. The devices are specified over the extended temperature range (-40°C to +85°C). PART MAX11041ETC+ Features ♦ Detect Up to Six (MAX11042) or 30 (MAX11041) Different Keys and Jack Insertion/Removal ♦ Work with Either 32Ω or 16Ω Headphones ♦ Add Remote-Control Functionality to Devices Using a Simple Resistor and Switch Array ♦ Low-Power Operation Consuming a Supply Current of Only 5µA (typ) ♦ Work with Standard 2.5mm or 3.5mm 4-Pin Headphone Jacks ♦ Support Hold Function to Lockout Keys ♦ 100kHz/400kHz I2C Interface ♦ Single 1.6V to 3.6V Supply Voltage Range ♦ ±15kV ESD Protection (IEC 61000-4-2) MAX11041/MAX11042 Ordering Information TEMP RANGE -40°C to +85°C PIN-PACKAGE 12 TQFN-EP* Applications Multimedia Controls for Multimedia-Enabled Cell Phones Keyboard Encoder for Slider, Flip, and other Cell Phones Portable Media Players MP3, CD, DVD Players PDAs Digital Still Cameras MAX11042ETC+** -40°C to +85°C 12 TQFN-EP* *EP = Exposed pad. **Future product—contact factory for availability. +Denotes a lead-free/RoHs-compliant package. Pin Configuration SHDN 7 6 A0 5 SDA SCL 8 PDA Accessory Keyboards Multimedia Desktop Speakers Portable Game Consoles TOP VIEW 9 INT 10 VDD 11 MAX11041 MAX11042 + 1 GND 2 SENSE 3 VDD A1 FORCE 12 4 N.C. THIN QFN (4mm x 4mm x 0.6mm) EXPOSED PAD CONNECTED TO GND. ________________________________________________________________ Maxim Integrated Products 1 For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Wired Remote Controllers MAX11041/MAX11042 ABSOLUTE MAXIMUM RATINGS VDD to GND ...........................................................-0.3V to +4.0V INT to GND .................................................-0.3V to (VDD + 0.3V) SCL, SDA, A1, A0, SHDN to GND.........................-0.3V to +4.0V FORCE, SENSE to GND.........................................................±6V Current into Any Pin..........................................................±50mA Maximum ESD per IEC 61000-4-2 Human Body Model, FORCE, SENSE............................±15kV FORCE, SENSE Short to GND....................................Continuous Junction Temperature ......................................................+150°C Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +1.6V to 3.6V, CSENSE = 10nF, RSENSE = 10kΩ, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS Provided the keys meet the next three specifications; RJACK connected; use recommended circuit (Note 1) (Note 1) (Note 1) CSENSE = 10nF, external resistor from FORCE to SENSE is 10kΩ (RSENSE) Pulses shorter than this are ignored tCPW Time required for a new voltage (due to keypress) to be detected and stored in FIFO Time required for detection of key release and final time duration to be stored in FIFO (Note 2) (Note 2) One tick MSB is overflow bit 0 MIN TYP MAX UNITS KEY DETECTION CHARACTERISTICS MAX11041 MAX11042 30 Keys 6 100 13 ±1 Ω ms % Detectable Keys Maximum Switch Resistance Maximum Switch Bounce Time External Resistor Tolerance SWITCH DEBOUNCE Debounce Analog Time Constant Chatter Rejection Rising Voltage Debounce Time 0.4 18 18 ms ms ms Falling Voltage Debounce Time Jack Insertion Debounce Time Jack Removal Debounce Time DURATION COUNTER Duration-Counter Resolution Duration-Counter Range Duration-Counter Accuracy tLPWS 18 18 18 32 127 ±20 0.7 x VDD 0.3 x VDD -10 9 10 +10 ms ms ms ms Counts % DIGITAL INPUTS (SDA, SCL, SHDN, A0, A1) Input High Voltage Input Low Voltage Input Leakage Current Input Hysteresis Input Capacitance VIH VIL IIH, IIL V V µA %VDD pF 2 _______________________________________________________________________________________ Wired Remote Controllers MAX11041/MAX11042 ELECTRICAL CHARACTERISTICS (continued) (VDD = +1.6V to 3.6V, CSENSE = 10nF, RSENSE = 10kΩ, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER DIGITAL OUTPUTS (SDA, INT) Output High Voltage (INT) Output Low Voltage (INT) Output High Leakage Current Output Low Voltage (SDA) VOH VOLINT IOHL VOLSDA ISOURCE ≤ 2mA ISINK ≤ 2mA VOUT = VDD IOL = 3mA for VDD > 2V IOL = 3mA for VDD < 2V 0.9 x VDD 0.1 x VDD 1 0.4 0.2 x VDD 0 1.3 0.6 1.3 0.6 0.6 0 100 (Note 3) (Note 3) VDD = 3.6V (Note 3) VDD = 2.4V to 3.6V SDA Transmitting Fall Time tFT VDD = 1.6V to 2.4V Setup Time for STOP Condition Bus Capacitance Pulse Width of Suppressed Spike tSU,STO Cb tSP 0 20 + Cb / 10 20 + Cb / 10 20 + Cb / 10 20 + Cb / 20 20 + Cb / 20 0.6 400 50 300 300 250 250 ns 375 µs pF ns 900 400 V V µA V V SYMBOL CONDITIONS MIN TYP MAX UNITS I2C TIMING CHARACTERISTICS (see Figure 1) Serial Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition SCL Pulse-Width Low SCL Pulse-Width High Setup Time for a Repeated START Condition Data Hold Time Data Setup Time SDA and SCL Receiving Rise Time SDA and SCL Receiving Fall Time SDA Transmitting Rise Time fSCL tBUF tHD,STA tLOW tHIGH tSU,STA tHD,DAT tSU,DAT tRR tFR tRT kHz µs µs µs µs µs ns ns ns ns ns ____________________________________________________________________________________ 3 Wired Remote Controllers MAX11041/MAX11042 ELECTRICAL CHARACTERISTICS (continued) (VDD = +1.6V to 3.6V, CSENSE = 10nF, RSENSE = 10kΩ, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER POWER SUPPLIES Power-Supply Voltage Average Operational Supply Current Shutdown Power-Supply Current Jack Current Key Current SHDN High to Part Active VDD IDDOP IDDSHDN IDDJACK Excluding jack/key current Jack inserted, RJACK = 619kΩ Excluding jack/key current Flowing when jack is inserted Wake-up time 4 90 5 1.6 5 8 1 3.6 20 V µA µA µA µA ms SYMBOL CONDITIONS MIN TYP MAX UNITS IDDBUTTON Flowing when keys pressed (Note 4) Note 1: Note 2: Note 3: Note 4: Recommended properties of external switch for proper detection of 30 keys or key combinations. See the Jack Insertion/Removal Detection section. Cb is the bus capacitance in pF. Key current depends on external key resistors and is calculated by VDD / (30.1kΩ + RSW). START CONDITION (S) SDA REPEAT START CONDITION (Sr) tRR,tRT tFR,tFT STOP CONDITION (P) tBUF tHD,STA tHD,DAT tSU,DAT tSU,STA tHD,STA tSU,STO SCL START CONDITION (S) tHIGH tRR tFR tLOW Figure 1. I2C Serial-Interface Timing 4 _______________________________________________________________________________________ Wired Remote Controllers Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) MAX11041/MAX11042 DEBOUNCE SCOPE SHOT (FALLING) MAX11041/42 TOC01 DEBOUNCE SCOPE SHOT (RISING) MAX11041/42 TOC02 KEYPRESS RELEASE SCOPE SHOT* MAX11041/42 TOC03 VSENSE VSENSE VSENSE INT DEBOUNCED KEY ADDED TO FIFO μP READS FIFO INT DEBOUNCE KEY ADDED TO FIFO μP READS FIFO INT DEBOUNCE KEY ADDED TO FIFO μP READS FIFO 10ms/div 10ms/div 10ms/div VDD SUPPLY CURRENT vs. VOLTAGE MAX11041/42 TOC04 VDD SHUTDOWN SUPPLY CURRENT vs. VOLTAGE NO JACK INSERTED MAX11041/42 TOC05 7.0 NO JACK INSERTED 6.5 TA = +85°C 6.0 IDD (µA) 1.00 0.75 IDD (µA) 5.5 TA = +25°C 5.0 0.50 TA = +85°C TA = -40°C 0.25 4.5 4.0 1.6 2.1 TA = -40°C 2.6 VDD (V) 3.1 3.6 0 1.6 2.1 TA = +25°C 2.6 VDD (V) 3.1 3.6 *Oscilloscope shots are taken with simulated bounce and chatter. Real switches will exhibit different bounce and chatter characteristics. ____________________________________________________________________________________ 5 Wired Remote Controllers Pin Description MAX11041/MAX11042 PIN 1 2 NAME GND SENSE Ground FUNCTION Voltage Sense Input. Connect SENSE to FORCE through an external lowpass filter composed of RSENSE and CSENSE (see the FORCE and SENSE section). There is a ±15kV IEC61000-4-2 ESD protection on SENSE. Power-Supply Input. Connect both VDD inputs together and bypass each VDD with a 0.1µF capacitor to GND. No Connection. Leave unconnected or connect to VDD. I2C Address Input 1. Logic state represents bit 1 of the I2C slave address. I2C Address Input 0. Logic state represents bit 0 of the I2C slave address. Active-Low Shutdown Input. Bring SHDN low to put the MAX11041/MAX11042 in shutdown mode. FORCE is in a high-impedance state while SHDN is low. I2C Serial-Interface Clock Input. SCL requires a pullup resistor. I2C Serial-Interface Data Input/Output. SDA requires a pullup resistor. Active-Low Interrupt Output. INT goes low when a valid keypress is detected at SENSE. Force Output. Connect FORCE to the external resistor array. Connect SENSE to FORCE through an external lowpass filter composed of RSENSE = 10kΩ and CSENSE = 10nF. There is a ±15kV IEC61000-4-2 ESD protection on FORCE. Exposed Pad. Connect EP to GND. 3, 11 4 5 6 7 8 9 10 12 EP VDD N.C. A1 A0 SHDN SCL SDA INT FORCE EP Detailed Description The MAX11041/MAX11042 wired remote controllers recognize either six or 30 different keypresses consisting of a resistor/switch array over a single connector. Designed for wired remote controllers on the headphone or headset cord, the MAX11041/MAX11042 contain debouncing circuitry and jack insertion/ removal detection. During a keypress, the MAX11041/ MAX11042 store the key type and key duration in an 8word FIFO and INT (interrupt output) goes low. The results stored in the FIFO are accessed through the I2C interface. Chip ID The chip ID identifies the features and capabilities of the wired remote controller to the software. For the MAX11041, the chip ID is 0x00. For the MAX11042, the chip ID is 0x01. Control Register The MAX11041/MAX11042 contain one control register (see Table 1). Bits C7, C6, and C5 control software shutdown. Set FORCE high-impedance and indicate if the FIFO is empty. Write/read to the control register through the I2C-compatible serial interface (see the Digital Serial Interface section). FORCE and SENSE During a keypress, a unique external resistor (RSW_) located in the remote controller connects SENSE to ground (Figure 2). This event changes the impedance seen by the SENSE line. The MAX11041/MAX11042 decode this resistor value to an 8-bit result (see the Required Resistor Set section). FORCE and SENSE are ±15kV ESD (IEC 61000-4-2) protected. FIFO The MAX11041/MAX11042 contain an 8-word FIFO that can hold enough information for four keypresses and releases. Each keypress and release results in two data words being stored into the FIFO. Each FIFO word consists of 2 bytes. The 1st byte is the decoded keypress or release (K7–K0) and the 2nd byte is the keypress or release duration time. Table 2 shows the format of a keypress entry into the FIFO. Read the FIFO through the I2Ccompatible serial interface (see the D igital Serial Interface section). At power-up, all the FIFO is reset such that K7–K0 are set to 0xFF hex and 0x0F, and T6–T0 are set to 0x00. See the Applications Information section for an example of how data is entered into the FIFO. Register Description The MAX11041/MAX11042 contain one 8-bit control register, an 8-word FIFO (each word consists of an 8bit key value and an 8-bit duration value), and an 8-bit chip ID. 6 _______________________________________________________________________________________ Wired Remote Controllers MAX11041/MAX11042 WIRED REMOTE CONTROLLER TO AUDIO CIRCUIT FORCE RSW0 MAX11041 MAX11042 RSENSE SENSE CSENSE 10nF 10kΩ JACK/PLUG CONNECTION RSW1 RSW30 RJACK HOLD SWITCH Figure 2. Recommended FORCE and SENSE Configuration Table 1. Control Register BITS C7 C6 C5 C4–C0 READ/WRITE R/W R/W R — POWER-UP STATE 1 0 1 Not used DESCRIPTION 0 = FORCE is high-impedance 1 = FORCE is not high-impedance (normal operation) 0 = Normal operation 1 = Power-down state, full reset 1 = FIFO is empty 0 = FIFO is not empty Reading/writing has no effect Table 2. FIFO Data Format FIFO DATA Keypress type (MAX11041) Keypress type (MAX11042) Keypress duration K7 K2 OF K6 K1 T6 K5 K0 T5 BIT NAMES K4 X T4 K3 X T3 K2 X T2 K1 X T1 K0 X T0 X = Don’t care. ____________________________________________________________________________________ 7 Wired Remote Controllers MAX11041/MAX11042 Table 3. Chip ID Data Format CHIP ID MAX11041 MAX11042 BIT NAMES I7 0 0 I6 0 0 I5 0 0 I4 0 0 I3 0 0 I2 0 0 I1 0 0 I0 0 1 Keypress Detection and Debounce At power-up, the MAX11041/MAX11042 begin to monitor the SENSE input for keypresses. When the MAX11041/MAX11042 detect a keypress at SENSE, they attempt to debounce the SENSE input. After successful debouncing of the input, the corresponding keypress result is inserted into the FIFO. In addition, INT goes low to signal a keypress to the µP. Keypress FIFO and Time Duration After detecting and debouncing a key, the decoded key is stored in one byte of the 8-word FIFO. A 7-bit internal timer starts counting the duration of the keypress (one count = 32ms) and the result is stored after each increment in another byte of the 8-word FIFO. The 8th bit in the time duration byte is an overflow bit that is set when the count reaches 128. After the count reaches 128, the 7-bit timer rolls over to 0 and continues to count while the 8th bit becomes set and stays set until the associated FIFO entry is cleared. For keypress durations longer than 8.16s, see the Extended Keypresses section. When the device detects another change in resistance at SENSE (either by key release or another keypress), the count resets and the FIFO begin recording the next keypress/duration. This allows the 8-word FIFO to store time duration and key-type information for up to four keypresses and releases. When the FIFO is full and a key is pressed, the oldest keypress information in the FIFO is written over. Writing to the power-down bit (bit 6) in the control register or bringing SHDN low clears the FIFO to its power-on-reset (POR) state. KEY TYPE ➀ ➁ ➂ ➃ KEY TYPE ➀ ➁ ➂ VINT TIME VINT TIME TIME TIME 1. DEBOUNCED KEYPRESS STORED IN FIFO AND INT GOES LOW, DURATION TIMER STARTS. 2. PROCESSOR READS FIFO AND INT GOES HIGH. KEY TYPE AND CURRENT KEYPRESS DURATION TIME SENT. FIFO IS NOT CLEARED. 3. KEYPRESS RELEASES AND INT GOES LOW. KEY TYPE AND FINAL KEYPRESS DURATION TIME STORED IN FIFO. 4. PROCESSOR READS THE FIFO AND INT GOES HIGH. KEYPRESS INFORMATION STORED IN FIFO FROM STEP 3 IS CLEARED. 1. DEBOUNCED KEYPRESS STORED IN FIFO AND INT GOES LOW. DURATION TIMER STARTS. 2. KEYPRESS RELEASES. KEY TYPE AND KEYPRESS TIME DURATION INFORMATION STORED IN FIFO. 3. PROCESSOR READS FIFO COMPLETELY AND INT GOES HIGH. PREVIOUS KEYPRESS INFORMATION CLEARED. Figure 3. Reading the FIFO While the Key is Still Pressed 8 Figure 4. Reading the FIFO After the Key is Released _______________________________________________________________________________________ Wired Remote Controllers MAX11041/MAX11042 WRITE FORMAT START ADDRESS BYTE 0 5 BITS A1 A0 R/W ACK CONTROL REG DATA BYTE 1 C7–C0 ACK STOP SLAVE TO MASTER S 0 A A P MASTER TO SLAVE READ FORMAT ADDRESS BYTE 0 5 BITS A1 A0 R/W 1 ACK A CHIP ID BYTE 1 I7–I0 ACK A CONTROL REG DATA BYTE 2 C7–C0 ACK A KEY TYPE BYTE 3 K7–K0 ACK A KEY DURATION BYTE 4 OF, T6–T0 ACK A STOP P START S Figure 5. Read/Write Formats Reading the FIFO While the Key is Still Pressed When a valid keypress occurs, INT goes low, signaling to the processor that a key has been pressed (see Figure 3). If the processor reads the FIFO while the key is still pressed, the key type and current duration of the keypress is sent. The current keypress information in the FIFO is not cleared after a read operation if the key is still pressed. In addition, after a read operation, if the key is still pressed, INT goes high again until the device detects another keypress/release, freeing the processor from polling. Conversely, if the processor chooses to poll the duration of the keypress, INT stays high at this time no matter how many times the processor reads the FIFO. When INT goes low again (from another keypress/release), key type and final time duration of the keypress is available in the FIFO. When the FIFO is read after the key release, the information from that keypress is cleared and INT goes high again. Reading the FIFO After the Key has Released When a valid keypress occurs, INT goes low, signaling to the processor that a key has been pressed (see Figure 4). If the processor reads the FIFO after the key has already been released (or an additional key was pressed), the key type and final duration time of that keypress is sent. In addition, the information from the keypress is cleared and INT goes high again. Write Format The only write to the MAX11041/MAX11042 that is possible is to the control register (C7–C0). Use the following sequence to write to the control register (see Figure 5): 1) After generating a start condition (S), address the MAX11041/MAX11042 by sending the appropriate slave address byte with its corresponding R/W bit set to a 0 (see the Slave Address and R/W Bit section). The MAX11041/MAX11042 answer with an ACK bit (see the Acknowledge Bits section). 2) Send the appropriate data bytes to program the control register (C7–C0). The MAX11041/MAX11042 answer with an ACK bit. 3) Generate a stop condition (P). Read Format To read the control register and key type/duration stored in FIFO, use the following sequence (see Figure 5): 1) After generating a start condition (S), address the MAX11041/MAX11042 by sending the appropriate slave address byte with its corresponding R/W bit set to a 1 (see the Slave Address and R/W Bit section). The MAX11041/MAX11042 answer with an ACK bit (see the Acknowledge Bits section). 2) The MAX11041/MAX11042 send the 8-bit chip ID I7–I0. Afterwards, the master must send an ACK bit. 3) The MAX11041/MAX11042 send the contents of the control register (C7–C0) starting with the most significant bit. Afterwards, the master must send an ACK bit. Digital Serial Interface The MAX11041/MAX11042 contain an I2C-compatible interface for data communication with a host processor (SCL and SDA). The interface supports a clock frequency up to 400kHz. SCL and SDA require pullup resistors that are connected to a positive supply. Figure 5 details the read and write formats. ____________________________________________________________________________________ 9 Wired Remote Controllers MAX11041/MAX11042 S SDA 0 1 0 0 0 A1 A2 R/W ACK SCL 1 2 3 4 5 6 7 8 9 Figure 6. Slave Address and R/W Bit S P SDA SCL Figure 7. START and STOP Conditions S NOT ACKNOWLEDGE SDA ACKNOWLEDGE SCL 1 2 8 9 Figure 8. Acknowledge Bits 4) The MAX11041/MAX11042 send the latest keypress type (K7–K0) stored in the FIFO starting with the most-significant bit. Afterwards the master must send an ACK bit. 5) The MAX11041/MAX11042 send the corresponding keypress time duration (OF, T6–T0) stored in the FIFO starting with the most significant bit (OF). Afterwards the master must send an ACK bit. 6) The master must generate a stop condition (P). Slave Address and R/W Bit The MAX11041/MAX11042 include a 7-bit slave address. The first 5 bits (MSBs) of the slave address are factory-programmed and always 01000. The logic state of the address inputs (A1 and A0) determine the last two LSBs of the device address (see Figure 6). Connect A1 and A0 to VDD (logic high) or GND (logic low). A maximum of four MAX11041/MAX11042 devices can be connected on the same bus at one time using these address inputs. The 8th bit of the address byte is a read/write bit (R/W). If this bit is set to 0, the device expects to receive data. If this bit is set to 1, the device expects to send data. 10 ______________________________________________________________________________________ Wired Remote Controllers MAX11041/MAX11042 Table 4. Required Resistor Set for the MAX11041 KEY 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Jack inserted Jack removed STANDARD 1% RESISTOR VALUE (Ω) 0 1470 2550 3740 4990 6340 7680 9310 11000 13000 15000 17400 20000 22600 26100 30100 34000 38300 44200 51100 59000 68100 80600 95300 118000 147000 191000 261000 402000 825000 619000 ∞ FIFO RESISTOR CODE* FUNCTION LOWEST 0 11 19 27 35 42 50 58 66 74 82 90 98 105 114 123 130 137 146 154 162 170 178 186 194 202 211 218 226 235 243 254 HIGHEST 1 13 21 30 38 46 53 62 70 78 86 94 102 110 119 127 135 142 150 159 166 174 182 190 198 206 214 222 229 237 245 255 Function 0 Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9 Function 10 Function 11 Function 12 Function 13 Function 14 Function 15 Function 16 Function 17 Function 18 Function 19 Function 20 Function 21 Function 22 Function 23 Function 24 Function 25 Function 26 Function 27 Function 28 Function 29 Jack inserted Jack removed *Values outside FIFO resistor code are considered invalid. ___________________________________________________________________________________ 11 Wired Remote Controllers MAX11041/MAX11042 Table 5. Required Resistor Set for the MAX11042 KEY 0 1 2 3 4 5 Jack inserted Jack removed STANDARD 1% RESISTOR VALUE (Ω) 0 7320 15400 28700 54900 133000 130000 ∞ FIFO RESISTOR CODE 0 1 2 3 4 5 6 7 FUNCTION Previous Next Play/pause Stop Volume up Volume down Jack inserted Jack removed Bit Transfer One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high and stable are considered control signals (see the START and STOP Conditions section). Both SDA and SCL remain high when the bus is not active. START and STOP Conditions The master initiates a transmission with a START condition (S), a high-to-low transition on SDA while SCL is high. The master terminates a transmission with a STOP condition (P), a low-to-high transition on SDA while SCL is high (see Figure 7). Acknowledge Bits Data transfers are acknowledged with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and the MAX11041/MAX11042 generate ACK bits. To generate an ACK, pull SDA low before the rising edge of the ninth clock pulse and keep it low during the high period of the ninth clock pulse (see Figure 8). To generate a NACK, leave SDA high before the rising edge of the ninth clock pulse and keep it high for the duration of the ninth clock pulse. Monitoring NACK bits allows for detection of unsuccessful data transfers. The master can also use NACK bits to interrupt the current data transfer to start another data transfer. If the master uses NACK during a read from the FIFO, the FIFO word pointer is not incremented and the next FIFO read produces the same FIFO word. Thus, the master must provide the ACK bit to advance the FIFO word pointer. Applications Information Required Resistor Set Tables 4 and 5 show the required resistor sets for 30 and six key implementations. Resistors must have a 1% tolerance. Jack Insertion/Removal Detection During jack insertion there may be several false key entries written to the FIFO. When a jack insertion/removal is detected, it is necessary to read the FIFO repeatedly until the final change in jack state is located (see Figure 9). Extended Keypresses In certain applications, a key triggers different events depending on the duration of the keypress, simultaneous keypresses, or a specific order of keypresses. Long Keypress Detection In some applications, the duration of the keypress determines the event triggered. For example, TALK dials the entered phone number normally and initiates voice dialing if it is held down. A second common use of holding a key down is to generate a continuous stream of events, such as the volume control or fast forward. Simultaneous Keypress Detection Certain applications require the detection of simultaneous keypresses, such as and combinations. This is done in software. For instance, the µP detects the SHIFT key is being pressed. When the µP detects an additional keypress instead of a key release, it knows the corresponding code is a result of two resistors in parallel. 12 ______________________________________________________________________________________ Wired Remote Controllers KEY TYPE JACK REMOVED JACK DETECTED FALSE KEYS ➀ ➁ ➂ ➃ Order of Keypress Detection Some applications require detection of the specific sequence of keys in software by looking for unique key presses within 32 ticks (1s). If the duration between keypresses exceeds the allowed time, assume the keypress is in error and return to the previous known state. MAX11041/MAX11042 Power-Up Jack Detect and Keypress Example TIME VINT Figure 10 illustrates the FIFO entries during a typical sequence of events. TIME Layout, Grounding, and Bypassing Position RSENSE and CSENSE as close to the device as possible. Bypass VDD with a 0.1µF capacitor to GND as close to the device as possible. Connect GND to a quiet analog ground plane. Route digital lines away from SENSE and FORCE. 1. JACK INSERTION DETECTED AND ENTERED IN FIFO. 2. JACK REMOVAL DETECTED AND ENTERED IN FIFO. 3. JACK INSERTION DETECTED AND ENTERED IN FIFO. 4. FIFO IS READ UNTIL EMPTY (INT GOES HIGH). THE LAST READ BEFORE THE EMPTY FIFO IS REACHED IS THE FINAL STATE OF THE JACK DETECTION. Figure 9. Jack Insertion Detection ___________________________________________________________________________________ 13 Wired Remote Controllers MAX11041/MAX11042 VSENSE 1 2 3 4 5 6 7 8 9 10 11 12 TIME VINT t1 t2 t3 t4 t5 t6 TIME 1 SHDN TRANSITION FROM LOW TO HIGH. 2 OPEN CIRCUIT DETECTED AND ENTERED IN FIFO. DURATION TIMER STARTS. WRITE POINTER 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF TIMER... 0x00 0x00 0x00 0x00 0x00 0x00 0x00 READ POINTER 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 WRITE POINTER READ POINTER JACK INSERTION DETECTED AND ENTERED IN FIFO. FINAL DURATION TIME FROM 2 IS STORED. NEW DURATION TIME READ FOR JACK DETECTION STARTS. POINTER WRITE 0xFF t1/32ms POINTER JD CODE TIMER... 0x00 0xFF 0xFF 0x00 0x00 0xFF 0xFF 0x00 0x00 0xFF 0xFF 0x00 3 JACK REMOVAL DETECTED (OPEN CIRCUIT) AND STORED IN FIFO. FINAL DURATION TIME FROM 3 IS STORED. NEW DURATION TIME FOR OPEN CIRCUIT STARTS. READ POINTER 0xFF t1/32ms WRITE t2/32ms JD CODE POINTER TIMER... 0xFF 0xFF 0x00 0x00 0xFF 0xFF 0x00 0x00 0xFF 0xFF 0x00 4 5 READ POINTER JACK INSERTION DETECTED AND ENTERED IN FIFO. FINAL DURATION TIME FROM 4 IS STORED. NEW DURATION TIME FOR JACK DETECTION STARTS. 0xFF JD CODE 0xFF JD CODE 0xFF 0xFF 0xFF 0xFF t1/32ms t2/32ms t3/32ms TIMER... 0x00 0x00 0x00 0x00 6 μP READS UNTIL FIFO EMPTY FLAG IS REACHED. FURTHER READS RESULT IN JD CODE AND CURRENT TIME DURATION OF JD CODE BEING SENT. 0xFF 0xFF 0xFF JD CODE 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 TIMER... 0x00 0x00 0x00 0x00 7 KEY PRESS DETECTED AND ENTERED IN FIFO. FINAL TIME DURATION FROM 6 IS STORED. NEW DURATION TIME FOR KEYPRESS STARTS. 0xFF 0xFF 0xFF JD CODE KEY_ CODE 0xFF 0xFF 0xFF 0x00 0x00 0x00 t4/32ms TIMER... 0x00 0x00 0x00 8 μP READS UNTIL FIFO EMPTY FLAG IS REACHED. FURTHER READS RESULT IN KEY_ CODE AND CURRENT TIME DURATION OF KEY_ CODE BEING SENT. 0xFF 0xFF 0xFF 0xFF KEY_ CODE 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 TIMER... 0x00 0x00 0x00 WRITE POINTER READ POINTER WRITE POINTER READ POINTER WRITE POINTER READ POINTER WRITE POINTER 9 KEY RELEASE DETECTED (JD CODE) AND ENTERED IN FIFO. FINAL DURATION TIME FROM 8 IS STORED. NEW DURATION TIME FOR JD CODE STARTS. 0xFF 0xFF 0xFF 0xFF KEY_ CODE JD CODE 0xFF 0xFF 0x00 0x00 0x00 0x00 t5/32ms TIMER... 0x00 0x00 10 μP READS UNTIL FIFO EMPTY FLAG IS REACHED. FURTHER READS RESULT IN JD CODE AND CURRENT TIME DURATION OF JD CODE BEING SENT. 0xFF 0xFF 0xFF 0xFF 0xFF JD CODE 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 TIMER... 0x00 0x00 11 JACK REMOVAL DETECTED (OPEN CIRCUIT) AND STORED IN FIFO. FINAL DURATION TIME FROM 10 IS STORED. NEW DURATION TIME FOR OPEN CIRCUIT STARTS. 0xFF 0xFF 0xFF 0xFF 0xFF JD CODE 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 t6/32ms TIMER... 0x00 12 μP READS UNTIL FIFO EMPTY FLAG IS REACHED. FURTHER READS RESULT IN 0xFF AND CURRENT TIME DURATION BEING SENT. 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 TIMER... 0x00 * READ POINTER WRITE POINTER READ POINTER WRITE POINTER READ POINTER WRITE POINTER READ POINTER WRITE POINTER DATA ENTERED *BOTH POINTERS WRAP AROUND TO THE TOP WHEN THEY GET TO THE END OF FIFO. RESET DATA (POR) Figure 10. Power-Up, Jack Detect, and Keypress Example 14 ______________________________________________________________________________________ Wired Remote Controllers Functional Diagram VDD MAX11041/MAX11042 8-WORD FIFO 8-BIT KEY I2C INTERFACE FORCE CONTROL LOGIC INT DEBOUNCE KEY DETECTOR ±15kV ESD SENSE 8-BIT DURATION DURATION TIMER MAX11041 MAX11042 A1 A0 SCL SDA SHDN GND ___________________________________________________________________________________ 15 Wired Remote Controllers MAX11041/MAX11042 Typical Operating Circuit RSW0 RSW1 RSW30 3.3V RJACK HOLD SWITCH DAC I2S VOLUME DAC VBUS 3.3V μP 0.01μF VDD AO MAX9850 SDA SCL I2C MAX11041 MAX11042 FORCE FIFO DEBOUNCE RESISTOR DETECTOR ESD SENSE 10kΩ 10nF OUTPUT INTERRUPT SHDN INT CONTROL LOGIC DURATION TIMER A1 GND Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 12 TQFN-EP PACKAGE CODE T1244-4 DOCUMENT NO. 21-0139 16 ______________________________________________________________________________________ Wired Remote Controllers Revision History REVISION NUMBER 1 2 REVISION DATE 8/07 11/08 Removed leaded package types Changed FIFO data format table DESCRIPTION PAGES CHANGED — 7 MAX11041/MAX11042 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. Boblet