MAX11043

19-4250; Rev 2; 3/11 KIT ATION EVALU ABLE AVAIL 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC General Description The MAX11043 features 4 single-ended or differential channels of simultaneous-sampling ADCs with 16-bit resolution. The MAX11043 contains a versatile filter block and programmable-gain amplifier (PGA) per channel. The filter consists of seven cascaded 2ndorder filter sections for each channel, allowing the construction of a 14th-order filter. The filter coefficients are user-programmable. Configure each 2nd-order filter as lowpass (LP), highpass (HP), or bandpass (BP) with optional rectification. Gain and phase mismatch of the analog signal path is better than -50dB. The ADC can digitize signals up to 200kHz. A 40MHz serial interface provides communication to and from the device. The SPI™ interface provides throughput of 1600ksps; 4 channels at 400ksps per channel or 2 channels at 800ksps per channel. A software-selectable scan mode allows reading the ADC results while simultaneously updating the DAC. Other features of the MAX11043 include an internal (+2.5V) or external (+2.0V to +2.8V) reference, power-saving modes, and a PGA with gains of 1 to 64. The PGA includes an equalizer (EQ) function that automatically boosts lowamplitude, high-frequency signals for applications such as CW-chirp radar. The MAX11043 includes two 8-bit coarse DACs that set the high and low references for a second-stage 12-bit fine DAC, typically used for VCO control. Use software controls to write to the DAC or step the DAC up and down under hardware control in programmable steps. The device operates from a +3.0V to +3.6V supply. The MAX11043 is available in a 40-pin, 6mm x 6mm TQFN package and operates over the extended -40°C to +125°C temperature range. Features o 4 Single-Ended or Differential Channels of Simultaneous-Sampling, 16-Bit ADCs o ±10 LSB INL, ±1 LSB DNL, No Missing Codes o 93dB SFDR at 100kHz Input o PGA with Gain of 1, 2, 4, 8, 16, 32, or 64 for Each Channel o EQ Function Automatically Boosts High-Frequency, Low-Amplitude Signals o Seven-Stage Internal Programmable Biquad Filters per Channel o High Throughput, 400ksps per Channel for 4 Channels o Dual-Stage DAC Two 8-Bit Coarse Reference DACs 12-Bit Fine DAC o +2.5V Internal Reference or +2.0V to +2.8V External Reference o Single +3.3V Operation o Shutdown and Power-Saving Modes o 40-Pin, 6mm x 6mm TQFN Package o -40°C to +125°C Operating Temperature MAX11043 Ordering Information PART MAX11043ATL+ TEMP RANGE -40°C to +125°C PIN-PACKAGE 40 TQFN-EP* MAX11043ATL/V+** -40°C to +125°C 40 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. *EP = Exposed pad. **Future product—contact factory for availability. Pin Configuration REFDACH REFDAC DGND AGND DVDD SHDN 20 OSCOUT 19 OSCIN 18 EOC 17 I.C. 16 SCLK 15 DIN 14 DOUT 13 CS 12 CONVRUN 11 DACSTEP 1 AINBN 2 REFA 3 AINAN 4 AINAP 5 AVDD 6 AGND 7 DGND 8 DVDD 9 DVREG 10 UP/DWN AVDD AOUT REFD TOP VIEW Applications Automotive Radar Systems Data Acquisition Systems Industrial Controls Power-Grid Monitoring AINDN 31 AINDP 32 AGND 33 REFBP 34 I.C. 35 AINCN 36 AINCP 37 REFC 38 REFB 39 AINBP 40 30 29 28 27 26 25 24 23 22 21 REFDACL MAX11043 + *EP SPI is a trademark of Motorola, Inc. *CONNECT EP TO AGND. TQFN ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 ABSOLUTE MAXIMUM RATINGS AVDD to AGND ....................................................-0.3V to +4.0V DVDD to DGND .....................................................-0.3V to +4.0V DVREG to DGND...................................................-0.3V to +3.0V AGND to DGND.....................................................-0.3V to +0.3V Analog I/O, REFDACH, REFDACL, REFA, REFB, REFC, REFD, AOUT, REFDAC, REFBP to AGND .....-0.3V to (VAVDD + 0.3V) UP/DWN, CONVRUN, SHDN, DACSTEP, EOC, Digital I/O, OSCIN, OSCOUT to DGND....................-0.3V to (VDVDD + 0.3V) Maximum Current into Any Pin except AVDD, DVDD, DVREG, AGND, DGND...............................................................±50mA Continuous Power Dissipation (TA = +70°C) TQFN Multilayer Board (derate 37mW/°C above +70°C) ................................2963mW TQFN Single-Layer Board (derate 26.3mW/°C above +70°C) ..........................2105.3mW Operating Temperature Range .........................-40°C to +125°C Junction Temperature ......................................................+150°C Storage Temperature Range ............................-65°C to +150°C Lead Temperature (soldering, 10s) ................................+300°C Soldering Temperature (reflow) ......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VAVDD = +3.0V to +3.6V, VDVDD = +3.0V, CDVREG = 10µF, VAGND = VDGND = 0V, common-mode input voltage = VAVDD/2, VREFBP = VREFA = VREFB = VREFC = VREFD = +2.5V (external reference), VREFDAC = VREFDACH = +1.25V (external reference), VREFDACL = 0V, CREFBP = CREFA = CREFB = CREFC = CREFD = CREFDAC = 1µF, fSCLK = 38.4MHz, fEXCLK = 38.4MHz (external clock applied to OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. TA = TMIN to TMAX, unless otherwise noted (Note 1). Typical values are at TA = +25°C.) PARAMETER SIGMA-DELTA ADC Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset-Error Drift Gain Error Gain Temperature Coefficient Channel Gain-Error Matching Channel Offset Matching Maximum Full-Scale Input Input-Referred Noise Spectral Density Second Harmonic to Fundamental Third Harmonic to Fundamental Spurious-Free Dynamic Range Channel-to-Channel Isolation Channel Phase Matching SFDR Unused channels are shorted and unconnected Between all channels, including complete analog signal path Complete analog signal path Complete analog signal path ADC modulator gain = 1 100kHz -80 -80 77 85 -0.25 -60 1.2 85 -93 -110 93 108 -0.05 +0.05 GE Trimmed with 150Ω/330pF anti-alias filter -1 ±50 +0.25 +60 N INL DNL OE Guaranteed monotonic 16 -16 -1 -35 ±30 +1 ±2 +1 +35 Bits LSB LSB mV µV/°C % ppm/°C % mV VP-P nV/√Hz dB dB dB dB Degrees SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE (PGA Disabled, PGA Gain = 1 x (25kHz -1dB Full-Scale Signal)) 2 _______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.0V to +3.6V, VDVDD = +3.0V, CDVREG = 10µF, VAGND = VDGND = 0V, common-mode input voltage = VAVDD/2, VREFBP = VREFA = VREFB = VREFC = VREFD = +2.5V (external reference), VREFDAC = VREFDACH = +1.25V (external reference), VREFDACL = 0V, CREFBP = CREFA = CREFB = CREFC = CREFD = CREFDAC = 1µF, fSCLK = 38.4MHz, fEXCLK = 38.4MHz (external clock applied to OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. TA = TMIN to TMAX, unless otherwise noted (Note 1). Typical values are at TA = +25°C.) PARAMETER Maximum Full-Scale Input Input-Referred Noise Spectral Density Second Harmonic to Fundamental Third Harmonic to Fundamental Spurious-Free Dynamic Range Channel-to-Channel Isolation Channel Phase Matching SFDR Unused channels are shorted and unconnected Between all channels, including complete analog signal path ADC modulator gain = 1 100kHz -0.05 SYMBOL CONDITIONS ADC modulator gain = 1 100kHz MIN TYP 150 20 -92 -94 92 110 +0.05 MAX UNITS mVP-P nV/√Hz dB dB dB dB Degrees MAX11043 DYNAMIC PERFORMANCE (PGA Enabled, PGA Gain = 8 x (25kHz -1dB Full-Scale Signal)) DYNAMIC PERFORMANCE (PGA Enabled, PGA Gain = 16 x (25kHz -1dB Full-Scale Signal)) Maximum Full-Scale Input Input-Referred Noise Spectral Density Second Harmonic to Fundamental Third Harmonic to Fundamental Spurious-Free Dynamic Range Channel-to-Channel Isolation Channel Phase Matching SFDR Unused channels are shorted and unconnected Between all channels, including complete analog signal path ADC modulator gain = 1 (Note 2) 100kHz -80 -77 SFDR Input referred (Note 3) 77 -0.075 75 15 -99 -93 93 106 +0.075 mVP-P nV/√Hz dB dB dB dB Degrees DYNAMIC PERFORMANCE (EQ Mode (5kHz -1dB Full-Scale Signal, CONFIG_ Register Bit 3 = 1)) Maximum Full-Scale Input Input-Referred Noise Spectral Density Second Harmonic to Fundamental Third Harmonic to Fundamental Spurious-Free Dynamic Range 800 6 -90 -98 89 mVP-P nV/√Hz dB dB dB _______________________________________________________________________________________ 3 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.0V to +3.6V, VDVDD = +3.0V, CDVREG = 10µF, VAGND = VDGND = 0V, common-mode input voltage = VAVDD/2, VREFBP = VREFA = VREFB = VREFC = VREFD = +2.5V (external reference), VREFDAC = VREFDACH = +1.25V (external reference), VREFDACL = 0V, CREFBP = CREFA = CREFB = CREFC = CREFD = CREFDAC = 1µF, fSCLK = 38.4MHz, fEXCLK = 38.4MHz (external clock applied to OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. TA = TMIN to TMAX, unless otherwise noted (Note 1). Typical values are at TA = +25°C.) PARAMETER Channel-to-Channel Isolation Channel Phase Matching DYNAMIC PERFORMANCE (All Modes) Conversion Rate Minimum Throughput Power-Supply Rejection Ratio Absolute Voltage Any Input DCPSRR (Note 4) Direct input to ADC, gain = 1 Input Impedance (Note 5) DIFF = 1 DIFF = 0 0 25 100 7 7 5.5 50 5 190 205 205 2 2 1 17 2.5 2.5 1.25 2.8 150 VREFBP VREFDAC 2.8 700 1.4 pF kHz kHz kHz kHz V µA V µA V kΩ kΩ ANALOG INPUTS (AINAP/AINAN, AINBP/AINBN, AINCP/AINCN, AINDP/AINDN) VAVDD V All 4 channels 2 channels only 5 50 400 800 ksps ksps dB SYMBOL CONDITIONS Unused channels are shorted and unconnected Between all channels, including complete analog signal path MIN 80 -0.12 TYP 104 +0.12 MAX UNITS dB Degrees Direct input to ADC, gain = 2 Direct input to ADC, gain = 4 or 8 PGA gain = 16 Input Capacitance EQ FILTER (Analog and Digital) Unity-Gain Frequency Lower Transition Frequency Upper Transition Frequency LP FILTER -3dB Corner Frequency REFERENCE INPUT REF_ Input Voltage Range Input Current REFBP Input Voltage Range Input Current REFDAC Input Voltage Range Input Resistance VREF_ EQ mode only Default Default, from 40dB/decade to 0dB/decade Default, from 0dB/decade to -80dB/decade Default 4 _______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.0V to +3.6V, VDVDD = +3.0V, CDVREG = 10µF, VAGND = VDGND = 0V, common-mode input voltage = VAVDD/2, VREFBP = VREFA = VREFB = VREFC = VREFD = +2.5V (external reference), VREFDAC = VREFDACH = +1.25V (external reference), VREFDACL = 0V, CREFBP = CREFA = CREFB = CREFC = CREFD = CREFDAC = 1µF, fSCLK = 38.4MHz, fEXCLK = 38.4MHz (external clock applied to OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. TA = TMIN to TMAX, unless otherwise noted (Note 1). Typical values are at TA = +25°C.) PARAMETER REFDAC_ Input Voltage Range Input Resistance INTERNAL REFERENCE Reference Voltage Reference Temperature Coefficient CRYSTAL OSCILLATOR (Max ESR 100Ω, 22pF Load Capacitors to DGND) Maximum Crystal Operating Frequency External Clock Input Frequency Range Stability Startup Time OSCIN Input Low Voltage OSCIN Input High Voltage OSCIN Leakage Current DIGITAL INPUTS Input High Voltage Input Low Voltage Input Hysterisis Input Leakage Current Input Capacitance DIGITAL OUTPUTS Output-Voltage High Output-Voltage Low Three-State Leakage Current Three-State Output Capacitance VOLTAGE REGULATOR Regulated Digital Supply Voltage POWER REQUIREMENTS Analog Supply Voltage Digital Supply Voltage 3.0 3.0 3.6 3.6 V V DVREG Internal use only 2.5 V VOH VOL ISOURCE = 0.8mA ISINK = 1.6mA DOUT only DOUT only -1 15 VDVDD - 0.6 0.4 +1 V V µA pF IIN CIN VIN = 0V or VDVDD -1 15 VIH VIL 15 +1 0.7 x VDVDD 0.3 x VDVDD V V mV µA pF Epson Electronics MA-505 (16MHz) External clock applied to OSCIN Excluding crystal Epson Electronics MA-505 (16MHz) When driven with external clock source When driven with external clock source 0.7 x VDVDD -5 +5 16 4 25 10 0.3 x VDVDD 40 MHz MHz ppm ms V V µA VREFBP 2.45 2.5 100 2.55 V ppm/°C SYMBOL VREFDAC_ CONDITIONS MIN 0 150 TYP MAX 1.4 UNITS V kΩ MAX11043 _______________________________________________________________________________________ 5 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.0V to +3.6V, VDVDD = +3.0V, CDVREG = 10µF, VAGND = VDGND = 0V, common-mode input voltage = VAVDD/2, VREFBP = VREFA = VREFB = VREFC = VREFD = +2.5V (external reference), VREFDAC = VREFDACH = +1.25V (external reference), VREFDACL = 0V, CREFBP = CREFA = CREFB = CREFC = CREFD = CREFDAC = 1µF, fSCLK = 38.4MHz, fEXCLK = 38.4MHz (external clock applied to OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. TA = TMIN to TMAX, unless otherwise noted (Note 1). Typical values are at TA = +25°C.) PARAMETER Analog Supply Current Digital Supply Current Shutdown Current SYMBOL IAVDD IDVDD IAVDD IDVDD 12 INL DNL Guaranteed monotonic -5 -1 -70 ±50 -2 ±20 0 +5 +1 +70 CONDITIONS All channels selected PGA disabled PGA enabled MIN TYP 60 120 26 MAX 80 140 40 5 5 UNITS mA mA mA STATIC ACCURACY—FINE DAC (CL = 200pF, RL = 10kΩ) Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset-Error Temperature Coefficient Gain Error Gain-Error Temperature Coefficient DYNAMIC PERFORMANCE—FINE DAC (CL = 200pF, RL = 10kΩ) Output Noise DAC Glitch Impulse Voltage-Output Settling Time Voltage-Output Slew Rate STATIC ACCURACY—REFDACH AND REFDACL Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset-Error Temperature Coefficient Gain Error Gain-Error Temperature Coefficient FLASH MEMORY Programming Endurance Data Retention TA = +85°C 10,000 15 Cycles Years -5 INL DNL 8 -0.5 -0.2 -30 ±50 +5 ±20 +0.5 +0.2 +30 Bits LSB LSB mV µV/°C LSB ppm of FS/°C f = 0.1Hz to 1MHz Major carry transition 25% to 75% FS 1% FS 200 12 3 1.5 0.6 µVRMS nV•s µs V/µs Bits LSB LSB mV µV/°C % ppm of FS/°C 6 _______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.0V to +3.6V, VDVDD = +3.0V, CDVREG = 10µF, VAGND = VDGND = 0V, common-mode input voltage = VAVDD/2, VREFBP = VREFA = VREFB = VREFC = VREFD = +2.5V (external reference), VREFDAC = VREFDACH = +1.25V (external reference), VREFDACL = 0V, CREFBP = CREFA = CREFB = CREFC = CREFD = CREFDAC = 1µF, fSCLK = 38.4MHz, fEXCLK = 38.4MHz (external clock applied to OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. TA = TMIN to TMAX, unless otherwise noted (Note 1). Typical values are at TA = +25°C.) PARAMETER SPI INTERFACE SCLK Clock Period SCLK Pulse-Width High SCLK Pulse-Width Low SCLK Rise to DOUT Transition CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Setup Time DIN to SCLK Rise Setup Time DIN to SCLK Rise Hold Time CS Pulse-Width High CS Rise to DOUT Disable CS Fall to DOUT Enable EOC Fall to CS Fall tCP tCH tCL tDOT tCSS tCSH tDS tDH tCSPWH tDOD tDOE tRDS CLOAD = 20pF CLOAD = 20pF 1 10 CLOAD = 20pF 25 10 10 1 10 5 10 0 10 20 15 ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS MAX11043 Note 1: Devices 100% production tested at TA = +125°C. Guaranteed by design and characterization to TA = -40°C. Note 2: Full scale in analog EQ mode decreases with increasing frequency at a rate of 20dB/decade from 8kHz. If digital EQ is also used, full scale decreases with increasing frequency at 40dB/decade from 5kHz. Note 3: SFDR in the EQ mode is normalized to the input by subtracting the analog EQ gain at each frequency (20dB/decade) from the FFT results. Note 4: The absolute input voltage range is 0 to AVDD. For optimal performance, use a common-mode voltage of AVDD/2. Note 5: Switched capacitor input impedance is proportional to 1/fC. Where f is the sampling frequency and C is the input capacitance. Typical Operating Characteristics (VAVDD = +3.3V, VDVDD = +3.0V, fSCLK = fEXCLK = 19.2MHz, VREFBP, VREF_ = +2.5V, common-mode input voltage = VAVDD/2, TA = +25°C, unless otherwise noted.) INL vs. CODE MAX11043 toc01 400ksps FFT LP MODE MAX11043 toc02 800ksps FFT LP MODE fIN = 50kHz GAIN = 1 fIN = 50kHz GAIN = 1 MAX11043 toc03 5 4 3 2 INL (LSB) 1 0 -1 -2 -3 -4 -5 0 16384 32768 CODE (LSB) 49152 LP MODE GAIN = 1 0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140 65536 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz) 0 50 100 150 200 250 300 350 400 FREQUENCY (kHz) _______________________________________________________________________________________ 7 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 Typical Operating Characteristics (continued) (VAVDD = +3.3V, VDVDD = +3.0V, fSCLK = fEXCLK = 19.2MHz, VREFBP, VREF_ = +2.5V, common-mode input voltage = VAVDD/2, TA = +25°C, unless otherwise noted.) 400ksps FFT EQ MODE MAX11043 toc04 800ksps FFT EQ MODE fIN = 100kHz VINP-P = 1.4mV MAX11043 toc05 SINAD vs. INPUT AMPLITUDE 70 60 50 SINAD (dB) 40 30 20 10 0 1kHz 10kHz 50kHz MAX11043 toc06 0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 0 fIN = 5kHz VINP-P = 560mV 0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140 80 -10 -20 0 200 FREQUENCY (kHz) 400 -90 -80 -70 -60 -50 -40 -30 -20 -10 INPUT AMPLITUDE (dBFS) 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz) FINE DAC DNL vs. CODE MAX11043 toc07 FINE DAC INL vs. CODE 4 3 2 INL (LSB) 1 0 -1 -2 -3 -4 -5 MAX11043 toc08 FINE DAC SETTLING 25% TO 75% FS STEP MAX11043 toc09 1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 CODE (LSB) 3072 5 500mV/div 0V 0 1024 2048 CODE (LSB) 3072 4096 4096 FINE DAC SETTLING 75% TO 25% FS STEP MAX11043 toc10 FINE DAC SETTLING 1% STEP-UP MAX11043 toc11 20mV/div 500mV/div 1200mV 0V 1µs/div 8 _______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Typical Operating Characteristics (continued) (VAVDD = +3.3V, VDVDD = +3.0V, fSCLK = fEXCLK = 19.2MHz, VREFBP, VREF_ = +2.5V, common-mode input voltage = VAVDD/2, TA = +25°C, unless otherwise noted.) COARSE DAC DNL FINE DAC SETTLING vs. CODE FINE DAC NOISE FLOOR 1% STEP-DOWN MAX11043 toc12 MAX11043 toc13 MAX11043 0.8 0.6 20mV/div DNL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 1µs/div 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz) 0 CODES 3 TO 255 DACH 20dBm/div DACL 1200mV 64 128 CODE (LSB) 192 256 COARSE DAC INL vs. CODE 0.4 0.3 0.2 INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 64 128 CODE (LSB) 192 256 DACL DACH CODES 3 TO 255 MAX11043 toc15 COARSE DAC SETTLING TIME, POSITIVE STEP MAX11043 toc16 COARSE DAC SETTLING TIME, NEGATIVE STEP MAX11043 toc17 0.5 200mV/div 2ms/div 2ms/div DVREG VOLTAGE vs. TEMPERATURE MAX11043 toc18 POWER-ON RESET vs. TEMPERATURE 1.8 1.6 SUPPLY VOLTAGE (V) 1.4 1.2 1.0 0.8 0.6 0.4 DIGITAL SUPPLY ANALOG SUPPLY MAX11043 toc19 2.369 2.368 DVREG VOLTAGE (V) 2.367 2.366 2.365 2.364 2.363 2.362 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) 2.0 0.2 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) _______________________________________________________________________________________ MAX11043 toc14 0dBm 1.0 200mV/div 9 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 Pin Description PIN 1 2 3 4 5, 26 6, 24, 33 7, 23 8, 22 9 10 11 12 13 14 15 16 17, 35 18 19 20 21 25 27 28 29 30 31 32 34 36 37 38 39 40 — NAME AINBN REFA AINAN AINAP AVDD AGND DGND DVDD DVREG UP/DWN DACSTEP CONVRUN CS DOUT DIN SCLK I.C. EOC OSCIN OSCOUT SHDN AOUT REFDACL REFDACH REFDAC REFD AINDN AINDP REFBP AINCN AINCP REFC REFB AINBP EP Channel B Analog Negative Input Channel A Reference Bypass. Bypass REFA with a nominal 1µF capacitor to AGND. Channel A Analog Negative Input Channel A Analog Positive Input Analog Supply. Bypass each AVDD with a nominal 1µF capacitor to AGND. Analog Ground. Connect AGND inputs together. Digital Ground. Connect DGND inputs together. Digital Supply. Bypass each DVDD with a nominal 1µF capacitor to DGND. Regulated Digital Core Supply. Bypass DVREG to DGND with a 10µF capacitor. DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled. DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising edge of the system clock. Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when CONVRUN is low. Active-Low Serial-Interface Chip Select Serial-Interface Data Out. Data transitions on the rising edge of SCLK. Serial-Interface Data In. Data is sampled on the rising edge of SCLK. Serial-Interface Clock Internally Connected. Connect to either AGND or DGND. Active-Low End-of-Conversion Indicator. EOC asserts low to indicate that new data is ready. Crystal Oscillator/External Clock Input Crystal-Oscillator Output. Leave unconnected when using external clock. Active-High Shutdown Input. Drive high to shut down the MAX11043. Buffered 12-Bit Fine DAC Output Fine DAC Low Reference Bypass. Bypass REFDACL with a nominal 1µF capacitor to AGND. Fine DAC High Reference Bypass. Bypass REFDACH with a nominal 1µF capacitor to AGND. Coarse DAC Reference Bypass. Bypass REFDAC with a nominal 1µF capacitor to AGND. Channel D Reference Bypass. Bypass REFD with a nominal 1µF capacitor to AGND. Channel D Analog Negative Input Channel D Analog Positive Input Main Reference Bypass. Bypass REFBP with a nominal 1µF capacitor to AGND. Channel C Analog Negative Input Channel C Analog Positive Input Channel C Reference Bypass. Bypass REFC with a nominal 1µF capacitor to AGND. Channel B Reference Bypass. Bypass REFB with a nominal 1µF capacitor to AGND. Channel B Analog Positive Input Exposed Pad. Connect EP to a ground plane on the PCB to enhance thermal dissipation. Internally connected to AGND. Not intended as an electrical connection point. FUNCTION 10 ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Functional Diagram AVDD AINAP UP/DWN PGA EQ AINAN SIGMA-DELTA ADC PROGRAMMABLE DIGITAL FILTER SERIAL INTERFACE REFA DACSTEP CONVRUN EOC SHDN SCLK DOUT DIN PGA EQ AINBN SIGMA-DELTA ADC PROGRAMMABLE DIGITAL FILTER DVDD MAX11043 AINBP REFB FLASH MAX11043 AINCP PGA EQ AINCN SIGMA-DELTA ADC PROGRAMMABLE DIGITAL FILTER POR REFC AINDP PGA EQ SIGMA-DELTA ADC PROGRAMMABLE DIGITAL FILTER DIGITAL SUPPLY INTERNAL REGULATOR +2.5V CLOCK DVREG AINDN REFD R 8-BIT DAC CRYSTAL OSCILLATOR AND CLOCK BUFFER 12-BIT DAC OSCOUT OSCIN +2.5V VOLTAGE REFERENCE R 2x REFBP REFDAC REFDACL REFDACH AOUT AGND DGND ______________________________________________________________________________________ 11 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 Detailed Description The MAX11043 features 4 single-ended or differential channels of simultaneous-sampling ADCs with 16-bit resolution. The MAX11043 contains a versatile filter block and PGA per channel. The filter consists of seven cascaded 2nd-order filter sections for each channel allowing the construction of a 14th-order filter. The filter coefficients are user-programmable. Configure each 2nd-order filter as a LP filter, HP filter, or BP filter with optional rectification. Gain and phase mismatch of the analog signal path is better than -50dB. The ADCs can digitize signals up to 200kHz. A 40MHz serial interface provides communication to and from the device. The SPI interface provides throughput of 1600ksps; 4 channels at 400ksps per channel or 2 channels at 800ksps per channel. A software-selectable scan mode allows reading the ADC results while simultaneously updating the DAC. Other features of the MAX11043 include an internal (+2.5V) or external (+2.0V to +2.8V) reference, power-saving modes, and a PGA with gains of 1 to 64. The PGA includes an EQ function that automatically boosts low-amplitude, highfrequency signals for applications such as CW-chirp radar. The MAX11043 includes two 8-bit coarse DACs that set the high and low references for a second-stage 12-bit fine DAC, typically used for VCO control. Use software controls to set the DAC, or step the DAC up and down using hardware control in programmable steps. MAX11043 Signal Path Each of the 4 ADC channels features a PGA and filter block that feeds the signal to the sigma-delta modulator. The PGA can either be bypassed, which provides a gain of 1, set to a gain of 8, a gain of 16, or set to analog EQ mode. For more amplification, set the ADC modulator gain to one, two, or four. After the modulator, the result passes through the sinc 5 filter and decimator. Seven biquad programmable digital filters isolate the band of interest. Read the result using the 40MHz SPI interface. See Figure 1. Analog-to-Digital Converter The MAX11043 features a quad sigma-delta ADC architecture with 4 differential input channels. For singleended operation, connect the N input to the common-mode voltage or bypass to AGND with a 10µF capacitor. All inputs feature a programmable bias generator; see the CONFIG_ Register (0Ch–0Fh) section. All four ADCs convert simultaneously with a maximum modulator sampling rate of 9.6Msps; decimated by 12 or 24 for output rates of 800ksps and 400ksps, respectively. The SPI bus limits the maximum output data rate to 40Mbps. Sinc 5 Filter The sinc 5 filter removes high-frequency noise from the output of the sigma-delta modulator and sets the upper frequency response of the ADC. It also decimates the modulator data by a factor of 12, providing a maximum of 800ksps to the programmable filters when the modulator is operating at 9.6Msps. Figure 2 shows the frequency characteristics of the sinc 5 filter with the CHAN X FINE GAIN RANGE: -4 TO +4 RESOLUTION = 16 BITS DECSEL 0 1 DECIMATE 2 1 TOTAL DECIMATION 24 12 IN PGA AND FILTER MODULATOR WITH GAINS OF 1, 2, OR 4 SINC 5 FILTER AND DECIMATE BY 12 FINE GAIN ADJUST BIQUAD FILTER 1 BIQUAD FILTER 7 DECIMATE BY 1 OR 2 SPI 7 BIQUAD FILTERS IN SERIES PGA AND FILTER MODES PDPGA BYPASS LP FILTER AND GAIN 8X LP FILTER AND GAIN 16X EQUALIZER 1 0 0 0 PGAG X 0 1 X EQ X 0 0 1 GAIN 1 2 4 4 MODG1 0 0 1 1 MODG0 0 1 0 1 BIQUAD MODES LP FILTER EQUALIZER USER DEFINED FILT 1 0 X RAM POR VALUES POR VALUES USER VALUES Figure 1. Signal Path 12 ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC modulator running at 9.6Msps. Operating the modulator at a lower sample rate causes a proportional reduction in the frequency response of the sinc 5 filter. The total attenuation of the MAX11043 is the sum of the analog filtering, the sinc 5 filter, and the seven stages of programmable filters. EOC asserts low when new data is available. Initiate a data read prior to the next rising edge of EOC or the result is overwritten. EOC asserts high upon read completion of all active channels. Use ConfigA, ConfigB, ConfigC, and ConfigD registers to read single channel data. Concatenated data is available in the ADCAB, ADCCD, and ADCABCD registers. Use concatenated registers to ensure simultaneous results are read. See the Register Functions section for more details. A software-selectable scan mode automatically sends the result from selected channels following the C S falling edge and allows other registers to be simultaneously updated. To enable scan mode, set SCHAN_ bits high. See the Configuration Register (08h) section for a detailed description. The ADC output is presented in two’s complement format (Figure 3). MAX11043 Equalizer (EQ) The EQ matches the frequency/gain characteristics of CW-chirp radar systems where the distance to the target is proportional to the measured frequency. Distant targets not only have a higher frequency, they have a weaker signal. Hence, higher frequencies need more amplification than lower frequencies. The EQ provides gain proportional to frequencies up to 190kHz, at which point the gain rolls off at 80dB/decade. The EQ consists of an analog section in the PGA and a digital EQ created from the biquad filters. The analog EQ (PGA) provides 20dB/decade of gain and the default digital EQ provides an additional 20dB/decade of gain. Together they provide 40dB/decade of gain up to 190kHz with a gain of 0dB at 5kHz. Variations in the manufacturing process affect the gain and phase of the analog filter. Compensation for these variations include adjustments to the digital filter during the manufacture of the MAX11043. Use the analog and digital EQs together for optimal performance. Conversion and ADC Reading Drive CONVRUN high to initiate a continuous conversion on all 4 channels. Keep CONVRUN high for the entire conversion process. Do not pulse CONVRUN. Digital Filter Seven cascaded, individually configurable, 2nd-order filter elements make up the digital filter. Figure 4 shows the structure of a single filter section. Configure these elements as LP, BP, HP, or all pass (AP) filters with optional rectification. Filter configuration is transferred from the flash to coefficient RAM (C-RAM) on power-up. Store custom filters permanently in the flash or write directly to C-RAM each time on power-up. Two separate sets of programmable coefficients exist for each filter. Dual coefficient sets allow rapid filter reconfiguration. These filter coefficients are programmed to LP and EQ modes at the factory. Multiple flash memory pages exist so that custom filters can be created while preserving factory-programmed filter coefficients. SINC 5 FILTER AT 9.6Msps MAX11043 fig02 0 -20 ATTENUATION (dB) -40 -60 -80 -100 0111 1111 1111 1111 0111 1111 1111 1110 0111 1111 1111 1101 BINARY OUTPUT CODE 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1000 0000 0000 0010 -120 0 400 800 1200 1600 2000 FREQUENCY (kHz) 1000 0000 0000 0001 1000 0000 0000 0000 -FS -1 0 +1 +FS INPUT VOLTAGE (LSB) Figure 2. Sinc 5 Filter Frequency Response Figure 3. Two’s Complement Transfer Function 13 ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 Filter coefficients A1 and B1 are always 1. B3 is limited to -1, 0, and 1. Filter coefficients A2, A3, and B2 are stored as 16-bit two’s complement values in the range of -4 to +4. Filter coefficients A2 and A3 are stored as -A2 and -A3. Gain is limited to the following values 24, 22, 20, 2-2, 2-4, 2-6, 2-8, and 2-10. For better gain resolution, adjust the Fine Gain A/B/C/D Registers at the input of each filter set. Fine gain adjustment has a resolution of 16 bits and a gain range of -4 to +4. Set the RECT bit to rectify the filter output. Figures 5–8 show the response to a step input of the default filters used for ADC trimming. RECT IN + 1/A1 B1 + ABS G OUT 2500 SINC 5 FILTER OUTPUT MAX11043 fig05 2000 Z-1 OUTPUT (LSB) X + -A2 B2 + 1500 1000 Z-1 500 Y -A3 B3 0 0 2 4 SAMPLE 6 8 10 Figure 4. Single Programmable 2nd-Order Filter Section Figure 5. Sinc 5 Filter Response to a Step Input Table 1. Default Filter Coefficients DEFAULT LOWPASS FILTER COEFFICIENTS STAGE 1 2 3 4 5 6 7 STAGE 1 2 3 4 5 6 7 B1 1 1 1 1 1 1 1 B1 1 1 1 1 1 1 1 B2 + 2.0 (typ) +1.9509 +1.6139 +1.1488 +0.7415 +0.4651 +0.3296 B2 + 2.0 (typ) +1.9401 +1.5458 +1.0518 +0.6785 -1.0000 +0.4902 B3 +1.0000 +1.0000 +1.0000 +1.0000 +1.0000 +1.0000 +1.0000 B3 +1.0000 +1.0000 +1.0000 +1.0000 +1.0000 +0.0000 +1.0000 A1 1 1 1 1 1 1 1 A1 1 1 1 1 1 1 1 A2 +0.468 (typ) +0.6874 +0.5936 +0.4395 +0.2715 +0.1310 +0.0493 A2 +0.468 (typ) +0.6886 +0.5803 +0.4139 +0.2563 +0.0039 +0.1649 A3 +0.607 (typ) +0.1317 +0.2015 +0.3258 +0.4851 +0.6685 +0.8788 A3 +0.607 (typ) +0.1359 +0.2275 +0.3887 +0.5966 -0.0000 +0.8489 GAIN +0 -2 -2 +0 +0 +0 +0 GAIN +0 +0 -2 +0 +0 +4 +2 DEFAULT EQUALIZER COEFFICIENTS 14 ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Programmable Gain Amplifier Each ADC channel features an input buffer with input impedance of at least 5kΩ and programmable gain of eight or 16. When set to a gain of one, the signal bypasses the PGA to reduce noise. The PGA features an optional 20dB/decade analog EQ mode, with a gain of 0dB near 8kHz and attenuation above 190kHz to reduce out-of-band noise. Using the digital EQ filter adds another 20dB/decade of gain and sets the 0dB frequency to 5kHz. Control the EQ and PGA gain from their respective CONFIG_ registers. For additional filtering and equalization, use the integrated digital filters. the step size. The UP/DWN input sets the direction of the step. Drive UP/DWN high to step up, drive low to step down. The coarse 8-bit, dual tap DAC generates the high and low reference values for the fine DAC. Obtain the coarse DAC reference from the main reference or by driving the REFDAC input externally. The main reference, REFBP, is divided by two before the coarse DAC. When driving REFDAC, REFDACH, or REFDACL directly, ensure the voltage to the fine DAC does not exceed AVDD/2 to prevent the output amplifier from saturating. MAX11043 Digital-to-Analog Converter The MAX11043 features a 12-bit fine DAC with high and low reference inputs set by the 8-bit, dual tap coarse DAC or driven externally. The output buffer of the fine DAC has a gain of two and can drive 10kΩ and 200pF in parallel. Bypass the REFDACH and REFDACL with a 1µF capacitor when using the coarse DAC to set the reference values, or power down the buffers and drive REFDACH and REFDACL with external references. Alternatively drive one of the fine DAC references using the coarse DAC and the other using an external reference. The fine DAC register contains the current value of the output. The output value changes by writing to this register or by the rising edge of the DACSTEP input. The DAC register updates on the next rising edge of the system clock following the rising edge of the DACSTEP input. The programmable DACSTEP register contains LP FILTER OUTPUT MAX11043 fig07 2500 2000 OUTPUT (LSB) 1500 1000 500 0 0 20 40 60 80 100 SAMPLE Figure 7. LP Filter Response to a Step Input EQ FILTER OUTPUT 30,000 25,000 20,000 OUTPUT (LSB) 15,000 10,000 5000 0 -5000 -10,000 -15,000 -20,000 0 20 40 60 80 100 SAMPLE 0 -500 0 OUTPUT (LSB) MAX11043 fig06 STAGE 1 FILTER OUTPUT 3000 2500 2000 1500 1000 500 MAX11043 fig08 35,000 3500 10 20 30 40 50 SAMPLE Figure 6. EQ Filter Response to a Step Input Figure 8. Stage 1 Default Filter Response to a Step Input 15 ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 Reference (REFBP) The MAX11043 features an internal 2.5V bandgap reference. Bypass REFBP with a 1µF capacitor or power down the buffer amplifier and drive REFBP with an external reference. In internal reference mode, REFBP provides the main reference voltage for the MAX11043. Refer to www.maxim-ic.com/references for a list of available precision references. In addition to the integrated main reference, there are seven separate references derived from REFBP, one for each ADC channel, one for the coarse DAC, and two (one high and one low) for the fine DAC. When using the main reference, bypass each of the references with a 1µF capacitor or set the appropriate bits (7–0), in the reference (10h) register, to power down the references and drive externally. Use external references capable of driving a 700µA or total load. The system clock, used for all internal timing, is derived from the clock divider setting and the input clock. For optimal performance, derive the SPI clock and system clock from the same source. Power Saving The MAX11043 features an active-high power-down input, as well as an SPI-controlled power-down bit that places the MAX11043 in low-power mode. In addition, the MAX11043 features an independent, SPI-controlled, power-down for each ADC channel, the DAC, and the oscillator. See the Configuration Register (08h) section for more details. Serial Communication The SPI-compatible interface allows synchronous serial data transfers up to 40Mbps. The bandwidth is divided between the DACs and the ADC. Maximum conversion throughput depends on which read commands are used. The highest conversion rates are obtained by using the scan mode. The second highest rate is obtained by reading concatenated registers. The slowest method is to read the results individually. Configure the SPI master for SCLK to idle low (SCLK is low when CS is asserted). The data at DIN is latched on the rising edge of SCLK. Data at DOUT transitions immediately after the rising edge of SCLK. All SPI transactions start with a command byte. The command byte selects the address of the register and the mode of operation (read/write). Clock Sources The MAX11043 features an internal 16MHz oscillator that supports either an external crystal or ceramic resonator. For highest performance, set bit 15 in the configuration register to 1 and use an external clock (EX clock) source, up to 40MHz, to drive OSCIN. A programmable clock divider divides the EX clock by 2, 3, 4, or 6 to generate the ADC sample clock. The system clock, used for all digital timing, is twice the ADC sample clock. Ensure that the minimum EX clock high or low time is greater than 25ns when using the divide-by2 or divide-by-3 mode. SPI Command Byte BIT 7 START BIT 6 ADR4 BIT 5 ADR3 BIT 4 ADR2 BIT 3 ADR1 BIT 2 ADR0 BIT 1 R/W BIT 0 0 START : Start bit. This bit must be 0 for normal operation. ADR_: Device register address bits. See the register map in Table 2. R/W: Read/write bit. 1 = read from device. 0 = write to device. 16 ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 tDS tCSS CS tDH tCL tCP tCH tCSH SCLK DIN START ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 R/W = 0 0 D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE X HIGH IMPEDANCE DOUT Figure 9. SPI 8-Bit Write Operation tCSS tDOE CS tDS tDH tCP tCH tCL tDOT tDOD SCLK DIN X START ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 R/W = 1 0 D7 X D6 X D5 X D4 X D3 X D2 X D1 X D0 X HIGH IMPEDANCE DOUT HIGH IMPEDANCE Figure 10. SPI 8-Bit Read Operation ______________________________________________________________________________________ 17 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 Register Map Table 2. SPI Register Map ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh REGISTER NAME ADCA ADCB ADCC ADCD ADCAB ADCCD ADCABCD Status Configuration DAC DACSTEP DACH/DACL ConfigA ConfigB ConfigC ConfigD Reference/Delay AGain BGain CGain DGain Filter coefficient address Filter coefficient data out Filter coefficient data in Flash mode Flash addr Flash data in Flash data out Reserved Reserved Reserved Reserved FUNCTION ADC channel A result register ADC channel B result register ADC channel C result register ADC channel D result register ADC channels A and B results register ADC channels C and D results register ADC channels A, B, C, and D results register Status register Configures the device Fine DAC value Step size for DAC increment/decrement function High and low coarse DAC values ADC channel A configuration ADC channel B configuration ADC channel C configuration ADC channel D configuration Sets the operation state of the reference and buffers Channel A fine gain Channel B fine gain Channel C fine gain Channel D fine gain Selects the filter coefficient to read or write. This autoincrements each time the coefficient data register is accessed. Coefficient RAMs output data Filter coefficient data Flash mode selection register Flash address register Flash data in register Flash data out register — — — — BITS 16/24 16/24 16/24 16/24 32/48 32/48 64/96 8 16 16 16 8+8 16 16 16 16 16 16 16 16 16 8 32 32 8 16 16 16 — — — — 18 ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Register Functions ADCA, ADCB, ADCC, and ADCD Result Registers (00h–03h) The ADC channel A, B, C, and D result registers provide the result data from the 4 ADC channels. EOC asserts low when new data is available. Initiate a data read prior to the next rising edge of EOC or the result is overwritten. Set bit 5 of the configuration register 08h high to read the data out in 24-bit resolution or set bit 5 low to read the data out in 16-bit resolution. ADCAB, ADCCD, and ADCABCD Result Registers (04h–06h) Registers ADCAB, ADCCD, and ADCABCD contain concatenated ADC results ensuring simultaneous results are read. This reduces the risk of reading samples delayed by one cycle from channel to channel. Set bit 5 of the configuration register 08h high to read the data out in 24-bit resolution or set bit 5 low to read the data out in 16-bit resolution. MAX11043 Status Register (07h) BIT 7 X BIT 6 X BIT 5 Flash Busy BIT 4 BOOT BIT 3 OFLGA BIT 2 OFLGB BIT 1 OFLGC BIT 0 OFLGD The status register contains the channel overflow flags and POR bits. X: Don’t-care bits. Flash Busy: Do not start a new flash operation until this is 0. BOOT: Power-on reset flag. OFLG_: Channel overflow flag, one per channel. Configuration Register (08h) BIT 15 EXTCLK BIT 14 CLKDIV1 BIT 13 CLKDIV0 BIT 12 PD BIT 11 PDA BIT 10 PDB BIT 9 PDC BIT 8 PDD BIT 7 PDDAC BIT 6 PDOSC BIT 5 24BIT BIT 4 SCHANA BIT 3 SCHANB BIT 2 SCHANC BIT 1 SCHAND BIT 0 DECSEL EXTCLK: External clock select. 1 = logic-level clock supplied on OSCIN. 0 = crystal or resonator connected between OSCIN and OSCOUT (default). CLKDIV1:CLKDIV0: Clock divider ratio (EX clock : ADC sample clock). 00 = 1:2 clock divider. 01 = 1:3 clock divider. 10 = 1:4 clock divider. 11 = 1:6 clock divider (default). PD: Power-down analog circuitry (reference and SPI interface remains active). 1 = low-power mode. 0 = normal operation (default). PD_: ADC power-down for each channel (A, B, C, and D). 1 = powers down analog signal path. 0 = normal operation (default). PDDAC< 7>: DAC power-down. 1 = fine DAC buffer powered down. 0 = normal operation (default). PDOSC: Oscillator power-down. 1 = oscillator powered down (disconnects EX clock in EX clock mode). 0 = normal operation (default). 24BIT: ADC output data format. 1 = ADC data output as 24 bits. 0 = ADC data output as 16 bits (default). Use the 24-bit ADC output in conjunction with external digital filtering to improve signal-to-noise ratio. ______________________________________________________________________________________ 19 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 SCHAN_: Automatic ADC result output for each channel (A, B, C, and D). 1 = ADC channel data is output on DOUT each time a new result is valid in the sequence, A, B, C, and D. 0 = ADC data is not presented automatically for this channel (default). When SCHAN_ = 1, the selected ADC channel data is automatically presented on DOUT each time E OC asserts low in the sequence A, B, C, and D with the unselected channels omitted. The data transitions on the rising edge of SCLK. Force CS low to initiate transmission. CS can go high between results. The MSB of the first selected ADC channel outputs immediately after the falling edge of EOC. EOC goes high after the last bit of the selected channels clocks out or one clock cycle before the next result is ready. Insufficient SCLK pulses result in truncated data. Extra clock pulses give an undefined output. In scan mode, keep DIN high or write data to the MAX11043 as usual. In scan mode, the MAX11043 ignores requests for data reads. DECSEL: Decimate select. 1 = decimate by 12. 0 = decimate by 24 (default). Set DECSEL high to decimate the ADC result by 12, doubling the number of samples. The SPI interface is limited to 40Mbps. Fine DAC Register (09h) BIT 15 X BIT 14 X BIT 13 X BIT 12 X BIT 11 DAC11 BIT 10 DAC10 BIT 9 DAC9 BIT 8 DAC8 BIT 7 DAC7 BIT 6 DAC6 BIT 5 DAC5 BIT 4 DAC4 BIT 3 DAC3 BIT 2 DAC2 BIT 1 DAC1 BIT 0 DAC0 X: Don’t-care bits. DAC_: Contains current fine DAC output value. When using the DACSTEP input to change the DAC value, this register updates to the new value on the next rising edge of the system clock following the rising edge of DACSTEP. The power-on default is 0. DACSTEP Register (0Ah) BIT 15 X BIT 14 X BIT 13 X BIT 12 X BIT 11 DACSTEP11 BIT 10 DACSTEP10 BIT 9 DACSTEP9 BIT 8 DACSTEP8 BIT 7 DACSTEP7 BIT 6 DACSTEP6 BIT 5 DACSTEP5 BIT 4 DACSTEP4 BIT 3 DACSTEP3 BIT 2 DACSTEP2 BIT 1 DACSTEP1 BIT 0 DACSTEP0 X: Don’t-care bits. DACSTEP11:DACSTEP0: Provides the size of the DAC step. The value is positive only and the UP/DWN input is used to set the direction. The value in the fine DAC register updates on the next rising edge of the system clock following the rising edge of the DACSTEP input. The power-on default is 0. Coarse DACH/DACL Register (0Bh) BIT 15 DACH7 BIT 14 DACH6 BIT 13 DACH5 BIT 12 DACH4 BIT 11 DACH3 BIT 10 DACH2 BIT 9 DACH1 BIT 8 DACH0 BIT 7 DACL7 BIT 6 DACL6 BIT 5 DACL5 BIT 4 DACL4 BIT 3 DACL3 BIT 2 DACL2 BIT 1 DACL1 BIT 0 DACL0 DACH7:DACH0: High coarse DAC value. DACL7:DACL0: Low coarse DAC value. 20 Coarse DAC sets high and low references for the fine DAC. The power-on default is 0. ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 CONFIG_ Register (0Ch–0Fh) BIT 15 X BIT 14 X BIT 13 X BIT 12 BDAC3 BIT 11 BDAC2 BIT 10 BDAC1 BIT 9 BDAC0 BIT 8 DIFF BIT 7 EQ BIT 6 MODG1 BIT 5 MODG0 BIT 4 PDPGA BIT 3 FILT BIT 2 PGAG BIT 1 ENBIASP BIT 0 ENBIASN This register sets the input gain of each ADC channel and selects one of the default filters or EQ function. X: Don’t-care bits. BDAC3:BDAC0: Sets the input bias voltage for AC-coupled signals when ENBIAS_ is set to 1. 0000 = 33% of AVDD. 0001 = 35% of AVDD. 0010 = 38% of AVDD. 0011 = 40% of AVDD. 0100 = 42% of AVDD. 0101 = 44% of AVDD. 0110 = 46% of AVDD. 0111 = 48% of AVDD. 1000 = 50% of AVDD. 1001 = 52% of AVDD. 1010 = 54% of AVDD. 1011 = 56% of AVDD. 1100 = 58% of AVDD. 1101 = 60% of AVDD. 1110 = 62% of AVDD. 1111 = 65% of AVDD. DIFF: Input mode select bit. 1 = normal operation in all modes. 0 = use for a 2x input signal range in LP, gain = 1 mode. Note that THD degrades. EQ: EQ function. 1 = analog EQ enabled. 0 = analog EQ disabled (default). MODG1:MODG0: ADC modulator gain. 00 = 1 (default). 01 = 2. 10 = 4. 11 = 4. PDPGA: PGA power-down control. 1 = PGA powered down, gain = 1. 0 = PGA powered, PGA gain set by PGAG (default). FILT: Programmable filter select. 1 = use preprogrammed LP filter. 0 = use preprogrammed EQ filter (default). PGAG: High PGA gain setting. 1 = PGA, gain = 16. 0 = PGA, gain = 8 (default). ENBIASP: Positive input bias enable. Bias voltage set by BDAC3:BDAC0. 1 = selfbiasing enabled. 0 = selfbiasing disabled (default). ENBIASN: Negative input bias enable. Bias voltage set by BDAC3:BDAC0. 1 = selfbiasing enabled. 0 = selfbiasing disabled (default). ______________________________________________________________________________________ 21 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 Reference Register (10h) BIT 15 0 BIT 14 0 BIT 13 0 BIT 12 PURGE4 BIT 11 PURGE3 BIT 10 PURGE2 BIT 9 PURGE1 BIT 8 PURGE0 BIT 7 EXTREF BIT 6 EXBUFA BIT 5 EXBUFB BIT 4 EXBUFC BIT 3 EXBUFD BIT 2 EXBUFDAC BIT 1 EXBUFDACH BIT 0 EXBUFDACL Reserved: Reserved. Set to 0. PURGE4:PURGE0: Filter purge interval. Straight binary. 00h = first available sample is presented (default). 1Fh = 31 results are discarded. Digital filters retain a history of past input data. At power-up and when changing the signal path, old data requires purging before new output data is valid. PURGE4(MSB):PURGE0 determine the number of samples to discard before a new result is valid. Each time CONVRUN is taken high, N results are discarded before EOC asserts low (where N is the decimal equivalent of the binary representation of PURGE4:PURGE0). Results prior to N+1 are overwritten. EOC asserts for results N+1, N+2, N+3, etc., as long as CONVRUN remains high. Taking CONVRUN low and then high invokes another purge. Purging of the sinc 5 filter requires five readings if DECSEL (configuration register 08h, bit 0) = 1 and three readings if DECSEL = 0. The minimum total purge interval of the seven cascaded filters is one reading if not used. If the filters are used, the total latency of the programmable filters is the sum of the latency caused by each stage. Set the appropriate delay for filter purging and settling time. EXTREF: Main reference selection. 1 = external reference applied to REFBP, internal reference buffer powered down. 0 = internal reference, bypass REFBP with 1µF to AGND (default). EXBUF_: ADC reference selection for each channel. 1 = external reference applied to REF_ input, internal switch open. 0 = using main internal reference, bypass REF_ with 1µF to AGND (default). EXBUFDAC: Coarse DAC reference selection. 1 = external reference applied to REFDAC, internal reference buffer powered down. 0 = using main internal reference, bypass REFDAC with 1µF to AGND (default). EXBUFDACH: High reference for fine DAC. 1 = external reference applied to REFDACH, internal reference buffer powered down. 0 = using high output from coarse DAC as reference, bypass REFDACH with 1µF to AGND (default). EXBUFDACL: Low reference for fine DAC. 1 = external reference applied to REFDACL, internal reference buffer powered down. 0 = using low output from coarse DAC as reference, bypass REFDACL with 1µF to AGND (default). 22 ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Fine Gain A/B/C/D Registers (11h–14h) Fine gain for each channel is a two’s complement binary value (8192 x desired gain). FINE GAIN REGISTER 7FFFh 4000h 2001h 2000h 1FFFh 1000h 0800h GAIN (4 – 1/8192) 2 8193/8192 1 (default) 8191/8192 0.5 0.25 MAX11043 Filter Coefficient Address Register (15h) BIT 7 CHAN1 BIT 6 CHAN0 BIT 5 ADR5 BIT 4 ADR4 BIT 3 ADR3 BIT 2 ADR2 BIT 1 ADR1 BIT 0 ADR0 CHAN_: Channel selection. 00 = channel A (default). 01 = channel B. 10 = channel C. 11 = channel D. ADR5:ADR0: Address pointer for C-RAM containing filter coefficients (default = 0). Filter Coefficient Data Out Register (16h) This is a 32-bit register that contains the data from a C-RAM read operation. Filter Coefficient Data In Register (17h) This is a 32-bit register that contains the data for a C-RAM write operation. Default = 0. ______________________________________________________________________________________ 23 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 Flash Mode Register (18h) BIT 7 FM2 (Flashmode2) BIT 6 FM1 (Flashmode1) BIT 5 FM0 (Flashmode0) BIT 4 0 BIT 3 X BIT 2 X BIT 1 X BIT 0 Flash busy (read only) Write allowed only if flash busy bit is zero. FM2:FM0: Flash operation (default 0). 000 = no operation. 001 = write data in flash data in register to flash. 010 = erase data in the selected page. 011 = mass erase the flash. 100 = no operation. 101 = read data from flash into data out register. 110 = transfer data from flash to C-RAM. 111 = no operation. Reserved: Reserved. Set to 0. X: Don’t-care bits. Flash busy: Flash busy flag. 1 = flash busy. 0 = flash ready. Flash Address Register (19h) BIT 15 X BIT 14 X BIT 13 X BIT 12 X BIT 11 X BIT 10 PAGE2 BIT 9 PAGE1 BIT 8 PAGE0 BIT 7 ADR7 BIT 6 ADR6 BIT 5 ADR5 BIT 4 ADR5 BIT 3 ADR3 BIT 2 ADR2 BIT 1 ADR1 BIT 0 ADR0 Write allowed only if flash busy bit is zero (18h bit 0 or status register) (default = 0). X : Don’t-care bits. PAGE2:PAGE0: Page selection. 000 = page 0 (default). 001 = page 1. 010 = page 2. 011 = page 3. 100 = page 4. 101 = page 5. 110 = page 6. 111 = page 7. ADR7:ADR0: Address pointer flash word containing filter coefficients (default = 0). 24 ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Flash Data In Register (1Ah) Write allowed only if flash busy bit is zero. This is a 16-bit register that contains the data for a flash write operation. Default = 0. Flash Data Out Register (1Bh) This is a read-only register. Data is valid only if flash busy is zero. This is a 16-bit register that contains the data for a flash read operation. pensate for manufacturing variations in the analog portion of the IC. These coefficients vary depending on the PGA gain setting and if the analog equalizer is used. To allow for these different modes, several sets of stage 1 coefficients are stored in flash. Bits in the CONGIF register select which set of stage 1 coefficients are used. Table 3 shows the C-RAM addresses used for each CONFIG setting. To maintain optimum performance when using custom filters, copy the trim data from flash pages zero and one to the corresponding locations in flash pages two and three or to C-RAM when writing directly to C-RAM. For custom filters, use stages 2–7 first, and only change the stage 1 coefficients when all seven stages require customization. To load the coefficients directly to C-RAM, create a 32bit data word by concatenating the data in adjacent flash locations as shown in Table 3. The C-RAM addresses below are for channel A; for channel B add 40h, for channel C add 80h, and for channel D add C0h. Multiple addresses exist for some stage 1 filter coefficients as shown in Table 4. The address accessed by the filter depends on the configuration bits as shown in Table 3. MAX11043 Flash and C-RAM Register Map The flash memory consists of 2048 words by 16 bits. The 3 MSBs of the flash address select one of eight pages of 256 words each. Page zero contains the default filter coefficients for channels A and B. Page one contains the default filter coefficients for channels C and D. Use pages two and three for the coefficients of custom filters. When the first word on page two contains a nonzero value, the MAX11043 loads these pages into C-RAM at power-up instead of the default values from pages zero and one. Flash pages zero and one include trim data. Unique trim data optimizes the performance of each MAX11043. Coefficients for the stage 1 filters and ADC gain are individually programmed at the factory to com- Table 3. Stage 1 Filter Selection STAGE 1 COEFFICIENT ADDRESS EQ filter stage 1 (C-RAM address 03h–05h) LP filter for ADC gain of 1, 2, and 4; stage 1 (C-RAM address 1Dh–1Fh) LP filter for ADC gain of 8; stage 1 (C-RAM address 3Dh–3Fh) LP filter for ADC gain of 16; stage 1 (C-RAM address 23h–25h) EQ 1 X 0 0 PDPGA 0 1 0 0 MODG XX XX 00 XX PGAG X X 0 1 Table 4. C-RAM and Flash Memory Map for Channel A Flash Page One* C-RAM ADDRESS 00h 01h 02h 03h FLASH ADDRESS 00h 01h* 02h 03h 04h 05h 06h* 07h* Not used — EQ filter coefficient -A2 for filter stage 1 MSB FOR C-RAM — EQ gain trim for gain = 1 — User trim for EQ gain, default = 2000h — Not used — EQ filter gain for filter stage 1 — Not used — Not used — LSB FOR C-RAM *For channel B add 80h, for channel C add 100h, and for channel D add 180h. To write to pages two and three of flash, add 200h to these values. ______________________________________________________________________________________ 25 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 Table 4. C-RAM and Flash Memory Map (continued) C-RAM ADDRESS 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h FLASH ADDRESS 08h 09h* 0Ah* 0Bh* 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh MSB FOR C-RAM — EQ filter coefficient -A3 for filter stage 1 — EQ filter coefficient B2 for filter stage 1 — EQ filter coefficient -A2 for filter stage 2 — EQ filter coefficient -A3 for filter stage 2 — EQ filter coefficient B2 for filter stage 2 — EQ filter coefficient -A2 for filter stage 3 — EQ filter coefficient -A3 for filter stage 3 — EQ filter coefficient B2 for filter stage 3 — EQ filter coefficient -A2 for filter stage 4 — EQ filter coefficient -A3 for filter stage 4 — EQ filter coefficient B2 for filter stage 4 — EQ filter coefficient -A2 for filter stage 5 — EQ filter coefficient -A3 for filter stage 5 — EQ filter coefficient B2 for filter stage 5 — EQ filter coefficient -A2 for filter stage 6 — EQ filter coefficient -A3 for filter stage 6 — EQ filter coefficient B2 for filter stage 6 — EQ filter coefficient -A2 for filter stage 7 — EQ filter coefficient -A3 for filter stage 7 Not used — Not used — EQ filter coefficient B3 and rectify bit for filter stage 6 — EQ filter gain for filter stage 7 — Not used — EQ filter coefficient B3 and rectify bit for filter stage 5 — EQ filter gain for filter stage 6 — Not used — EQ filter coefficient B3 and rectify bit for filter stage 4 — EQ filter gain for filter stage 5 — Not used — EQ filter coefficient B3 and rectify bit for filter stage 3 — EQ filter gain for filter stage 4 — Not used — EQ filter coefficient B3 and rectify bit for filter stage 2 — EQ filter gain for filter stage 3 — Not used — EQ filter coefficient B3 and rectify bit for filter stage 1 — EQ filter gain for filter stage 2 — LSB FOR C-RAM 26 ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Table 4. C-RAM and Flash Memory Map (continued) C-RAM ADDRESS 17h 18h 19h 1Ah 1Bh 1Ch FLASH ADDRESS 2Eh 2Fh 30h 31h* 32h 33h* 34h 35h* 36h 37h* 38h 39h* 3Ah* 1Dh 3Bh* 3Ch 1Eh 3Dh* 3Eh* 1Fh 3Fh* 20h 21h 22h 40h 41h* 42h 43h 44h 45h 46h* 23h 47h* 48h 24h 49h* 4Ah* 25h 4Bh* 26h 4Ch 4Dh LP filter coefficient B2 for filter stage 1, gain = 16 — LP filter coefficient -A2 for filter stage 2 — LP filter gain for filter stage 2 — Not used — LP filter coefficient -A2 for filter stage 1, gain = 16 — LP filter coefficient -A3 for filter stage 1, gain = 16 — Not used — LP filter coefficient B3 and rectify bit for filter stage 1, gain = 16 LP filter coefficient B2 for filter stage 1, gain = 1, 2, or 4 — ADC gain trim for gain = 16 — User trim for ADC gain, default = 2000h — Not used — LP filter gain for filter stage 1, gain = 16 — Not used — Not used — — MSB FOR C-RAM — EQ filter coefficient B2 for filter stage 7 — ADC gain trim for gain = 1 — ADC gain trim for gain = 2 — ADC gain trim for gain = 4 — EQ gain trim for gain = 2 — EQ gain trim for gain = 4 — LP filter coefficient -A2 for filter stage 1, gain = 1, 2, or 4 — LP filter coefficient -A3 for filter stage 1, gain = 1, 2, or 4 — Not used — LP filter coefficient B3 and rectify bit for filter stage 1, gain = 1, 2, or 4 Not used — LP filter gain for filter stage 1, gain = 1, 2, or 4 — Not used — Not used — Not used — Not used — LSB FOR C-RAM EQ filter coefficient B3 and rectify bit for filter stage 7 — MAX11043 27 ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 Table 4. C-RAM and Flash Memory Map (continued) C-RAM ADDRESS 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah FLASH ADDRESS 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h* Not used — ADC gain trim for gain = 8 Not used — Not used — Not used — MSB FOR C-RAM — LP filter coefficient -A3 for filter stage 2 — LP filter coefficient B2 for filter stage 2 — LP filter coefficient -A2 for filter stage 3 — LP filter coefficient -A3 for filter stage 3 — LP filter coefficient B2 for filter stage 3 — LP filter coefficient -A2 for filter stage 4 — LP filter coefficient -A3 for filter stage 4 — LP filter coefficient B2 for filter stage 4 — LP filter coefficient -A2 for filter stage 5 — LP filter coefficient -A3 for filter stage 5 — LP filter coefficient B2 for filter stage 5 — LP filter coefficient -A2 for filter stage 6 — LP filter coefficient -A3 for filter stage 6 — LP filter coefficient B2 for filter stage 6 — LP filter coefficient -A2 for filter stage 7 — LP filter coefficient -A3 for filter stage 7 — LP filter coefficient B2 for filter stage 7 — Not used — Not used — LP filter coefficient B3 and rectify bit for filter stage 7 — Not used — LP filter coefficient B3 and rectify bit for filter stage 6 — LP filter gain for filter stage 7 — Not used — LP filter coefficient B3 and rectify bit for filter stage 5 — LP filter gain for filter stage 6 — Not used — LP filter coefficient B3 and rectify bit for filter stage 4 — LP filter gain for filter stage 5 — Not used — LP filter coefficient B3 and rectify bit for filter stage 3 — LP filter gain for filter stage 4 — Not used — LP filter coefficient B3 and rectify bit for filter stage 2 — LP filter gain for filter stage 3 — LSB FOR C-RAM 28 ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Table 4. C-RAM and Flash Memory Map (continued) C-RAM ADDRESS 3Bh 3Ch FLASH ADDRESS 76h 77h* 78h 79h* 7Ah* 3Dh 7Bh* 7Ch 3Eh 7Dh* 7Eh* 3Fh 7Fh* LP filter coefficient B2 for filter stage 1, gain = 8 — MSB FOR C-RAM — ADC gain trim for gain = 32 — ADC gain trim for gain = 64 — LP filter coefficient -A2 for filter stage 1, gain = 8 — LP filter coefficient -A3 for filter stage 1, gain = 8 — Not used — LP filter coefficient B3 and rectify bit for filter stage 1, gain = 8 Not used — LP filter gain for filter stage 1, gain = 8 — Not used — LSB FOR C-RAM MAX11043 *Recommended copy to C-RAM or flash for optimum custom-filter performance. Flash Erase and Programming When erasing or programming the flash, maintain the system clock between 14MHz and 27MHz to satisfy flash timing requirements and ensure CONVRUN = 0. The system clock used for all digital timing is twice the ADC sample clock (2 x EX clock/divider). Always erase the flash page before writing new data. The procedure for flash mass erase is as follows: 1) Read the flash mode register (18h); proceed when the LSB is zero. 2) Write 0000h to the flash address register (19h). 3) Write 60h to the flash mode register (18h). 4) Wait 200ms for erase to complete. 5) FFFFh = flash erased state. The procedure for flash single page erase is as follows: 1) Read the flash mode register (18h); proceed when the LSB is zero. 2) Write page address, set word address to 00h in the flash address register (19h). 3) Write 40h to the flash mode register (18h). 4) Wait 20ms for page erase to complete. 5) FFFFh = flash erased state. The procedure for flash single word write is as follows: 1) Read the flash mode register (18h); proceed when the LSB is zero. 2) Write page and word address to the flash address register (19h). 3) Write the data to the flash data in register (1Ah). 4) Write 20h to the flash mode register (18h). 5) Read the flash mode register (18h); proceed when the LSB is zero (approx. 40µs). The procedure for flash single word read is as follows: 1) Read the flash mode register (18h); proceed when the LSB is zero. 2) Write page and word address to the flash address register (19h). 3) Write A0h to the flash mode register (18h). 4) Read the flash mode register (18h); proceed when the LSB is zero (approx. 1µs). 5) Read the data from the flash data out register (1Bh). The procedure for flash to C-RAM transfer is as follows: 1) Read the flash mode register (18h); proceed when the LSB is zero. 2) Write C0h to the flash mode register (18h). 3) Read the flash mode register (18h); proceed when the LSB is zero (approx. 1ms). 4) The content of flash is transferred to C-RAM. ______________________________________________________________________________________ 29 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 Digital Filter Coefficients Table 5. Typical Filter Coefficients Register Map (LP Filter Channel A, Stage 3) COEFFICIENT FLASH ADDRESS 52h 53h 54h 55h 56h 57h Gain for channel A, stage 3 A2 coefficient for channel A, stage 3 Not used; set to 0 A3 coefficient for channel A, stage 3 B3 coefficient and rectify flag (RECT) for channel A, stage 3 B2 coefficient for channel A, stage 3 FUNCTION Format for Filter Stage Gain (52h) BIT 15 X BIT 14 GAIN2 BIT 13 GAIN1 BIT 12 GAIN0 BIT 11 X BIT 10 X BIT 9 X BIT 8 X BIT 7 X BIT 6 X BIT 5 X BIT 4 X BIT 3 X BIT 2 X BIT 1 X BIT 0 X X: Don’t-care bit. Not used. GAIN2:GAIN0: Filter gain. 000 = = 16. 001 = 22 = 4. 010 = 20 = 1. 011 = 2-2 = 0.25. 24 100 = 2-4 = 0.0625. 101 = 2-6 = 0.015625. 110 = 2-8 = 0.00390625. 111 = 2-10 = 0.0009765625. X: Don’t-care bits. Not used. 30 ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC A2, A3, and B2 Filter Coefficient Format (52h, 54h, 56h) Filter coefficients A2, A3, and B2 are stored as 16-bit two’s complement values in the -4 to (4 - 2-13) range. The transfer function equation is as follows: A2 = int (N x 213) where N is the decimal coefficient value. The following are two examples of the transfer function equation: Example 1: N = 2.381 A2 = int (2.381 x 213) A2 = int (19505.152) A2 = 19505 = 4C31h (two’s complement) Example 2: N = -2.381 A2 = int (-2.381 x 213) A2 = int (-19505.152) A2 = -19505 = B3CFh (two’s complement) MAX11043 B3 Coefficient (56h) BIT 15 B31 BIT 14 B30 BIT 13 RECT BIT 12 X BIT 11 X BIT 10 X BIT 9 X BIT 8 X BIT 7 X BIT 6 X BIT 5 X BIT 4 X BIT 3 X BIT 2 X BIT 1 X BIT 0 X B31:B30: Filter coefficient B3. 11 = -1. 00 = 0. 01 = 1. 10 = 0. X: Don’t-care bit. Not used. RECT: Rectify bit. 0 = bipolar output. 1 = output rectified. All samples positive. X: Don’t-care bits. Not used. Power Supplies, Layout, and Bypassing Considerations For best performance, use PCBs with ground planes. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital lines parallel to one another (especially clock lines), and do not run digital lines underneath the MAX11043 package. Use a single-point analog ground (star ground point) at AGND, separate from the logic ground. Connect all other analog grounds and DGND to this star ground point. Do not connect other digital system grounds to this single-point analog ground. The ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. Bypass all supplies to ground with high quality capacitors as close as possible to the device. ______________________________________________________________________________________ 31 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC MAX11043 Typical Operating Circuit TO DIGITAL SUPPLY AINAP DVDD *SEE NOTE ECHOAINAN REFA AVDD RADAR FRONT END *SEE NOTE TO ANALOG SUPPLY ECHO+ ECHO+ AINBP AGND AINBN REFB ECHO- MAX11043 CS UP/DWN DACSTEP CONVRUN EOC SHDN SCLK DOUT DIN OSCIN ECHO+ AINCP AINCN REFC DSP *SEE NOTE ECHO- ECHO+ AINDP AINDN DGND *SEE NOTE ECHOREFD DVREG AOUT REFBP EXT REF REFDAC REFDACH REFDACL *NOTE: CONNECT TO AGND FOR SINGLE-ENDED OPERATION. Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 40 TQFN-EP PACKAGE CODE T4066+5 OUTLINE NO. 21-0141 LAND PATTERN NO. 90-0055 32 ______________________________________________________________________________________ 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Revision History REVISION NUMBER 0 1 2 REVISION DATE 8/08 3/10 3/11 Initial release Updated Ordering Information with automotive grade information and clarified/amended data sheet Updated the Flash Erase and Programming section DESCRIPTION PAGES CHANGED — 1, 2–7, 12–15, 21, 25, 30 29 MAX11043 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 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