MAX11049

19-5106; Rev 0; 12/09 KIT ATION EVALU ABLE AVAIL 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs General Description Features o o o o o o o o o o o 4-/6-/8-Channel 16-Bit ADC Single Analog and Digital Supply High-Impedance Inputs Up to 1GΩ On-Chip T/H Circuit for Each Channel Fast 3µs Conversion Time High Throughput: 250ksps for All 8 Channels 16-Bit, High-Speed, Parallel Interface Internal Clocked Conversions 10ns Aperture Delay 100ps Channel-to-Channel T/H Matching Low Drift, Accurate 4.096V Internal Reference Providing an Input Range of 0 to 5V o External Reference Range of 3.0V to 4.25V, Allowing Full-Scale Input Ranges of +3.7V to +5.2V o 56-Pin TQFN Package (8mm x 8mm) o Evaluation Kit Available MAX11047/MAX11048/MAX11049 The MAX11047/MAX11048/MAX11049 16-bit ADCs offer 4, 6, or 8 independent input channels. Featuring independent track and hold (T/H) and SAR circuitry, these parts provide simultaneous sampling at 250ksps for each channel. The MAX11047/MAX11048/MAX11049 accept a 0 to +5V input. All inputs are overrange protected with internal ±20mA input clamps providing overrange protection with a simple external resistor. Other features include a 4MHz T/H input bandwidth, internal clock, and internal or external reference. A 20MHz, 16-bit, bidirectional, parallel interface provides the conversion results and accepts digital configuration inputs. The MAX11047/MAX11048/MAX11049 operate with a 4.75V to 5.25V analog supply and a separate flexible 2.7V to 5.25V digital supply for interfacing with the host without a level shifter. The MAX11047/MAX11048/MAX11049 are available in a 56-pin TQFN package and operate over the extended -40°C to +85°C temperature range. Applications Automatic Test Equipment Power-Factor Monitoring and Correction Power-Grid Protection Multiphase Motor Control Vibration and Waveform Analysis Ordering Information PART MAX11047ETN+ MAX11048ETN+ MAX11049ETN+ PIN-PACKAGE 56 TQFN-EP* 56 TQFN-EP* 56 TQFN-EP* CHANNELS 4 6 8 Functional Diagram AVDD DVDD DB15 Note: All devices are specified over the -40°C to +85°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Pin Configuration AGNDS AGND AGND REFIO AVDD AVDD RDC CH6 CH5 CH4 CH3 CH2 42 41 40 39 38 37 36 35 34 33 32 31 30 29 RDC 43 28 RDC 27 AGNDS 26 CH0 25 AGND 24 AVDD CH1 23 AGNDS 22 RDC 21 DGND 20 DVDD 19 SHDN 18 CONVST 17 EOC *EP 16 DB0 15 DB1 1 DB13 2 DB12 3 DB11 4 DB10 5 DB9 6 DB8 7 DGND 8 DVDD 9 DB7 10 11 12 13 14 DB6 DB5 DB4 DB3 DB2 TOP VIEW BIDIRECTIONAL DRIVERS CH0 8 x 16-BIT REGISTERS CLAMP S/H 16-BIT ADC DB4 DB3 DB0 AGNDS 44 CH7 45 AGND 46 AVDD 47 AGNDS 48 RDC 49 CH7 CLAMP S/H 16-BIT ADC AGNDS CONFIGURATION REGISTERS WR RD CS CONVST SHDN EOC DGND 50 DVDD 51 WR 52 CS 53 RD 54 DB15 55 DB14 56 MAX11047 MAX11048 MAX11049 AGND MAX11047 MAX11048 MAX11049 INT REF BANDGAP REFERENCE REF BUF EXT REF INTERFACE AND CONTROL + RDC DGND REFIO TQFN ____________________________ Maxim Integrated Products AGNDS 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs MAX11047/MAX11048/MAX11049 ABSOLUTE MAXIMUM RATINGS AVDD to AGND ........................................................-0.3V to +6V DVDD to AGND and DGND .....................................-0.3V to +6V DGND to AGND.....................................................-0.3V to +0.3V AGNDS to AGND...................................................-0.3V to +0.3V CH0–CH7 to AGND ...............................................-2.5V to +7.5V REFIO, RDC to AGND ..................................-0.3V to the lower of (AVDD + 0.3V) and +6V EOC, WR, RD, CS, CONVST to AGND.........-0.3V to the lower of (DVDD + 0.3V) and +6V DB0–DB15 to AGND ....................................-0.3V to the lower of (DVDD + 0.3V) and +6V Maximum Current into Any Pin Except AVDD, DVDD, AGND, DGND ...........................................................................±50mA Continuous Power Dissipation (TA = +70°C) 56-Pin TQFN (derated 36mW/°C above +70°C) ........2222mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = 4.75V to 5.25V, DVDD = +2.7V to 5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33μF, CREFIO = 0.1μF, CAVDD = 4 x 0.1μF || 10μF, CDVDD = 3 x 0.1μF || 10μF; all digital inputs at DVDD or DGND, unless otherwise noted. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER STATIC PERFORMANCE (Note 1) Resolution Integral Nonlinearity Integral Nonlinearity Differential Nonlinearity Differential Nonlinearity No Missing Codes Offset Error Offset Temperature Coefficient Channel Offset Matching Gain Error Positive Full-Scale Error Positive Full-Scale Error Matching Channel Gain-Error Matching Gain Temperature Coefficient DYNAMIC PERFORMANCE (Note 4) Signal-to-Noise Ratio Signal-to-Noise and Distortion Ratio Spurious-Free Dynamic Range Total Harmonic Distortion Channel-to-Channel Crosstalk ANALOG INPUTS (CH0–CH7) Input Voltage Range Input Leakage Current (Note 6) 0 -1 1.22 x VREFIO +1 V μA SNR SINAD SFDR THD fIN = 10kHz, full-scale input fIN = 10kHz, full-scale input fIN = 10kHz, full-scale input fIN = 10kHz, full-scale input fIN = 60Hz, full scale and ground on adjacent channel (Note 5) 91 90.5 95 92.3 92 106 -105 -126 -95 -100 dB dB dB dB dB Between all channels ±0.8 N INL INL DNL DNL (Note 2) (Note 3) (Note 2) (Note 3) 16 ±0.002 ±2.4 ±0.01 ±0.03 ±0.02 ±0.02 ±0.03 ±0.01 > -1 16 -2 ±0.6 ±0.8 ±0.6 ±0.7 < +1.3 +2 Bits LSB LSB LSB LSB Bits %FSR μV/°C %FSR %FSR %FSR %FSR %FSR ppm/°C SYMBOL CONDITIONS MIN TYP MAX UNITS 2 _______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs ELECTRICAL CHARACTERISTICS (continued) (AVDD = 4.75V to 5.25V, DVDD = +2.7V to 5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33μF, CREFIO = 0.1μF, CAVDD = 4 x 0.1μF || 10μF, CDVDD = 3 x 0.1μF || 10μF; all digital inputs at DVDD or DGND, unless otherwise noted. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Input Capacitance Input-Clamp Protection Current TRACK AND HOLD Throughput Rate Acquisition Time Full-Power Bandwidth Aperture Delay Aperture-Delay Matching Aperture Jitter INTERNAL REFERENCE REFIO Voltage REFIO Temperature Coefficient EXTERNAL REFERENCE Input Current REF Voltage Input Range REF Input Capacitance DIGITAL INPUTS (DB0–DB15, RD, WR, CS, CONVST) Input-Voltage High Input-Voltage Low Input Capacitance Input Current DIGITAL OUTPUTS (DB0–DB15, EOC) Output-Voltage High Output-Voltage Low Three-State Leakage Current Three-State Output Capacitance POWER SUPPLIES (MAX11047) Analog Supply Voltage Digital Supply Voltage Analog Supply Current Digital Supply Current Shutdown Current Shutdown Current Power-Supply Rejection Ratio PSRR AVDD DVDD IAVDD IDVDD VDVDD = 3.3V (Note 7) For DVDD For AVDD VAVDD = 4.9V to 5.1V (Note 8) ±0.5 4.75 2.70 5.25 5.25 32 5.7 10 12 V V mA mA μA μA LSB VOH VOL ISOURCE = 1.2mA ISINK = 1mA DB0–DB15, VRD ≥ VIH or VCS ≥ VIH DB0–DB15, VRD ≥ VIH or VCS ≥ VIH 15 VDVDD 0.4 0.4 10 V V μA pF VIH VIL CIN IIN VIN = 0 or VDVDD VDVDD = 2.7V to 5.25V VDVDD = 2.7V to 5.25V 10 ±10 2 0.8 V V pF μA VREF -10 3.00 15 +10 4.25 μA V pF VREF 4.073 4.096 ±5 4.119 V ppm/°C tACQ -3dB point -0.1dB point Per channel, 8 channels in 4μs 1 4 > 0.2 10 100 50 250 ksps μs MHz ns ps psRMS Each input simultaneously -20 SYMBOL CONDITIONS MIN TYP 15 +20 MAX UNITS pF mA MAX11047/MAX11048/MAX11049 _______________________________________________________________________________________ 3 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs MAX11047/MAX11048/MAX11049 ELECTRICAL CHARACTERISTICS (continued) (AVDD = 4.75V to 5.25V, DVDD = +2.7V to 5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33μF, CREFIO = 0.1μF, CAVDD = 4 x 0.1μF || 10μF, CDVDD = 3 x 0.1μF || 10μF; all digital inputs at DVDD or DGND, unless otherwise noted. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER POWER SUPPLIES (MAX11048) Analog Supply Voltage Digital Supply Voltage Analog Supply Current Digital Supply Current Shutdown Current Shutdown Current Power-Supply Rejection Ratio POWER SUPPLIES (MAX11049) Analog Supply Voltage Digital Supply Voltage Analog Supply Current Digital Supply Current Shutdown Current Shutdown Current Power-Supply Rejection Ratio TIMING CHARACTERISTICS (Note 7) CONVST Rise to EOC Fall Acquisition Time CS Rise to CONVST Rise CONVST Rise to EOC Rise EOC Fall to CONVST Fall CONVST Low Time CS Fall to WR Fall WR Low Time CS Rise to WR Rise Input Data Setup Time Input Data Hold Time CS Fall to RD Fall RD Low Time RD Rise to CS Rise RD High Time RD Fall to Data Valid RD Rise to Data Hold Time tCON tACQ tQ t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 (Note 10) 5 CONVST mode B0 = 0 only (Note 10) CONVST mode B0 = 1 only 0 20 0 20 0 10 0 0 30 0 10 35 Sample quiet time (Note 9) Conversion time (Note 9) 1 500 65 140 3 μs μs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns PSRR AVDD DVDD IAVDD IDVDD VDVDD = 3.3V (Note 7) For DVDD For AVDD VAVDD = 4.9V to 5.1V (Note 8) ±0.5 4.75 2.70 5.25 5.25 40 7.3 10 12 V V mA mA μA μA LSB PSRR AVDD DVDD IAVDD IDVDD VDVDD = 3.3V (Note 7) For DVDD For AVDD VAVDD = 4.9V to 5.1V (Note 8) ±0.5 4.75 2.70 5.25 5.25 36 6.5 10 12 V V mA mA μA μA LSB SYMBOL CONDITIONS MIN TYP MAX UNITS 4 _______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs ELECTRICAL CHARACTERISTICS (continued) (AVDD = 4.75V to 5.25V, DVDD = +2.7V to 5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33μF, CREFIO = 0.1μF, CAVDD = 4 x 0.1μF || 10μF, CDVDD = 3 x 0.1μF || 10μF; all digital inputs at DVDD or DGND, unless otherwise noted. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) Note 1: See the Definitions section at the end of the data sheet. Note 2: Guaranteed at 5V ≤ VAVDD ≤ 5.25V for+25°C ≤ TA ≤ +85°C. See the Input Range and Protection section and Typical Operating Characteristics. Note 3: TA = -40°C. Note 4: Dynamic performance is guaranteed at AVDD = 5.0V to 5.25V. See the Input Range and Protection section and the Typical Operating Characteristics. Note 5: Tested with alternating channels modulated at full scale and ground. Note 6: See the Input Range and Protection section. Note 7: CLOAD= 30pF on DB0–DB15 and EOC. Inputs (CH0–CH7) alternate between full scale and zero scale. fCONV = 250ksps. All data is read out. Note 8: Defined as the change in positive full scale caused by a ±2% variation in the nominal supply voltage. Note 9: It is recommended that RD, WR, and CS are kept high for the quiet time (tQ) and conversion time (tCON). Note 10: Guaranteed by design. MAX11047/MAX11048/MAX11049 Typical Operating Characteristics (AVDD = 5V, DVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) INTEGRAL NONLINEARITY (INL) vs. CODE MAX11047 toc01 DIFFERENTIAL NONLINEARITY (DNL) vs. CODE MAX11047 toc02 INL AND DNL vs. ANALOG SUPPLY VOLTAGE MAX INL MAX11047 toc03 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 8192 16384 24576 32768 -1.0 0 VAVDD = 5.0V VDVDD = 3.3V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V 40960 49152 57344 1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 VAVDD = 5.0V, VDVDD = 3.3V, fSAMPLE = 250ksps TA = +25°C, VRDC = 4.096V 1.5 1.0 INL AND DNL (LSB) 0.5 MAX DNL 0 MIN DNL -0.5 -1.0 -1.5 MIN INL 4.75 4.85 4.95 INL (LSB) VDVDD = 3.3V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V 8192 16384 24576 32768 40960 49152 57344 65536 65536 0 5.05 5.15 5.25 OUTPUT CODE (DECIMAL) OUTPUT CODE (DECIMAL) VAVDD (V) INL AND DNL vs. TEMPERATURE MAX11047 toc04 ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE TA = +25°C fSAMPLE = 250ksps MAX11049 STATIC MAX11049 CONVERTING MAX11047 toc05 1.5 1.0 INL AND DNL (LSB) 0.5 MAX INL 37 35 33 IAVDD (mA) 31 29 MAX DNL 0 -0.5 -1.0 -1.5 -40 -15 10 MIN INL VAVDD = 5.0V VDVDD = 3.3V fSAMPLE = 250ksps VRDC = 4.096V MAX11048 STATIC MAX11048 CONVERTING MAX11047 CONVERTING MAX11047 STATIC 4.75 4.85 4.95 5.05 5.15 5.25 MIN DNL 27 25 35 60 85 TEMPERATURE (°C) VAVDD (V) _______________________________________________________________________________________ 5 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs MAX11047/MAX11048/MAX11049 Typical Operating Characteristics (continued) (AVDD = 5V, DVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) ANALOG SUPPLY CURRENT vs. TEMPERATURE MAX11047 toc06 DIGITAL SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX11047 toc07 DIGITAL SUPPLY CURRENT vs. TEMPERATURE MAX11049 CONVERTING MAX11047 toc08 35 VAVDD = 5.0V fSAMPLE = 250ksps 12 10 8 IDVDD (mA) TA = +25°C fSAMPLE = 250ksps CDBxx = 15pF MAX11049 CONVERTING 7.2 6.0 4.8 MAX11049 CONVERTING IAVDD (mA) 31 MAX11049 STATIC MAX11048 CONVERTING 27 MAX11048 STATIC MAX11047 CONVERTING 23 -40 MAX11047 STATIC -15 10 35 60 6 4 2 0 MAX11047 CONVERTING 2.75 3.25 3.75 MAX11048 CONVERTING IDVDD (mA) 3.6 2.4 MAX11047 CONVERTING VDVDD = 3.3V fSAMPLE = 250ksps CDBxx = 15pF -40 -15 10 MAX11048 CONVERTING MAX11047/MAX11048/ MAX11049 STATIC 1.2 0 MAX11047/MAX11048/ MAX11049 STATIC 85 4.25 4.75 5.25 35 60 85 TEMPERATURE (°C) VDVDD (V) TEMPERATURE (°C) ANALOG AND DIGITAL SHUTDOWN CURRENT vs. TEMPERATURE MAX11047 toc09 ANALOG AND DIGITAL SHUTDOWN CURRENT vs. SUPPLY VOLTAGE MAX11047 toc9a INTERNAL REFERENCE VOLTAGES vs. SUPPLY VOLTAGE TA = +25°C 4.09515 4.09510 VREF (V) 4.09505 4.09500 4.09495 4.09490 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V) VREFIO MAX11047 toc10 5 4 3 2 1 0 -40 -15 10 VAVDD = 5.0V VDVDD = 3.3V IAVDD 5 TA = +25°C SHUTDOWN CURRENT (µA) 4 3 2 1 0 2.75 3.25 3.75 4.25 4.75 IDVDD IAVDD 4.09520 SHUTDOWN CURRENT (µA) VRDC IDVDD 35 60 85 5.25 TEMPERATURE (°C) AVDD OR VDVDD (V) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX11047 toc11 OFFSET ERROR AND OFFSET ERROR MATCHING vs. SUPPLY VOLTAGE MAX11047 toc12 OFFSET ERROR AND OFFSET ERROR MATCHING vs. TEMPERATURE VAVDD = 5.0V VREFIO = 4.096V OFFSET ERROR MATCHING 0.002 -0.002 OFFSET ERROR -0.006 -0.010 MAX11047 toc13 4.112 4.108 4.104 VREFIO (V) 4.100 4.096 4.092 4.088 4.084 4.080 0.010 TA = +25°C 0.006 ERRORS (%FS) OFFSET ERROR MATCHING 0.002 -0.002 OFFSET ERROR -0.006 -0.010 VAVDD = 5.0V 0.010 0.006 ERRORS (%FS) UPPER TYPICAL LIMIT LOWER TYPICAL LIMIT -40 -15 10 35 60 85 4.75 4.85 4.95 5.05 5.15 5.25 -40 -15 10 35 60 85 TEMPERATURE (°C) VAVDD (V) TEMPERATURE (°C) 6 _______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs Typical Operating Characteristics (continued) (AVDD = 5V, DVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) GAIN ERROR AND GAIN ERROR MATCHING vs. SUPPLY VOLTAGE MAX11047 toc14 MAX11047/MAX11048/MAX11049 GAIN ERROR AND GAIN ERROR MATCHING vs. TEMPERATURE MAX11047 toc15 FFT PLOT -20 MAGNITUDE (dB) -40 -60 -80 -100 fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VAVDD = 5.0V MAX11047 toc16 0.010 TA = +25°C 0.006 ERRORS (%FS) 0.002 -0.002 -0.006 -0.010 GAIN ERROR 0.010 0.006 ERRORS (%FS) 0.002 -0.002 -0.006 -0.010 0 VAVDD = 5.0V GAIN ERROR GAIN-ERROR MATCHING GAIN-ERROR MATCHING -120 -140 -40 -15 10 35 60 85 TEMPERATURE (°C) 4.75 4.85 4.95 5.05 5.15 5.25 0 25 50 75 100 125 VAVDD (V) FREQUENCY (kHz) TWO-TONE IMD PLOT MAX11047 toc17 SIGNAL-TO-NOISE RATIO (SNR) AND SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) vs. TEMPERATURE MAX11047 toc18 TOTAL HARMONIC DISTORTION vs. TEMPERATURE VAVDD = 5.0V fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS MAX11047 toc19 0 -20 MAGNITUDE (dB) -40 -60 -80 -100 -120 -140 fIN1 = 9834Hz fIN2 = 10384Hz fSAMPLE = 250ksps TA = +25°C VAVDD = 5.0V VRDC = 4.096V VIN = -0.01dBFS 93.0 92.5 SNR AND SINAD (dB) 92.0 SNR -105.0 -105.5 -106.0 THD (dB) -106.5 -107.0 -107.5 -108.0 91.5 91.0 90.5 90.0 VAVDD = 5.0V fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS -40 -15 10 35 SINAD 7.6 8.4 9.2 10.0 10.8 11.6 12.4 60 85 -40 -15 10 35 60 85 FREQUENCY (kHz) TEMPERATURE (°C) TEMPERATURE (°C) SNR AND SINAD vs. ANALOG SUPPLY VOLTAGE SNR MAX11047 toc20 THD vs. ANALOG SUPPLY VOLTAGE MAX11047 toc21 93.0 92.5 SNR AND SINAD (dB) 92.0 -105.0 -105.5 -106.0 THD (dB) -106.5 -107.0 -107.5 -108.0 fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS 4.75 4.85 4.95 5.05 5.15 91.5 91.0 90.5 90.0 SINAD fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS 4.75 4.85 4.95 5.05 5.15 5.25 5.25 VAVDD (V) VAVDD (V) _______________________________________________________________________________________ 7 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs MAX11047/MAX11048/MAX11049 Typical Operating Characteristics (continued) (AVDD = 5V, DVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) vs. FREQUENCY MAX11047 toc22 THD vs. INPUT FREQUENCY -90 -95 THD (dB) -100 -105 -110 -115 -120 VAVDD = 5.0V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS MAX11047 toc23 94 93 92 91 90 89 88 VAVDD = 5.0V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS 0.1 1.0 10.0 -85 SINAD (dB) 100.0 0.1 1.0 10.0 100.0 FREQUENCY (kHz) FREQUENCY (kHz) CROSSTALK vs. FREQUENCY MAX11047 toc24 OUTPUT NOISE HISTOGRAM WITH INPUT CONNECTED TO 2.5V VCHX = 2.500270V VAVDD = 5.0V fSAMPLE = 250ksps TA = +25°C MAX11047 toc25 -95 -100 CROSSTALK (dB) -105 -110 -115 -120 -125 NUMBER OF OCCURENCES 10.0 100.0 VAVDD = 5.0V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS INACTIVE CHANNEL AT GND 24,000 20,000 16,000 12,000 8000 4000 0 32768 32769 32770 32771 32772 32773 FREQUENCY (kHz) OUTPUT CODE (DECIMAL) CONVERSION TIME vs. ANALOG SUPPLY VOLTAGE MAX11047 toc26 CONVERSION TIME vs. TEMPERATURE 2.99 CONVERSION TIME (µs) 2.98 2.97 2.96 2.95 2.94 2.93 2.92 MAX11047 toc27 3.00 2.99 CONVERSION TIME (µs) 2.98 2.97 2.96 2.95 2.94 2.93 2.92 4.75 4.85 4.95 5.05 5.15 3.00 5.25 -40 -15 10 35 60 32774 85 0.1 1.0 VAVDD (V) TEMPERATURE (°C) 8 _______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs Pin Description PIN 1 2 3 4 5 6 7, 21, 50 8, 20, 51 9 10 11 12 13 14 15 16 17 18 19 22, 28, 35, 43, 49 23, 27, 33, 38, 44, 48 24, 30, 41, 47 25, 31, 40, 46 26 29 32 34 36 37 39 NAME DB13 DB12 DB11 DB10 DB9 DB8 DGND DVDD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 EOC CONVST SHDN 16-Bit Parallel Data Bus Digital Output Bit 13 16-Bit Parallel Data Bus Digital Output Bit 12 16-Bit Parallel Data Bus Digital Output Bit 11 16-Bit Parallel Data Bus Digital Output Bit 10 16-Bit Parallel Data Bus Digital Output Bit 9 16-Bit Parallel Data Bus Digital Output Bit 8 Digital Ground Digital Supply. Bypass to DGND with a 0.1μF capacitor at each DVDD input. 16-Bit Parallel Data Bus Digital Output Bit 7 16-Bit Parallel Data Bus Digital Output Bit 6 16-Bit Parallel Data Bus Digital Output Bit 5 16-Bit Parallel Data Bus Digital Output Bit 4 16-Bit Parallel Data Bus Digital I/O Bit 3 16-Bit Parallel Data Bus Digital I/O Bit 2 16-Bit Parallel Data Bus Digital I/O Bit 1 16-Bit Parallel Data Bus Digital I/O Bit 0 Active-Low, End-of-Conversion Output. EOC goes low when a conversion is completed. EOC goes high when a conversion is initiated. Convert Start Input. The rising edge of CONVST ends sample and starts a conversion on the captured sample. The ADC is in acquisition mode when CONVST is low and CONVST mode is zero. Active-High Shutdown Input. Drive the SHDN high to place the device into a low-current state. In shutdown mode, the contents of the configuration register are not lost. Reference Buffer Decoupling. Bypass to AGND with at least a 22μF capacitor each at pins 22, 28, 43, and 49. Connect all RDC outputs together and bypass with 80μF total capacitance. See the Layout, Grounding, and Bypassing section. Signal Ground. Connect all AGND and AGNDS inputs together. Analog Supply Input. Bypass AVDD to AGND with a 0.1μF capacitor at each AVDD input. Analog Ground. Connect all AGND inputs together. Channel 0 Analog Input for the MAX11049 Channel 1 Analog Input for the MAX11049. Channel 0 for the MAX11048. Channel 2 Analog Input for MAX11049. Channel 1 for the MAX11048, Channel 0 for the MAX11047. Channel 3 Analog Input for MAX11049. Channel 2 for the MAX11048, Channel 1 for the MAX11047. External Reference Input/Internal Reference Output. Place a 0.1μF capacitor from REFIO to AGND. Channel 4 Analog Input for the MAX11049. Channel 3 for the MAX11048, Channel 2 for the MAX11047. Channel 5 Analog Input for the MAX11049. Channel 4 for the MAX11048, Channel 3 for the MAX11047. FUNCTION MAX11047/MAX11048/MAX11049 RDC AGNDS AVDD AGND CH0 CH1 CH2 CH3 REFIO CH4 CH5 _______________________________________________________________________________________ 9 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs MAX11047/MAX11048/MAX11049 Pin Description (continued) PIN 42 45 52 53 54 55 56 — NAME CH6 CH7 WR CS RD DB15 DB14 EP Channel 7 Analog Input for MAX11049 Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are loaded on the rising edge of WR. Active-Low Chip-Select Input. Drive CS low when reading from or writing to the ADC. Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge of RD advances the channel output on the data bus. 16-Bit Parallel Data Bus Digital Out Bit 15 16-Bit Parallel Data Bus Digital Out Bit 14 Exposed Pad. Internally connected to AGND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point. FUNCTION Channel 6 Analog Input for MAX11049. Channel 5 for MAX11048. Detailed Description The MAX11047/MAX11048/MAX11049 are fast, lowpower ADCs that combine 4, 6, or 8 independent ADC channels in a single IC. Each channel includes simultaneously sampling independent T/H circuitry that preserves relative phase information between inputs making the MAX11047/MAX11048/MAX11049 ideal for motor control and power monitoring. The MAX11047/ MAX11048/MAX11049 are available with a 0 to 5V input range that features ±20mA overrange, fault-tolerant inputs. The MAX11047/MAX11048/MAX11049 operate with a single 4.75V to 5.25V supply. A separate 2.7V to 5.25V supply for digital circuitry makes the devices compatible with low-voltage processors. The MAX11047/MAX11048/MAX11049 perform conversions for all channels in parallel by activating independent ADCs. Results are available through a high-speed, 20MHz, parallel data bus after a conversion time of 3μs following the end of a sample. The data bus is bidirectional and allows for easy programming of the configuration register. The MAX11047/MAX11048/MAX11049 feature a reference buffer, which is driven by an internal bandgap reference circuit (VREFIO = 4.096V). Drive REFIO with an external reference or bypass with a 0.1μF capacitor to ground when using the internal reference. using undersampling techniques. Use anti-alias filtering to avoid high-frequency signals being aliased into the frequency band of interest. Input Range and Protection The full-scale analog input voltage is a product of the reference voltage. For MAX11047/MAX11048/ MAX11049, the input is unipolar in the range of: 0 to + VREFIO x 5.0 4.096 In external reference mode, drive VREFIO with a 3.0V to 4.25V source, resulting in a full-scale input range of 3.662V to 5.188V, respectively. All analog inputs are fault-protected up to ±20mA. The MAX11047/MAX11048/MAX11049 include an input clamping circuit that activates when the input voltage at the analog input is above (VAVDD + 300mV) or below -300mV. The clamp circuit remains high impedance while the input signal is within the range of 0V to +VAVDD and draws little to no current. However, when the input signal exceeds the range of 0V to +VAVDD, the clamps begin to turn on. Consequently, to obtain the highest accuracy, ensure that the input voltage does not exceed the range of 0V to +VAVDD. To make use of the input clamps, connect a resistor (RS) between the analog input and the voltage source to limit the voltage at the analog input so that the fault current into the MAX11047/MAX11048/MAX11049 does not exceed ±20mA. Note that the voltage at the analog input pin limits to approximately 7V during a fault condition so the following equation can be used to calculate the value of RS: Analog Inputs Track and Hold (T/H) To preserve phase information across all channels, each input includes a dedicated T/H circuitry. The input tracking circuitry provides a 4MHz small-signal bandwidth, enabling the device to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by 10 ______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs RS = VFAULT _ MAX − 7V 20mA Applications Information Digital Interface The bidirectional, parallel, digital interface, DB0–DB3, sets the 4-bit configuration register. This interface configures the following control signals: chip select (CS), read (RD), write (WR), end of conversion (EOC), and convert start (CONVST). Figures 6 and 7 and the Timing Characteristics in the Electrical Characteristics table show the operation of the interface. DB0–DB3, together with the output-only DB4–DB15, also output the 16-bit conversion result. All bits are high impedance when RD = 1 or CS = 1. MAX11047/MAX11048/MAX11049 where VFAULT_MAX is the maximum voltage that the source produces during a fault condition. Figures 2 and 3 illustrate the clamp circuit voltage-current characteristics for a source impedance R S = 1280Ω. While the input voltage is within the range of -300mV to +(VAVDD + 300mV), no current flows in the input clamps. Once the input voltage goes beyond this voltage range, the clamps turn on and limit the voltage at the input pin. INPUT SIGNAL RS PIN VOLTAGE AVDD DVDD DB15 SOURCE BIDIRECTIONAL DRIVERS 8 x 16-BIT REGISTERS CH0 CLAMP S/H 16-BIT ADC DB4 DB3 DB0 CH7 CLAMP S/H 16-BIT ADC AGNDs CONFIGURATION REGISTERS WR RD CS CONVST SHDN EOC MAX11047 MAX11048 MAX11049 AGND INT REF BANDGAP REFERENCE REFIO EXT REF REF BUF INTERFACE AND CONTROL RDC DGND Figure 1. Required Setup for Clamp Circuit 25 20 15 10 ICLAMP (mA) 5 0 -5 -10 -15 -20 -25 -30 -20 -10 0 10 20 30 40 AT SOURCE 25 20 15 10 ICLAMP (mA) 5 0 -5 -10 -15 -20 -25 -4 -2 0 2 4 6 8 AT SOURCE RS = 1170I VAVDD = 5.0V AT CH_ INPUT RS = 1170I VAVDD = 5.0V AT CH_ INPUT SIGNAL VOLTAGE AT SOURCE AND CH_ INPUT (V) SIGNAL VOLTAGE AT SOURCE AND CH_ INPUT (V) Figure 2. Input Clamp Characteristics Figure 3. Input Clamp Characteristics (Zoom In) 11 ______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs MAX11047/MAX11048/MAX11049 DB3 (Int/Ext Reference) DB3 selects the internal or external reference. The POR default = 0. 0 = internal reference, REFIO internally driven through a 10kΩ resistor, bypass with 0.1μF capacitor to AGND. 1 = external reference, drive REFIO with a high quality reference. Table 1. Configuration Register DB3 Int/Ext Reference DB2 Output Data Format DB1 Reserved DB0 CONVST Mode DB2 (Output Data Format) DB2 selects the output data format. The POR default = 0. 0 = offset binary. 1 = two’s complement. DB1 (Reserved) Set to 0 for normal operation. 0 = normal operation. 1 = reserved; do not use. In the second mode (DB0 = 1), the MAX11047/ MAX11048/MAX11049 enter acquisition mode as soon as the previous conversion is completed. CONVST rising edge initiates the next sample and conversion sequence. Drive CONVST low for at least 20ns to be valid. Provide adequate time for acquisition and the requisite quiet time in both modes to achieve accurate sampling and maximum performance of the MAX11047/ MAX11048/MAX11049. Reading Conversion Results The CS and RD are active-low, digital inputs that control the readout through the 16-bit, parallel, 20MHz data bus (D0–D15). After EOC transitions low, read the conversion data by driving CS and RD low. Each low period of RD presents the next channel’s result. When CS and RD are high, the data bus is high impedance. CS may be driven high between individual channel readouts or left low during the entire 8-channel readout. DB0 (CONVST Mode) DB0 selects the acquisition mode. The POR default = 0. 0 = CONVST controls the acquisition and conversion. Drive CONVST low to start acquisition. The rising edge of CONVST begins the conversion. 1 = acquisition mode starts as soon as previous conversion is complete. The rising edge of CONVST begins the conversion. Programming the Configuration Register To program the configuration register, bring the CS and WR low and apply the required configuration data on DB3–DB0 of the bus and then raise WR once to save changes. Reference Internal Reference The MAX11047/MAX11048/MAX11049 feature a precision, low-drift, internal bandgap reference. Bypass REFIO with a 0.1μF capacitor to AGND to reduce noise. The REFIO output voltage may be used as a reference for other circuits. The output impedance of REFIO is 10kΩ. Drive only high-impedance circuits or buffer externally when using REFIO to drive external circuitry. External Reference Set the configuration register to disable the internal reference and drive REFIO with a high-quality external reference. To avoid signal degradation, ensure that the integrated reference noise applied to REFIO is less than 10μV in the bandwidth of up to 50kHz. Reference Buffer The MAX11047/MAX11048/MAX11049 have a built- in reference buffer to provide a low-impedance reference source to the SAR converters. This buffer is used in both internal and external reference modes. The internal reference buffer output feeds five RDC outputs. Connect all RDC outputs together. The reference buffer is externally compensated and requires at least 10μF on the RDC node for stability. For best performance, provide a total of at least 80μF on the RDC outputs. Starting a Conversion CONVST initiates conversions. The MAX11047/ MAX11048/MAX11049 provide two acquisition modes set through the configuration register. Allow a quiet time (tQ) of 500ns prior to the start of conversion to avoid any noise interference during readout or write operations from corrupting a sample. In default mode (DB0 = 0), drive CONVST low to place the MAX11047/MAX11048/MAX11049 into acquisition mode. All the input switches are closed and the internal T/H circuits track the respective input voltage. Keep the CONVST signal low for at least 1μs (tACQ) to enable proper settling of the sampled voltages. On the rising edge of CONVST, the switches are opened and the MAX11047/MAX11048/MAX11049 begin the conversion on all the samples in parallel. EOC remains high until the conversion is completed. 12 ______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs Transfer Functions Figures 8 and 9 show the transfer functions for all the formats and devices. Code transitions occur halfway between successive-integer LSB values. In cases where Y5U or Z5U ceramics are used, select higher voltage rating capacitors to compensate for the high-voltage coefficient of these ceramic capacitors, thus ensuring that at least 80μF of capacitance is on the RDC plane when the plane is driven to 4.096V by the internal reference buffer. For example, at 4.096V, a 22μF X5R ceramic capacitor with a 10V rating diminishes to only 20μF, whereas the same capacitor in Y5U ceramic at 4.096V decreases to about 13μF. However, a 22μF Y5U ceramic capacitor with a 25V rating capacitor is approximately 20μF at 4.096V. Bypass AVDD and DVDD to the ground plane with 0.1μF ceramic chip capacitors on each pin as close as possible to the device to minimize parasitic inductance. Add at least one bulk 10μF decoupling capacitor to AVDD and DVDD per PCB. Interconnect all of the AVDD inputs and DVDD inputs using two solid power planes. For best performance, bring the AVDD power plane in on the analog interface side of the MAX11047/ MAX11048/MAX11049 and the DVDD power plane from the digital interface side of the device. For sampling periods near minimum (1μs) use a 1nF C0G ceramic chip capacitor between each of the channel inputs to the ground plane as close as possible to the MAX11047/MAX11048/MAX11049. This capacitor reduces the inductance seen by the sampling circuitry and reduces the voltage transient seen by the input source circuit. MAX11047/MAX11048/MAX11049 Layout, Grounding, and Bypassing For best performance, use PCBs with ground planes. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital lines parallel to one another (especially clock lines), and avoid running digital lines underneath the ADC package. A single solid GND plane configuration with digital signals routed from one direction and analog signals from the other provides the best performance. Connect DGND, AGND, and AGNDS pins on the MAX11047/MAX11048/MAX11049 to this ground plane. Keep the ground return to the power supply for this ground low impedance and as short as possible for noise-free operation. To achieve the highest performance, connect all the RDC outputs to a local RDC plane on the PCB. Bypass the RDC outputs with a total of at least 80μF of capacitance. For example, if two capacitors are used, place two 47μF, 10V X5R capacitors in 1210 case size as close as possible to pins 22 and 49. Alternatively, if four capacitors are used, place four 22μF, 10V X5R capacitors in 1210 case size as close as possible to pins 22, 28, 43, and 49. Ensure that each capacitor is connected directly into the GND plane with an independent via. CS (USER SUPPLIED) t5 t3 WR (USER SUPPLIED) t7 t6 D0–D15 Sn Sn + 1 CS (USER SUPPLIED) t8 RD (USER SUPPLIED) t12 t13 t9 t10 t11 t4 D0–D15 (USER SUPPLIED) CONFIGURATION REGISTER Figure 4. Programming Configuration-Register Timing Requirements Figure 5. Readout Timing Requirements ______________________________________________________________________________________ 13 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs MAX11047/MAX11048/MAX11049 SAMPLE tCON CONVST tACQ t1 EOC tO tQ CS RD D0–D15 S0 S1 S6 S7 Figure 6. Conversion Timing Diagram (DB0 = 0) SAMPLE tCON CONVST tACQ t2 EOC tO tQ CS RD D0–D15 S0 S1 S6 S7 Figure 7. Conversion Timing Diagram (DB0 = 1) 14 ______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs MAX11047/MAX11048/MAX11049 7FFF 7FFE OUTPUT CODE (hex) OUTPUT CODE (hex) LSB = FS 65536 FULL-SCALE TRANSITION FFFF FFFE LSB = FS 65536 FULL-SCALE TRANSITION 0001 0000 FFFF FFFE 8001 8000 7FFF 7FFE 8001 8000 0 FS/2 INPUT VOLTAGE (LSB) CODE = VIN x 65536 - 32768, 5 VRDC x 4.096 FS = 5 x VRDC 4.096 +FS 0001 0000 0 FS/2 INPUT VOLTAGE (LSB) CODE = 5 x VRDC VIN x 65536 , FS = 4.096 5 4.096 +FS VRDC x Figure 8. Two’s Complement Transfer Function Figure 9. Offset-Binary Transfer Function Typical Application Circuits Power-Grid Protection Figure 10 shows a typical power-grid protection application. DSP Motor Control Figure 11 shows a typical DSP motor control application. Definitions Integral Nonlinearity (INL) INL is the deviation of the values on an actual transfer function from a straight line. For these devices, this straight line is a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. Differential Nonlinearity (DNL) DNL is the difference between an actual step width and the ideal value of 1 LSB. For these devices, the DNL of each digital output code is measured and the worstcase value is reported in the Electrical Characteristics table. A DNL error specification of greater than -1 LSB guarantees no missing codes and a monotonic transfer function for an SAR ADC. For example, -0.9 LSB guarantees no missing code while -1.1 LSB results in missing code. Offset Error For the MAX11047/MAX11048/MAX11049, the offset error is defined at code transition 0x0000 to 0x0001 in offset binary encoding and 0x8000 to 0x8001 for two’s complement encoding. The offset code transitions should occur with an analog input voltage of exactly 0.5 x (5/4.096) x VREF/65,536 above GND. The offset error is defined as the deviation between the actual analog input voltage required to produce the offset code transition and the ideal analog input of 0.5 x (5/4.096) x VREF/65,536 above GND, expressed in LSBs. Gain Error Gain error is defined as the difference between the change in analog input voltage required to produce a top code transition minus a bottom code transition, subtracted from the ideal change in analog input voltage on (5/4.096) x V REF x (65,534/65,536). For the MAX11047/MAX11048/MAX11049, top code transition is 0x7FFE to 0x7FFF in two’s complement mode and 0xFFFE to 0xFFFF in offset binary mode. The bottom code transition is 0x8000 and 0x8001 in two’s complement mode and 0x0000 and 0x0001 in offset binary mode. For the MAX11047/MAX11048/MAX11049, the analog input voltage to produce these code transitions is measured and the gain error is computed by subtracting (5/4.096) x VREF x (65,534/65,536) from this measurement. 15 ______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs MAX11047/MAX11048/MAX11049 VOLTAGE TRANSFORMER OPT PHASE 1 2.5V ADC OPT CURRENT TRANSFORMER VN ADC 2.5V ADC NEUTRAL IN ADC LOAD 1 MAX11049 LOAD 2 LOAD 3 I3 ADC V3 I2 PHASE 2 V2 ADC ADC ADC PHASE 3 Figure 10. Power-Grid Protection 16 ______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs MAX11047/MAX11048/MAX11049 DSP-BASED DIGITAL PROCESSING ENGINE MAX11048 16-BIT ADC IGBT CURRENT DRIVERS 16-BIT ADC 16-BIT ADC 16-BIT ADC 16-BIT ADC IPHASE1 IPHASE3 IPHASE2 3-PHASE ELECTRIC MOTOR POSITION ENCODER Figure 11. DSP Motor Control ______________________________________________________________________________________ 17 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs MAX11047/MAX11048/MAX11049 Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the ADC’s resolution (N bits): SNR = (6.02 x N + 1.76)dB where N = 16 bits. In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components not including the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is the ratio of the fundamental input frequency’s RMS amplitude to the RMS equivalent of all the other ADC output signals: ⎡ ⎤ Signal RMS SINAD(dB) = 10 × log ⎢ ⎥ ⎣ (Noise + Distortion) RMS ⎦ Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest frequency component. Aperture Delay Aperture delay (tAD) is the time delay from the sampling clock edge to the instant when an actual sample is taken. Aperture Jitter Aperture Jitter (tAJ) is the sample-to-sample variation in aperture delay. Channel-to-Channel Isolation Channel-to-channel isolation indicates how well each analog input is isolated from the other channels. Channel-to-channel isolation is measured by applying DC to channels 1 to 7, while a -0.4dBFS sine wave at 60Hz is applied to channel 0. A 10ksps FFT is taken for channel 0 and channel 1. Channel-to-channel isolation is expressed in dB as the power ratio of the two 60Hz magnitudes. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC in a manner that ensures that the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased 3dB. Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. This point is defined as fullpower input bandwidth frequency. Effective Number of Bits (ENOB) The ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the full-scale range of the ADC, calculate the ENOB as follows: ENOB = SINAD − 1. 76 6. 02 Total Harmonic Distortion (THD) THD is the ratio of the RMS of the first five harmonics of the input signal to the fundamental itself. This is expressed as: ⎡ V2 2 + V3 2 + V4 2 + V 5 2 THD = 20 × log ⎢ V1 ⎢ ⎣ ⎤ ⎥ ⎥ ⎦ Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 56 TQFN-EP PACKAGE CODE T5688+2 DOCUMENT NO. 21-0135 where V1 is the fundamental amplitude and V2 through V5 are the 2nd- through 5th-order harmonics. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.