MAX110BEWE

19-0283; Rev 5; 11/98 KIT ATION EVALU E AILABL AV Low-Cost, 2-Channel, ±14-Bit Serial ADCs General Description The MAX110/MAX111 analog-to-digital converters (ADCs) use an internal auto-calibration technique to achieve 14-bit resolution plus overrange, with no external components. Operating supply current is only 550µA (MAX110) and reduces to 4µA in power-down mode, making these ADCs ideal for high-resolution battery-powered or remote-sensing applications. A fast serial interface simplifies signal routing and opto-isolation, saves microcontroller pins, and offers compatibility with SPI™, QSPI™, and MICROWIRE™. The MAX110 operates with ±5V supplies, and converts differential analog signals in the -3V to +3V range. The MAX111 operates with a single +5V supply and converts differential analog signals in the ±1.5V range, or singleended signals in the 0V to +1.5V range. Internal calibration allows for both offset and gain-error correction under microprocessor (µP) control. Both devices are available in space-saving 16-pin DIP and SO packages, as well as an even smaller 20-pin SSOP package. ____________________________Features o o o o o Single +5V Supply (MAX111) Two Differential Input Channels 14-Bit Resolution Plus Sign and Overrange 0.03% Linearity (MAX110) 0.05% Linearity (MAX111) Low Power Consumption: 550µA (MAX110) 640µA (MAX111) 4µA Shutdown Current Up to 50 Conversions/sec 50Hz/60Hz Rejection Auto-Calibration Mode No External Components Required 16-Pin DIP/SO, 20-Pin SSOP MAX110/MAX111 o o o o o Ordering Information PART MAX110ACPE TEMP. RANGE 0°C to +70°C PIN-PACKAGE INL(%) 16 Plastic DIP ±0.03 ________________________Applications Process Control Weigh Scales Panel Meters Data-Acquisition Systems Temperature Measurement MAX110BCPE 0°C to +70°C 16 Plastic DIP ±0.05 MAX110ACWE 0°C to +70°C 16 Wide SO ±0.03 MAX110BCWE 0°C to +70°C 16 Wide SO ±0.05 MAX110ACAP 0°C to +70°C 20 SSOP ±0.03 MAX110BCAP 0°C to +70°C 20 SSOP ±0.05 MAX110BC/D 0°C to +70°C Dice* ±0.05 Ordering Information continued at end of data sheet. * Contact factory for dice specifications. Typical Operating Circuit +5V Pin Configurations TOP VIEW IN1+ VDD IN1+ RCSEL 1 2 3 4 5 6 7 8 16 15 IN1IN2+ IN2VSS (AGND) GND DIN DOUT CS REFREF+ VDD RCSEL XCLK IN1- MAX110 MAX111 IN2+ IN2REF+ REFCS SCLK VSS (AGND) DOUT DIN FROM µC MAX110 MAX111 14 13 12 11 10 9 SCLK BUSY ( ) ARE FOR MAX111 DIP/SO ( ) ARE FOR MAX111 -5V (0V) Pin Configurations continued at end of data sheet. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 ABSOLUTE MAXIMUM RATINGS VDD to GND ...........................................................................+6V VSS to GND (MAX110)..............................................+0.3V to -6V AGND to DGND.....................................................-0.3V to +0.3V VIN1+, VIN1- ......................................(VDD + 0.3V) to (VSS - 0.3V) VIN2+, VIN2- ......................................(VDD + 0.3V) to (VSS - 0.3V) VREF+, VREF- ....................................(VDD + 0.3V) to (VSS - 0.3V) Digital Inputs and Outputs .........................(VDD + 0.3V) to -0.3V Continuous Power Dissipation 16-Pin Plastic DIP (derate 10.53mW/°C above +70°C).....842mW 16-Pin Wide SO (derate 9.52mW/°C above +70°C) ......762mW 20-Pin SSOP (derate 8.00mW/°C above +70°C) ...........640mW 16-Pin CERDIP (derate 10.00mW/°C above +70°C)......800mW Operating Temperature Ranges MAX11_ _C_ _......................................................0°C to +70°C MAX11_ _E_ _ ...................................................-40°C to +85°C MAX11_BMJE .................................................-55°C to +125°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS—MAX110 PARAMETER ACCURACY (Note 1) Resolution Differential Nonlinearity No-Missing-Codes Resolution RES DNL (Note 2) (Notes 3, 4) (Note 3) MAX110AC/E Relative Accuracy (Notes 3, 5–7) INL MAX110BC/E MAX110BM Offset Error Offset Error Temperature Drift Common-Mode Rejection Ratio Full-Scale Error Full-Scale Error Temperature Drift Power-Supply Rejection ANALOG INPUTS Differential Input Voltage Range Absolute Input Voltage Range Input Bias Current Input Capacitance VIN VIN+, VINIIN+, IIN(Note 3) (Note 6) CMRR VIN+ = VIN- = 0V After offset null Uncalibrated SYMBOL (VDD = 5V ±5%, VSS = -5V ±5%, fXCLK = 1MHz, ÷ 2 mode (DV2 = 1), 81,920 CLK cycles/conv, VREF+ = 1.5V, VREF- = -1.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) CONDITIONS MIN 14 + POL + OFL ±2 13 + POL + OFL -VREF ≤ VIN ≤ VREF -0.83 x VREF ≤ VIN ≤ 0.83 x VREF -VREF ≤ VIN ≤ VREF -0.83 x VREF ≤ VIN ≤ 0.83 x VREF -VREF ≤ VIN ≤ VREF -0.83 x VREF ≤ VIN ≤ 0.83 x VREF 0.003 0.02 6 ±0.1 -8 8 VSS = -5V, VDD = 4.75V to 5.25V VDD = 5V, VSS = -4.75V to -5.25V 15 30 0 ±0.03 ±0.04 ±0.018 ±0.1 ±0.05 ±4 mV µV/°C ppm/V % ppm/°C ppm ±0.06 ±0.015 ±0.03 %FSR TYP MAX UNITS Bits LSB Bits -2.5V ≤ (VIN+ = VIN-) ≤ 2.5V After gain calibration (Note 5) Uncalibrated -VREF VSS + 2.25 +VREF VDD 2.25 500 10 V V nA pF 2 _______________________________________________________________________________________ Low-Cost, 2-Channel, ±14-Bit Serial ADCs ELECTRICAL CHARACTERISTICS—MAX110 (continued) PARAMETER REFERENCE INPUTS Differential Reference Input Voltage Range Absolute Reference Input Voltage Range Reference Input Current Reference Input Capacitance CONVERSION TIME Synchronous Conversion Time (Note 7) Oversampling Clock Frequency Input High Voltage Input Low Voltage Input Capacitance Input Leakage Current ILKG tCONV fOSC 10,240 clock-cycles/conversion 102,400 clock-cycles/conversion (Note 8) 0.25 20.48 204.80 1.25 ms MHz VREF VREF+, VREFIREF+, IREFVREF+ = 2.5V, VREF- = 0V (Note 3) 0 VSS + 2.25 3.0 VDD 2.25 500 10 V V nA pF SYMBOL CONDITIONS MAX110/MAX111 (VDD = 5V ±5%, VSS = -5V ±5%, fXCLK = 1MHz, ÷ 2 mode (DV2 = 1), 81,920 CLK cycles/conv, VREF+ = 1.5V, VREF- = -1.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) MIN TYP MAX UNITS DIGITAL INPUTS (CS, SCLK, DIN, and XCLK when RCSEL = 0V) VIH VIL (Note 3) Digital inputs at 0V or 5V DOUT, BUSY, ISINK = 1.6mA XCLK, ISINK = 200µA DOUT, BUSY, VDD = 4.75V, ISOURCE = 1.0mA XCLK, VDD = 4.75V, ISOURCE = 200µA Leakage Current Output Capacitance Positive Supply Voltage Negative Supply Voltage VDD VSS ILKG VOUT = 5V or 0V (Note 3) Performance guaranteed by supply rejection test Performance guaranteed by supply rejection test fXCLK = 500kHz, continuous-conversion mode XCLK unloaded, continuous-conversion mode, RC oscillator operational (Note 9) fXCLK = 500kHz, continuous-conversion mode 4.75 -4.75 550 780 320 4 0.05 650 10 2 µA µA VDD - 0.5 VDD - 0.5 ±10 10 5.25 -5.25 950 µA µA pF V V 2.4 0.8 10 ±1 0.4 0.4 V V pF µA DIGITAL OUTPUTS (DOUT, BUSY, and XCLK when RCSEL = VDD) Output Low Voltage VOL V Output High Voltage VOH V POWER REQUIREMENTS (all digital inputs at 0V or 5V) Positive Supply Current IDD VDD = 5.25V, VSS = -5.25V VDD = 5.25V, VSS = -5.25V Negative Supply Current Power-Down Current ISS IDD ISS VDD = 5.25V, VSS = -5.25V, VXCLK = 0V, PD = 1 _______________________________________________________________________________________ 3 Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 ELECTRICAL CHARACTERISTICS—MAX111 (VDD = 5V ±5%, fXCLK = 1MHz, ÷ 2 mode (DV2 = 1), 81,920 CLK cycles/conv, VREF+ = 1.5V, VREF- = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER ACCURACY (Note 1) Resolution Differential Nonlinearity No-Missing-Codes Resolution RES DNL (Note 2) (Notes 3, 4) (Note 3) MAX111AC/E Relative Accuracy, Differential Input (Notes 3, 5–7) INL MAX111BC/E MAX111BM MAX111AC/E Relative Accuracy, Single-Ended Input (IN- = GND) INL MAX111BC/E MAX111BM Offset Error Common-Mode Rejection Ratio Full-Scale Error Full-Scale Error Temperature Drift Power-Supply Rejection ANALOG INPUTS Differential Input Voltage Range Absolute Input Voltage Range Input Bias Current Input Capacitance VIN VIN+, VINIIN+, IIN(Note 3) (Note 6) -VREF 0 +VREF VDD - 3.2 500 10 V V nA pF VDD = 4.75V to 5.25V CMRR VIN+ = VIN- = 0V 10mV ≤ (VIN+ = VIN-) ≤ 2.0V After gain calibration (Note 5) Uncalibrated -8 8 15 6 ±0.2 0 -VREF ≤ VIN ≤ VREF -0.667 x VREF ≤ VIN ≤ 0.667 x VREF -VREF ≤ VIN ≤ VREF -0.667 x VREF ≤ VIN ≤ 0.667 x VREF -VREF ≤ VIN ≤ VREF -0.667 x VREF ≤ VIN ≤ 0.667 x VREF 0V ≤ VIN ≤ VREF VIN ≤ 0.667 x VREF 0V ≤ VIN ≤ VREF VIN ≤ 0.667 x VREF 0V ≤ VIN ≤ VREF VIN ≤ 0.667 x VREF ±0.1 ±0.06 ±0.18 ±0.10 ±0.25 ±0.15 ±4 mV ppm/V % ppm/°C ppm %FSR 13 + POL + OFL ±0.05 ±0.03 ±0.10 ±0.05 ±0.18 ±0.10 ±0.25 ±0.20 %FSR 14 + POL + OFL ±2 Bits LSB Bits SYMBOL CONDITIONS MIN TYP MAX UNITS 4 _______________________________________________________________________________________ Low-Cost, 2-Channel, ±14-Bit Serial ADCs ELECTRICAL CHARACTERISTICS—MAX111 (continued) (VDD = 5V ±5%, fXCLK = 1MHz, ÷ 2 mode (DV2 = 1), 81,920 CLK cycles/conv, VREF+ = 1.5V, VREF- = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER REFERENCE INPUTS Differential Reference Input Voltage Range Absolute Reference Input Voltage Range Reference Input Current Reference Input Capacitance CONVERSION TIME Synchronous Conversion Time (Note 7) Oversampling Clock Frequency Input High Voltage Input Low Voltage Input Capacitance Input Leakage Current ILKG tCONV fOSC 10,240 clock-cycles/conversion 102,400 clock-cycles/conversion (Note 8) 0.25 20.48 204.80 1.25 ms MHz VREF VREF+, VREFIREF+, IREFVREF+ = 1.5V, VREF- = 0V (Note 3) 0 0 1.5 VDD - 3.2 500 10 V V nA pF SYMBOL CONDITIONS MIN TYP MAX UNITS MAX110/MAX111 DIGITAL INPUTS (CS, SCLK, DIN, and XCLK when RCSEL = 0V) VIH VIL (Note 3) Digital inputs at 0V or 5V DOUT, BUSY, ISINK = 1.6mA XCLK, ISINK = 200µA DOUT, BUSY, VDD = 4.75V, ISOURCE = 1.0mA XCLK, VDD = 4.75V, ISOURCE = 200µA Leakage Current Output Capacitance Positive Supply Voltage VDD ILKG VOUT = 5V or 0V (Note 3) Performance guaranteed by supply rejection test fXCLK = 500kHz, continuous-conversion mode VDD = 5.25V XCLK unloaded, continuous-conversion mode, RC oscillator operational (Note 9) VDD = 5.25V, VXCLK = 0V, PD = 1 4.75 640 960 4 10 µA VDD - 0.5 VDD - 0.5 ±1 10 5.25 1200 µA µA pF V 2.4 0.8 10 ±1 0.4 0.4 V V pF µA DIGITAL OUTPUTS (DOUT, BUSY, and XCLK when RCSEL = VDD) Output Low Voltage VOL V Output High Voltage VOH V POWER REQUIREMENTS (all digital inputs at 0V or 5V) Supply Current IDD Power-Down Current IDD _______________________________________________________________________________________ 5 Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 Note 1: These specifications apply after auto-null and gain calibration. Performance at power-supply tolerance limits is guaranteed by power-supply rejection tests. Tests are performed at VDD = 5V and VSS = -5V (MAX110). Note 2: 32,768 LSBs cover an input voltage range of ±VREF (15 bits). An additional bit (OFL) is set for VIN > VREF. Note 3: Guaranteed by design. Not subject to production testing. Note 4: DNL is less than ±2 counts (LSBs) out of 215 counts (±14 bits). The major source of DNL is noise, and this can be further improved by averaging. Note 5: See 3-Step Calibration section in text. Note 6: VREF = (VREF+ - VREF-), VIN = (VIN1+ - VIN1-) or (VIN2+ - VIN2-). The voltage is interpreted as negative when the voltage at the negative input terminal exceeds the voltage at the positive input terminal. Note 7: Conversion time is set by control bits CONV1–CONV4. Note 8: Tested at clock frequency of 1MHz with the divide-by-2 mode (i.e. oversampling clock of 500kHz). See Typical Operating Characteristics section for the effect of other clock frequencies. Also read the Clock Frequency section. Note 9: This current depends strongly on CXCLK (see Applications Information section). TIMING CHARACTERISTICS (see Figure 6) (VDD = 5V, VSS = -5V (MAX110), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER CS to SCLK Setup Time (Note 10) CS to SCLK Hold Time (Note 10) DIN to SCLK Setup Time (Note 10) DIN to SCLK Hold Time (Note 10) SCLK, XCLK Pulse Width (Note 10) SYMBOL TA = +25°C tCSS MAX11_ _C/E MAX11_ BM tCSH TA = +25°C tDS MAX11_ _C/E MAX11_ BM tDH TA = +25°C tCK MAX11_ _C/E MAX11_ BM Data Access Time (Note 10) TA = +25°C tDA CLOAD = 50pF MAX11_ _C/E MAX11_ BM SCLK to DOUT Valid Delay (Note 10) Bus Relinquish Time (Note 10) RC Oscillator Frequency TA = +25°C tDO CLOAD = 50pF TA = +25°C MAX11_ _C/E/M TA = +25°C MAX11_ _C/E MAX11_ BM 1.3 1.1 2.0 2.8 3.0 MHz MAX11_ _C/E MAX11_ BM tDH CONDITIONS MIN 60 80 100 0 60 80 100 0 100 120 160 0 0 0 0 0 0 35 60 35 80 100 120 100 120 140 80 120 ns ns ns ns ns ns ns ns TYP MAX UNITS Note 10: Timing specifications are guaranteed by design. All input control signals are specified with tr = tf = 5ns (10% to 90% of +5V) and timed from a +1.6V voltage level. 6 _______________________________________________________________________________________ Low-Cost, 2-Channel, ±14-Bit Serial ADCs __________________________________________Typical Operating Characteristics (MAX110, VDD = 5V, VSS = -5V, VREF+ = 1.5V, VREF- = -1.5V, differential input (VIN+ = -VIN-), fXCLK = 1MHz, ÷ 2 mode (DV2 = 1), 81,920 clocks/conv, TA = +25°C, unless otherwise noted.) MAX110 RELATIVE ACCURACY (-0.83 VREF < VIN < 0.83 VREF) MAX110 RELATIVE ACCURACY (-VREF < VIN < VREF) MAX110 toc02 RELATIVE ACCURANCY (%FSR) RELATIVE ACCURANCY (%FSR) -40°C ≤ TA ≤ +85°C RANGE OF INL VALUES (200 PIECE SAMPLE SIZE) -40°C ≤ TA ≤ +85°C RANGE OF INL VALUES (200 PIECE SAMPLE SIZE) 0.05 0.05 0 0 -0.05 -0.05 -0.10 -0.10 -4 -2 0 2 4 -4 -2 0 2 4 VIN (V) VIN (V) MAX110 RELATIVE ACCURACY vs. OVERSAMPLING FREQUENCY (fOSC) VDD = 4.75V VSS = -4.75V TA = +85°C MAX110 RELATIVE ACCURACY vs. TEMPERATURE MAX110-TOC03 RELATIVE ACCURACY (%FSR) RELATIVE ACCURACY (%FSR) 0.06 0.05 0.04 0.03 0.02 0.01 0 0.08 ÷1 MODE 0.06 ÷2 MODE 0.04 0.02 0 ÷ 4 MODE 0 0.25 0.50 0.75 1.00 1.25 -50 -25 0 25 50 75 100 fOSC (MHz) TEMPERATURE (°C) MAX110 POWER DISSIPATION vs. OVERSAMPLING FREQUENCY (fOSC) VDD = 5.25V VIN = 0V TA = -40°C MAX110-TOC05 8 POWER DISSIPATION (mW) 7 6 5 4 3 2 0 0.25 0.50 0.75 1.00 ÷ 4 MODE ÷ 2 MODE ÷ 1 MODE 1.25 fOSC (MHz) _______________________________________________________________________________________ MAX110-TOC04 0.07 0.10 MAX110 toc01 0.10       

,, 0.10 MAX110/MAX111 7 Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 ____________________________Typical Operating Characteristics (continued) (MAX111, VDD = 5V, VREF+ = 1.5V, VREF- = 0V, differential input (VIN+ = -VIN-), fXCLK = 1MHz, ÷ 2 mode (DV2 = 1), 81,920 clocks/conv, TA = +25°C, unless otherwise noted.) MAX111 RELATIVE ACCURACY (-0.667VREF < VIN < 0.667VREF) MAX110-TOC6 MAX111 RELATIVE ACCURACY (-VREF < VIN < VREF) MAX110-TOC7 0.10 0.10 RELATIVE ACCURACY (%FSR) RELATIVE ACCURACY (%FSR) 0.05 0.05 0 0 -0.05 -0.05 -0.10 -2.0 -1.5 -1.0 -0.5 0 VIN (V) 0.5 1.0 1.5 2.0 -0.10 -2.0 -1.5 -1.0 -0.5 0 VIN (V) 0.5 1.0 1.5 2.0 MAX111 RELATIVE ACCURACY vs. OVERSAMPLING FREQUENCY (fOSC) MAX110-TOC08 MAX111 RELATIVE ACCURACY vs. TEMPERATURE MAX110-TOC09 0.14 RELATIVE ACCURACY (%FSR) 0.12 0.1 0.08 0.06 0.04 0.02 0 0 0.25 0.50 fOSC (MHz) 0.75 VDD = 4.75V TA = +85°C 0.10 RELATIVE ACCURACY (%FSR) 0.08 ÷ 1 MODE ÷2 MODE ÷4 MODE 0.06 0.04 0.02 0 1.00 -50 -25 0 25 50 75 100 TEMPERATURE (°C) MAX111 POWER DISSIPATION vs. OVERSAMPLING FREQUENCY (fOSC) 6 POWER DISSIPATION (mW) 5 4 3 2 1 0 0 0.25 0.50 0.75 1.00 1.25 fOSC (MHz) VDD = 5.25V VIN = 0V TA = -40°C MAX110-TOC10 7 ÷ 4 MODE ÷ 1 MODE ÷ 2 MODE 8 _______________________________________________________________________________________ Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 ______________________________________________________________Pin Description PIN NAME DIP/SO 1 2 3 4 5 SSOP 1 2 3 6 7 IN1+ REFREF+ VDD RCSEL Channel 1 Positive Analog Input Negative Reference Input Positive Reference Input Positive Power-Supply Input—connect to +5V RC Select Input. Connect to GND to select external clock mode. Connect to VDD to select RC OSC mode. XCLK must be connected to VDD or GND through a resistor (1MΩ or less) when RC OSC mode is selected. Clock Input / RC Oscillator Output. TTL/CMOS-compatible oversampling clock input when RCSEL = GND. Connects to the internal RC oscillator when RCSEL = VDD. XCLK must be connected to VDD or GND through a resistor (1MΩ or less) when RC OSC mode is selected. Serial Clock Input. TTL/CMOS-compatible clock input for serial-interface data I/O. Busy Output. Goes low at conversion start, and returns high at end of conversion. Chip-Select Input. Pull this input low to perform a control-word-write/data-read operation. A conversion begins when CS returns high, provided NO-OP is a 1. See the section Using the MAX110/MAX111 with SPI, QSPI, and MICROWIRE Serial Interfaces. Serial Data Output. High-impedance when CS is high. Serial Data Input. See Control Register section. Digital Ground MAX110 Negative Power-Supply Input—connect to -5V MAX111 Analog Ground Channel 2 Negative Analog Input Channel 2 Positive Analog Input Channel 1 Negative Analog Input No Connect—there is no internal connection to this pin FUNCTION 6 8 XCLK 7 8 9 10 11 12 13 14 15 16 — 9 10 11 12 13 16 17 18 19 20 4, 5, 14, 15 SCLK BUSY CS DOUT DIN GND VSS AGND IN2IN2+ IN1N.C. _______________Detailed Description The MAX110/MAX111 ADC converts low-frequency analog signals to a 16-bit serial digital output (14 data bits, a sign bit, and an overrange bit) using a first-order sigma-delta loop (Figure 1). The differential input voltage is internally connected to a precision voltage-tocurrent converter. The resulting current is integrated and applied to a comparator. The comparator output then drives an up/down counter and a 1-bit DAC. When the DAC output is fed back to the integrator input, the sigma-delta loop is completed. During a conversion, the comparator output is a VREFto VREF+ square wave; its duty cycle is proportional to the magnitude of the differential input voltage applied to the ADC. The up/down counter clocks data in from the comparator at the oversampling clock rate and averages the pulse-width-modulated (PWM) square wave to produce the conversion result. A 16-bit static shift register stores the result at the end of the conversion. Figure 2 shows the ADC waveforms for a differential analog input equal to 1/2 (V REF+ - V REF- ). The resulting comparator and 1-bit DAC outputs are high for seven cycles and low for three cycles of the oversampling clock. Since the analog input signal is integrated over many clock cycles, much of the signal and quantization noise is attenuated. The more clock cycles allowed during each conversion, the greater the noise attenuation (see Programming Conversion Time). 9 _______________________________________________________________________________________ Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 DIN IN1+ IN1IN2+ IN2REF+ REFIN+ INPUT MUX INGm Σ DITHER GENERATOR INTEGRATOR ∫ UP/DOWN COUNTER SERIAL SHIFT REGISTER 16 16 CONTROL REGISTER Gm 16 TIMER + CONTROL LOGIC + CLOCK GENERATOR OSC DIVIDER NETWORK, DIVIDE BY 1, 2, OR 4 RC OSCILLATOR 16 BUSY RCSEL DOUT SCLK CS MAX110 MAX111 XCLK Figure 1. Functional Diagram Oversampling Clock XCLK internally connects to a clock-frequency divider network, whose output is the ADC oversampling clock, fOSC. This allows the selected clock source (internal RC oscillator or external clock applied to XCLK) to be divided by one, two, or four (see Clock Divider-Ratio Control Bits). Figure 3 shows the two methods for providing the oversampling clock to the MAX110/MAX111. In externalclock mode (Figure 3a), the internal RC oscillator is disabled and XCLK accepts a TTL/CMOS-level clock to provide the oversampling clock to the ADC. Select external-clock mode (Figure 3a) by connecting RCSEL to GND and a TTL/CMOS-compatible clock to XCLK (see S electing the Oversampling Clock Frequency). In RC-oscillator mode (Figure 3b), the internal RC oscillator is active and its output is connected to XCLK (Figure 1). Select RC-oscillator mode by connecting RCSEL to VDD. This enables the internal oscillator and connects it to XCLK for use by the ADC and external system components. Minimize the capacitive loading on XCLK when using the internal RC oscillator. VREF+ DIFFERENTIAL ANALOG INPUT VREFVREF+ OUTPUT FROM 1-BIT DAC VREFOVERSAMPLING CLOCK DC LEVEL AT 1/2 VREF MAX110 MAX111 Figure 2. ADC Waveforms During a Conversion 10 ______________________________________________________________________________________ Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 +5V +5V VDD RCSEL RCSEL VDD MAX110 MAX111 GND TTL/CMOS XCLK VSS (AGND) -5V (0V) ( ) ARE FOR MAX111. 1MΩ +5V MAX110 MAX111 GND XCLK VSS (AGND) -5V (0V) ( ) ARE FOR MAX111. Figure 3a. Connection for External-Clock Mode Figure 3b. Connection for Internal RC-Oscillator Mode—XCLK connects to the internal RC oscillator. Note, the pull-up resistor is not necessary if the internal oscillator is never shut down. ADC Operation The output data from the MAX110/MAX111 is arranged in twos-complement format (Figures 4, 5). The sign bit (POL) is shifted out first, followed by the overrange bit (OR), and the 14 data bits (MSB first) (see Figure 6). The MAX110 operates from ±5V power supplies and converts low-frequency analog signals in the ±3V range when using the maximum reference voltage of VREF = 3V (VREF = VREF+ - VREF-). Within the ±3V input range, greater accuracy is obtained within ±2.5V (see Electrical Characteristics for details). Note that a negative input voltage is defined as VIN- > VIN+. For the MAX110, the absolute voltage at any analog input pin must remain within the (VSS + 2.25V) to (VDD - 2.25V) range. The MAX111 operates from a single +5V supply and converts low-frequency differential analog signals in the ±1.5V range when using the maximum reference voltage of V REF = 1.5V. As indicated in the E lectrical Characteristics, greater accuracy is achieved within the ±1.2V range. The absolute voltage at any analog input pin for the MAX111 must remain within 0V to VDD - 3.2V. When VIN- > VIN+ the input is interpreted as negative. The overrange bit (OFL) is provided to sense when the input voltage level has exceeded the reference voltage level. The converter does not “saturate” until the input voltage is typically 20% larger. The linearity is not guaranteed in this range. Note that the overrange bit works properly if the reference voltage remains within the recommended voltage range (see Reference Inputs). If the reference voltage exceeds the recommended input range, the overrange bit may not operate properly. Digital Interface—Starting a Conversion Data is transferred into and out of the serial I/O shift register by pulling CS low and applying a serial clock at SCLK. This fully static shift register allows SCLK to range from DC to 2MHz. Output data from the ADC is clocked out on SCLK’s falling edge and should be read on SCLK’s rising edge. Input data to the ADC at DIN is clocked in on SCLK’s rising edge. A new conversion begins when CS returns high, provided the MSB in the input control word ( NO-OP ) is a 1 (see U sing the MAX110/MAX111 with MICROWIRE, SPI, and QSPI Serial Interfaces). Figure 6 shows the detailed serialinterface timing diagram. CS must remain high during the conversion (while BUSY remains low). Bringing CS low during the conversion causes the ADC to stop converting, and may result in erroneous output data. Using the MAX110/MAX111 with SPI, QSPI, and MICROWIRE Serial Interfaces Figure 7 shows the most common serial-interface connections. The MAX110/MAX111 are compatible with SPI, QSPI (CPHA = 0, CPOL = 0), and MICROWIRE serial-interface standards. 11 ______________________________________________________________________________________ Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 OUTPUT CODE POL OFL D13...D0 1 00 . . .000 +OVERFLOW 0 0 0 11 . . .111 0 0 11 . . .110 0 0 11 . . .101 0 0 0 0 1 1 1 1 1 1 -OVERFLOW 1 0 0 0 0 1 1 1 1 1 1 0 11 . . .100 00 . . .001 00 . . .001 00 . . .000 11 . . .111 11 . . .110 00 . . .011 00 . . .010 00 . . .001 00 . . .000 11 . . .111 - VREF INPUT VOLTAGE (LSBs) VREF -1LSB +OVERFLOW TRANSITION -OVERFLOW TRANSITION Figure 4. Differential Transfer Function OUTPUT CODE POL OFL D13...D0 1 00 . . .000 +OVERFLOW 0 0 0 11 . . .111 0 0 11 . . .110 0 0 0 0 11 . . .101 11 . . .100 OVERFLOW TRANSITION 0 0 0 0 1 0 0 0 0 1 00 . . .011 00 . . .010 00 . . .001 00 . . .000 11 . . .111 0 1 2 3 INPUT VOLTAGE (LSBs) VREF -1LSB Figure 5. Unipolar Transfer Function 12 ______________________________________________________________________________________ Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 CS tCSH tCK tCSS SCLK tCK tDH tDS DIN MSB LSB tDO tDA DOUT POL OFL MSB tDH DO BUSY END OF CONVERSION START OF CONVERSION Figure 6. Detailed Serial-Interface Timing +5V SS I/O SCK µP MISO MOSI MASKABLE INTERRUPT a. SPI/QSPI CS SCLK MAX110 DOUT MAX111 DIN BUSY The ADC serial interface operates with just SCLK, DIN, and DOUT (allow sufficient time for the conversion to complete between read/write operations). Achieve continuous operation by connecting BUSY to an uncommitted µP I/O or interrupt, to signal the processor when the conversion results are ready. Figures 8a and 8b show the timing for SPI/MICROWIRE and QSPI operation. The fully static 16-bit I/O register allows infinite time between the two 8-bit read/write operations necessary to obtain the full 16 bits of data with SPI and MICROWIRE. CS must remain low during the entire two-byte transfer (Figure 8a). QSPI allows a full 16-bit data transfer (Figure 8b). I/O SK µP SI SO MASKABLE INTERRUPT or I/O b. MICROWIRE CS SCLK MAX110 DOUT MAX111 DIN BUSY Interfacing to the 80C32 Microcontroller Family Figure 7c shows the general 80C32 connection to the MAX110/MAX111 using Port 1. For a more detailed discussion, see the MAX110 evaluation kit manual. I/O Shift Register µP P1.0 P1.1 P1.2 P1.3 P1.4 CS SCLK MAX110 DIN MAX111 DOUT BUSY c. 80C51/80C32 Figure 7. Common Serial-Interface Connections Serial data transfer is accomplished with a 16-bit fully static shift register. The 16-bit control word shifted into this register during a data-transfer operation controls the ADC’s various functions. The MSB ( NO-OP ) enables/disables transfer of the control word within the ADC. A logic 1 causes the remaining 15 bits in the control word to be transferred from the I/O register into the control register when C S goes high, updating the ADC’s configuration and starting a new conversion. If 13 ______________________________________________________________________________________ Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 1ST BYTE READ/WRITE 2ND BYTE READ/WRITE MAX110 MAX111 BUSY CS SCLK DOUT POL OFL D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DIN NO OP NU NU CONV4 CONV3 CONV2 CONV1 DV4 DV2 NU NU CHS CAL NUL PDX PD Figure 8a. SPI/MICROWIRE-Interface Timing MAX110 MAX111 BUSY CS SCLK DOUT POL OFL D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DIN NO OP NU NU CONV4 CONV3 CONV2 CONV1 DV4 DV2 NU NU CHS CAL NUL PDX PD Figure 8b. QSPI Serial-Interface Timing 14 ______________________________________________________________________________________ Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 Table 1. Input Control-Word Bit Map 15 NO-OP 14 NU 13 NU 12 11 10 9 8 DV4 7 DV2 6 NU 5 NU 4 CHS 3 CAL 2 NUL 1 PDX 0 PD CONV4 CONV3 CONV2 CONV1 ↑ First bit clocked in. BIT NAME DESCRIPTION If this bit is a logic high, the remaining 15 LSBs are transferred to the control register and a new conversion begins when CS returns high. If this bit is set low, the control word is not passed to the control register, the ADC configuration remains unchanged, and no new conversion begins when CS returns high. Used for test purposes only. Set these bits low. Conversion Time Control Bits. See Table 4. XCLK to Oversampling Cock Ratio Control Bits. See Table 5. Input Channel Select. A logic high selects channel 2 (IN2+ and IN2-), while a logic low selects channel 1 (IN1+ and IN1-). See Tables 2 and 3. Gain-Calibration Bit. A logic high selects gain-calibration mode. See Table 3. Internal Offset-Null Bit. A logic high selects offset-null mode. See Table 3. Oscillator Power-Down. Set this bit high to power down the RC oscillator. Analog Power-Down. Set this bit high to power down the analog section. 15 NO-OP 5, 6, 13, 14 9–12 7, 8 4 3 2 1 0 NU CONV1–CONV4 DV2, DV4 CHS CAL NUL PDX PD NO-OP is a zero, the control word is not transferred to the control register, the ADC’s configuration remains unchanged, and no new conversion is initiated. This allows specific ADCs in a “daisy chain” arrangement to be reconfigured while leaving the remaining ADCs unchanged. Table 1 lists the various ADC control word functions. Output data is shifted out of DOUT at the same time the input control word for the next conversion is shifted in (Figure 8). On power-up, all internal registers reset to zero. Therefore, when writing the first control word to the ADC, the data simultaneously shifted out will be zeros. The first conversion begins when CS goes high (NO-OP = 1). The results are placed in the 16-bit I/O register for access on the next data-transfer operation. When PDX is set high, the internal RC oscillator stops shortly after CS returns high. If the next control word written to the device has NO-OP = 1 instructing the ADC to convert, BUSY will go low, but because the RC oscillator is stopped, BUSY will remain low and will not allow a new conversion to begin. To avoid this situation, write a “dummy” control word with NO-OP = 0 and any combination of bits 14-0 in the control word following the control word with PDX = 0. With NO-OP = 0, bits 140 are ignored and the internal state machine resets. Next, perform a normal 3-step calibration (see Table 3). Note that XCLK must be connected to V DD or GND through a resistor (suggested value is 1MΩ) when the RC oscillator mode is selected (RCSEL = VDD). This resistor is not necessary if the external oscillator mode is used, or if the internal oscillator is not shut down. Power-Down Mode Bits 0 and 1 control the ADC’s power-down mode. If bit 0 (PD) is a logic high, power is removed from all analog circuitry except the RC oscillator. A logic high at bit 1 (PDX) removes power from the RC oscillator. If both bits PD and PDX are a logic high, or if PD is high and RCSEL is low, the supply currents reduce to 4µA. If an external XCLK clock continues to run in power-down mode, the supply current will depend on the clock rate. Selecting the Analog Inputs Bit 4 (CHS) controls which of the two differential inputs connect to the internal ADC inputs (see the Functional Diagram). A logic high selects IN2+ and IN2- while a logic low selects IN1+ and IN1-. Table 2 shows the allowable input multiplexer configurations. ______________________________________________________________________________________ 15 Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 Table 2. Allowable Input Multiplexer Configurations CAL NUL CHS 0 0 0 0 1 0 0 1 1 1 0 1 0 1 X NO-OP 1 1 1 1 1 ADC IN+ ADC ININ1+ IN2+ IN1IN2REFIN1IN2IN1IN2REFDESCRIPTION Channel 1 connected to ADC inputs. Conversion begins when CS returns high. Channel 2 connected to ADC inputs. Conversion begins when CS returns high. IN1- connected to the ADC inputs; offset-null mode selected. Autonull conversion begins when CS returns high, and the results are stored in the null register. IN2- connected to the ADC inputs; offset-null mode selected. Autonull conversion begins when CS returns high, and the results are stored in the null register. REF- connected to the ADC inputs; offset-null mode selected. Autonull conversion begins when CS returns high, and the results are stored in the null register. REF+ and REF- connected to the ADC inputs; gain-calibration mode selected. Autocal conversion begins when CS returns high, and the results are stored in the 16-bit I/O register. Input control word is not transferred to the control register. ADC configuration remains unchanged and no new conversion starts when CS returns high. 1 0 X 1 REF+ REF- X X X 0 No Change No Change X = Don't Care Table 3. Procedure to Calibrate the ADC CONTROL WORD STEP DESCRIPTION Sets the new conversion speed (if required) and performs an offset correction conversion with the internal ADC inputs shorted to REF-. The result is stored in the null register. (This step also selects the speed/resolution for the ADC.) Performs a gain-calibration conversion with the null register contents as the starting value. The result is stored in the calibration register. Performs an offset-null conversion with the internal ADC inputs shorted to the selected input channel's negative input (IN1- or IN2-). The next operation performs the first signal conversion with the new setup. NO-OP Not CONV1- DV2 & Not CHS Used CONV4 DV4 Used CAL NUL PDX PD 1 1 00 New Data XX 00 X 1 1 0 0 2 1 00 No Change XX 00 X 1 0 0 0 3 1 00 No Change XX 00 0 or 1 0 1 0 0 X = Don't Care 16 ______________________________________________________________________________________ Low-Cost, 2-Channel, ±14-Bit Serial ADCs 3-Step Calibration The data sheet electrical specifications apply to the device after optional calibration of gain error and offset. Uncalibrated, the gain error is typically 2%. Table 3 describes the three steps required to calibrate the ADC completely. Once the ADC is calibrated to the selected channel, set CAL = 0 and NUL = 0 and leave CHS unchanged in the next control word to perform a signal conversion on the selected analog input channel. Calibrate the ADC after the following operations: — when power is first applied — if the reference common-mode voltage changes — Automatic gain calibration is not allowed in the 102,400 cycles per conversion mode (see Programming Conversion Time). In this mode, calibration can be achieved by connecting the reference voltage to one input channel and performing a normal conversion. Subsequent conversion results can be corrected by software. Do not issue a NO-OP command directly following the gain calibration, as the calibration data will be lost. MAX110/MAX111 Programming Conversion Time The MAX110/MAX111 are specified for 12 bits of accuracy and up to ±14 bits of resolution. The ADC’s resolution depends on the number of clock cycles allowed during each conversion. Control-register bits 9–12 (CONV1–CONV4) determine the conversion time by controlling the nominal number of oversampling clock cycles required for each conversion (OSCC/CONV). Table 4 lists the available conversion times and resulting resolutions. To program a new conversion time, perform a 3-step calibration with the appropriate CONV1–CONV4 data used in Table 3. The ADC is now calibrated at the new conversion speed/resolution. — — — if the common-mode voltage of the selected input channel varies significantly. The CMRR of the analog inputs is 0.25LSB/V. after changing channels (if the common-mode voltages of the two channels are different) after changing conversion speed/resolution. after significant changes in temperature. The offset drift with temperature is typically 0.003µV/°C. Table 4. Available Conversion Times CONV4 CONV3 CONV2 CONV1 CLOCK CYCLES PER CONVERSION 10,240 20,480 81,920 102,400* NOMINAL CONVERSION TIME RCSEL = GND, DV2 = DV4 = 0, XCLK = 500kHz (ms) 20.48 40.96 163.84 204.80 CONVERSION RESOLUTION (Bits) 12 + POL 13 + POL 14 + POL 14 + POL 1 0 0 0 0 0 1 0 0 1 1 0 1 1 0 0 * Gain-calibration mode is not available with 102,400 clock cycles/conversion selected. Table 5. Clock Divider-Ratio Control DV2 0 0 1 1 DV4 0 1 0 1 DESCRIPTION XCLK or internal RC oscillator connects directly to the ADC; fOSC = fXCLK. XCLK or internal RC oscillator is divided by 4 and connects to the ADC; fOSC = fXCLK ÷ 4. XCLK or internal RC oscillator is divided by 2 and connects to the ADC; fOSC = fXCLK ÷ 2. Not allowed Clock duty cycles of 50% ±10% are recommended. ______________________________________________________________________________________ 17 Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 0 -10 -20 GAIN (dB) CONVERSION TIME LINE CYCLE PERIOD -30 -40 -50 -60 0.1 1 10 2 20 3 30 4 5 6 7 8 9 10 SIGNAL FREQUENCY IN Hz 1 FOR 100ms CONVERSION TIME (see Table 6) 40 50 60 70 80 90100 Figure 9. MAX110/MAX111 Noise Rejection Follows SIN(X) / X Function Selecting the Oversampling Clock Frequency Choose the oversampling frequency, fOSC, carefully to achieve the best relative-accuracy performance from the MAX110/MAX111 (see Typical Operating Characteristics). clock frequency can be used for best performance. Over the extended and military temperature ranges, the ratio of 2 or 4 gives the best performance. See the Typical Operating Characteristics to observe the effect of the clock divider on the converter’s linearity. Clock Divider-Ratio Control Bits Bits 7 and 8 (DV2 and DV4) program the clockfrequency divider network. The divider network sets the frequency ratio between f XCLK (the frequency of the external TTL/CMOS clock or internal RC oscillator) and fOSC (the oversampling frequency used by the ADC). An oversampling clock frequency between 450kHz and 700kHz is optimum for the converter. B est performance over the extended temperature range is obtained by choosing 1MHz or 1.024MHz with the divide-by-2 option (DV2 = 1) (see the section Effect of Dither on INL). To determine the converter’s accuracy at other clock frequencies, see the T ypical Operating Characteristics and Table 5. Effect of Dither on Relative Accuracy First-order sigma-delta converters require dither for randomizing any systematic tone being generated in the modulator. The frequency of the dither source plays an important role in linearizing the modulator. The ratio of the dither generator’s frequency to that of the modulator’s oversampling clock can be changed by setting the DV2/DV4 bits. The XCLK clock is directly used by the dither generator while the DV2/DV4 bits reduce the oversampling clock by a ratio of 2 or 4. Over the commercial temperature range, any ratio (i.e., 1, 2, or 4) between the dither frequency and the oversampling 18 50Hz/60Hz Line Frequency Rejection High rejection of 50Hz or 60Hz is obtained by using an oversampling clock frequency and a clock-cycles/conversion setting so the conversion time equals an integral number of line cycles, as in the following equation: fOSC = fLINE x m / n where fOSC is the oversampling clock frequency, fLINE = 50Hz or 60Hz, m is the number of clock cycles per conversion (see Table 4), and n is the number of line cycles averaged every conversion. This noise rejection is inherent in integrating and sigma-delta ADCs, and follows a SIN(X) / X function (Figure 9). Notches in this function represent extremely high rejection, and correspond to frequencies with an integral number of cycles in the MAX110/MAX111’s selected conversion time. The shortest conversion time resulting in maximum simultaneous rejection of both 60Hz and 50Hz line frequencies is 100ms. When using the MAX111, use a 200ms conversion time for maximum 60Hz and 50Hz rejection and optimum performance. For either device, select the appropriate oversampling clock frequency and either an 81,240 or 102,400 clock cycles per conversion (CCPC) ratio. Table 6 suggests the possible configurations. ______________________________________________________________________________________ Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 POWER SUPPLIES +5V -5V GND +5V POWER SUPPLIES GND *R = 10Ω 4.7µF 4.7µF *R = 10Ω 4.7µF 0.1µF VDD GND 0.1µF VSS +5V DGND VDD 0.1µF GND AGND +5V DGND MAX110 *OPTIONAL DIGITAL CIRCUITRY *OPTIONAL MAX111 DIGITAL CIRCUITRY Figure 10a. MAX110 Power-Supply Grounding Connections Figure 10b. MAX111 Power-Supply Grounding Connections A 100ms conversion time cannot be achieved with either 10,240 CCPC or 20,480 CCPC modes because fOSC would be below the minimum 250kHz requirement. When the gain calibration is performed, the conversion times change approximately 1% to compensate for the modulator’s gain error. This slightly degrades the linefrequency rejection, because the corrected conversion time is no longer an exact multiple of the line frequency. Typically, the rejection of 50Hz/60Hz from the converter is 55dB; i.e., if there is 100mV injection at the reference or the analog input pin, it will cause an uncertainty of ±0.006%. If the system has large 50Hz/60Hz noise, the use of internal auto gain calibration is not recommended. Instead, gain calibration should be done off-chip, using numerical computation methods. If you wish to use a configuration other than those suggested in Table 6, you can accomplish similar 50Hz and 60Hz line-frequency rejection off-chip by averaging several conversions. __________Applications Information Layout, Grounding, Bypassing For minimal noise, bypass each supply to GND with a 0.1µF capacitor. A ground plane should also be placed under the analog circuitry. To minimize the coupling effects of stray capacitance, keep digital lines as far from analog components and lines as possible. Figure 10 shows the suggested power-supply and groundplane connections. Table 6. Suggested XCLK Frequencies to Achieve Maximum Rejection of Both 50Hz/60Hz Line Frequencies MAX110 (tCONVERT = 100ms) 81,240 CCPC DIVIDER RATIO fXCLK (MHz) 0.8124 1.6248 3.2496 RELATIVE ACCURACY (%) 0.025 0.018 0.016 102,400 CCPC fXCLK (MHz) 1.024 2.048 4.096 RELATIVE ACCURACY (%) 0.065 0.045 0.030 DIVIDER RATIO MAX111 (tCONVERT = 200ms) 81,240 CCPC fXCLK (MHz) 0.4062 0.8124 1.6248 RELATIVE ACCURACY (%) 0.030 0.025 0.022 102,400 CCPC fXCLK (MHz) 0.512 1.024 2.048 RELATIVE ACCURACY (%) 0.030 0.025 0.023 1:1 2:1 4:1 1:1 2:1 4:1 CCPC = Clock Cycles per Conversion ______________________________________________________________________________________ 19 Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 +5V 0.1µF +5V VDD 22k 1/2 MAX492 +5V 1k 1µF +5V 121k 49.9k IN1+ 2k 49.9k 1k 1µF IN1REF+ 10k REF1k 30mV FULL-SCALE MAX111 CS DIN DOUT SCLK 121k +5V AGND 1/2 MAX492 GND Figure 11. Weigh Scale Application Capacitive Loading Effects of XCLK in Internal RC-Oscillator Mode When using the internal RC oscillator, capacitive loading effects on the XCLK pin must be minimized. Stray capacitance causes the VDD power consumption to increase by an amount p = 1⁄2CV2f, where C = stray capacitance, V is the supply voltage, and f is the frequency of the internal RC oscillator. Weigh Scale Application The fully differential analog signal and reference inputs make the MAX111 easy to interface to transducers with differential outputs, such as the load cell in Figure 11. Because the ADC input is differential, the load cell only requires differential gain, eliminating the need for the difference amplifier (differential to single-ended converter) of the standard three op-amp instrumentationamplifier realization. The 30mV full-scale bridge output is amplified to 2V full-scale and applied to the MAX111 channel-one input. The reference voltage to the ADC is created by a voltage divider connected to the +5V rail. The same 5V provides excitation for the bridge; therefore, as the excitation voltage varies, the reference voltage to the ADC also varies, providing an ADC output that does not depend on the supply voltage. The two 121kΩ resistors connected to the +5V supplies shift the common-mode voltage from 2.5V (5V/2) to 1.5V to ensure linearity. Match these two resistors to avoid introducing differential offset, or trim the resistor mismatch with a potentiometer. In practice, the scale is “zeroed” or “tared” by storing the average of several conversions in a memory location while the scale is External Reference The reference inputs to the ADC are high impedance, allowing both an external voltage reference and ratiometric applications without loading effects. The fully differential analog signal and reference inputs are advantageous for performing ratiometric conversions (Figures 11 and 12). For example, when measuring load cells, the bridge excitation and the ADC reference input both share the same voltage source. As the excitation changes with temperature or voltage, the output of the load cell will change. But since the differential reference voltage also changes, the conversion results remain constant, all else remaining equal. 20 ______________________________________________________________________________________ Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 1/4 MAX479 IN2+ IN210k 10k 1/4 MAX479 1k +5V 1µF VIN TEMP K-TYPE 243k IN1+ 1k 243k 10k 1k 1µF 1/4 MAX479 1M -5V IN1REF+ REFVSS DIN DOUT SCLK CS +5V VDD MAX110 MAX874 OUT Figure 12. Thermocouple Circuit with Software Compensation unloaded, and subtracting this value from actual weight measurements. The lowpass filtering action of the MAX111’s sigma-delta converter helps minimize noise. The resolution of the weigh scale can be further increased by averaging several conversions. Thermocouple Circuit with Software Compensation A thermocouple is created by the junction of dissimilar metals, and generates a voltage proportional to temperature (Seebeck voltage), making it useful for temperature-measurement instruments. When a thermocouple probe is connected to a measurement instrument, other thermoelectric potentials are created between the alloys of the probe and the copper connectors of the instrument. These potentials introduce a temperature-dependent error that must be subtracted from the temperature measurement to obtain an accurate result. According to the law of intermediate metals, the junction of the thermocouple-probe alloys with the copper of the instrument junction block can be treated as another thermocouple of the same type. The voltage measured by the instrument can be expressed as: V = α(T1 - TREF) where α is the Seebeck constant for the type of thermocouple, T1 is the temperature being measured, and TREF is the temperature of the junction block. Although one method to obtain TREF is to force the junction block to a known temperature (0°C), a more popular approach is to measure TREF directly using a thermistor or PN junction voltage. The circuit in Figure 12 shows a k-type thermocouple going through a 54dB gain stage to channel 1 of the MAX110. A MAX874 voltage reference provides both the 3V reference voltage and reference junction temperature information to the MAX110. Armed with the temperature information provided by the MAX874, the thermocouple voltage created at the junction block can be subtracted out in software. The TEMP output of the MAX874 is nominally 690mV at room temperature, and increases with temperature at about 2.3mV/°C. Place the MAX874 as close as possible to the terminal block, and ensure good thermal contact between them. This circuit employs a common k-type thermocouple and, with the component values shown, can indicate temperatures in the range of -150°C to +125°C. ______________________________________________________________________________________ 21 Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 _Ordering Information (continued) PART MAX110AEPE MAX110BEPE MAX110AEWE MAX110BEWE MAX110AEAP MAX110BEAP MAX110BMJE MAX111ACPE MAX111BCPE MAX111ACWE MAX111BCWE MAX111ACAP MAX111BCAP MAX111BC/D MAX111AEPE MAX111BEPE MAX111AEWE MAX111BEWE MAX111AEAP MAX111BEAP MAX111BMJE TEMP. RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C PIN-PACKAGE INL(%) 16 Plastic DIP 16 Plastic DIP 16 Wide SO 16 Wide SO 20 SSOP 20 SSOP 16 CERDIP** 16 Plastic DIP 16 Plastic DIP 16 Wide SO 16 Wide SO 20 SSOP 20 SSOP Dice* 16 Plastic DIP 16 Plastic DIP 16 Wide SO 16 Wide SO 20 SSOP 20 SSOP 16 CERDIP** ±0.03 ±0.05 ±0.03 ±0.05 ±0.03 ±0.05 ±0.05 ±0.03 ±0.05 ±0.03 ±0.05 ±0.03 ±0.05 ±0.05 ±0.03 ±0.05 ±0.03 ±0.05 ±0.03 ±0.05 ±0.05 __________________Chip Topography REF+ REF- IN1+ IN1- IN2+ IN2- V SS (AGND) V SS (AGND) GND V DD V DD R CSEL 0.168" (4.27mm) GND * Contact factory for dice specifications. ** Contact factory for availability. XCLK SCLK BUSY CS DOUT DIN 0.121" (3.07mm) ( ) ARE FOR MAX111 ____Pin Configurations (continued) TOP VIEW TRANSISTOR COUNT: 5849 SUBSTRATE CONNECTED TO VDD 1 2 3 4 5 6 7 8 9 20 19 IN1IN2+ IN2VSS (AGND) GND N.C. N.C. DIN DOUT CS IN1+ REFREF+ N.C. N.C. VDD RCSEL XCLK SCLK MAX110 MAX111 18 17 16 15 14 13 12 11 BUSY 10 SSOP ( ) ARE FOR MAX111 22 ______________________________________________________________________________________ Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 _______________________________________________________Package Information PDIPN.EPS ______________________________________________________________________________________ SOICW.EPS 23 Low-Cost, 2-Channel, ±14-Bit Serial ADCs MAX110/MAX111 ___________________________________________Package Information (continued) SSOP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. CDIPS.EPS