MAX11102

19-5245; Rev 5; 8/11 TION KIT EVALUA BLE ILA AVA 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs Features S 2Msps/3Msps Conversion Rate, No Pipeline Delay S 12-/10-/8-Bit Resolution S 1-/2-Channel, Single-Ended Analog Inputs S Low-Noise 73dB SNR S Variable I/O: 1.5V to 3.6V (Dual-Channel Only) Allows the Serial Interface to Connect Directly to 1.5V, 1.8V, 2.5V, or 3V Digital Systems S 2.2V to 3.6V Supply Voltage S Low Power 3.7mW at 2Msps 5.2mW at 3Msps Very Low Power Consumption at 2.5µA/ksps S External Reference Input (Dual-Channel Devices Only) S 1.3µA Power-Down Current S SPI-/QSPI-/MICROWIRE-Compatible Serial Interface S 10-Pin, 3mm x 3mm TDFN Package S 10-Pin, 3mm x 5mm µMAX Package S 6-Pin, 2.8mm x 2.9mm SOT23 Package S Wide -40NC to +125NC Operation General Description The M AX11102/MAX11103/MAX11105/MAX11106/ MAX11110/MAX11111/MAX11115/MAX11116/ MAX11117 are 12-/10-/8-bit, compact, high-speed, lowpower, successive approximation analog-to-digital converters (ADCs). These high-performance ADCs include a high-dynamic range sample-and-hold and a high-speed serial interface. These ADCs accept a full-scale input from 0V to the power supply or to the reference voltage. The MAX11102/MAX11103/MAX11106/MAX11111 feature dual, single-ended analog inputs connected to the ADC core using a 2:1 MUX. The devices also include a separate supply input for data interface and a dedicated input for reference voltage. In contrast, the single-channel devices generate the reference voltage internally from the power supply. These ADCs operate from a 2.2V to 3.6V supply and consume only 5.2mW at 3Msps and 3.7mW at 2Msps. The devices include full power-down mode and fast wake-up for optimal power management and a highspeed 3-wire serial interface. The 3-wire serial interface directly connects to SPIK, QSPIK, and MICROWIREK devices without external logic. Excellent dynamic performance, low voltage, low power, ease of use, and small package size make these converters ideal for portable battery-powered data-acquisition applications, and for other applications that demand low-power consumption and minimal space. These ADCs are available in a 10-pin TDFN package, 10-pin FMAX® package, and a 6-pin SOT23 package. These devices operate over the -40NC to +125NC temperature range. MAX11102/03/05/06/10/11/15/16/17 Applications Data Acquisition Portable Data Logging Medical Instrumentation Battery-Operated Systems Communication Systems Automotive Systems Ordering Information TOP MARK +AABH +AWI +AAAV 2 2 2 PART MAX11102AUB+ MAX11102ATB+ MAX11103AUB+ PIN-PACKAGE 10 FMAX-EP* 10 TDFN-EP* 10 FMAX-EP* BITS 12 12 12 SPEED (Msps) 2 2 3 NO. OF CHANNELS Ordering Information continued at end of data sheet. Note: All devices are specified over the -40°C to +125°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. µMAX is a registered trademark of Maxim Integrated Products, Inc. _______________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17 ABSOLUTE MAXIMUM RATINGS VDD to GND ............................................................ -0.3V to +4V REF, OVDD, AIN1, AIN2, AIN to GND ........-0.3V to the lower of (VDD + 0.3V) and +4V CS, SCLK, CHSEL, DOUT TO GND ............-0.3V to the lower of (VOVDD + 0.3V) and +4V AGND to GND ...................................................... -0.3V to +0.3V Input/Output Current (all pins) ...........................................50mA Continuous Power Dissipation (TA = +70NC) 6-Pin SOT23 (derate 8.7mW/NC above +70NC) ......... ..696mW 10-Pin TDFN (derate 24.4mW/NC above +70NC) ...... .1951mW 10-Pin FMAX (derate 8.8mW/NC above +70NC)...... ..707.3mW Operating Temperature Range ....................... .-40NC to +125NC Junction Temperature .....................................................+150NC Storage Temperature Range............................ -65NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (MAX11102/MAX11103) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD. MAX11102: fSCLK = 32MHz, 50% duty cycle, 2Msps. MAX11103: fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Total Unadjusted Error Channel-to-Channel Offset Matching Channel-to-Channel Gain Matching DYNAMIC PERFORMANCE (MAX11103: fAIN_ = 1MHz, MAX11102: fAIN_ = 0.5MHz) Signal-to-Noise and Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth Small-Signal Bandwidth Crosstalk SINAD SNR THD SFDR IMD MAX11103 MAX11102 MAX11103 MAX11102 MAX11103 MAX11102 MAX11103 MAX11102 MAX11103: f1 = 1.0003MHz, f2 = 0.99955MHz MAX11102: f1 = 500.15kHz, f2 = 499.56kHz -3dB point SINAD > 68dB 76 77 70 70 70.5 70.5 72 72.5 72 73 -85 -85 85 85 -84 40 2.5 45 -90 -75 -76 dB dB dB dB dB MHz MHz MHz dB INL DNL OE GE TUE Excluding offset and reference errors No missing codes Q0.3 Q1 Q1.5 Q0.4 Q0.05 12 Q1 Q1 Q3 Q3 Bits LSB LSB LSB LSB LSB LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS 2 ______________________________________________________________________________________ 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11102/MAX11103) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD. MAX11102: fSCLK = 32MHz, 50% duty cycle, 2Msps. MAX11103: fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER CONVERSION RATE Throughput Conversion Time Acquisition Time Aperture Delay Aperture Jitter Serial-Clock Frequency ANALOG INPUT (AIN1, AIN2) Input Voltage Range Input Leakage Current Input Capacitance VAIN_ IILA CAIN_ Track Hold 0 0.002 20 4 VDD + 0.05 0.005 5 0.75 x VOVDD 0.25 x VOVDD 0.15 x VOVDD Inputs at GND or VDD 0.001 2 0.85 x VOVDD 0.15 x VOVDD Q1.0 4 Q1 Q1 VREF Q1 V FA pF fCLK MAX11103 MAX11102 0.48 0.32 tACQ From CS falling edge MAX11103 MAX11102 MAX11103 MAX11102 0.03 0.02 260 391 52 4 15 48 32 3 2 Msps ns ns ns ps MHz SYMBOL CONDITIONS MIN TYP MAX UNITS MAX11102/03/05/06/10/11/15/16/17 EXTERNAL REFERENCE INPUT (REF) Reference Input-Voltage Range Reference Input Leakage Current Reference Input Capacitance VREF IILR CREF Conversion stopped 1 V FA pF DIGITAL INPUTS (SCLK, CS, CHSEL) Digital Input High Voltage Digital Input Low Voltage Digital Input Hysteresis Digital Input Leakage Current Digital Input Capacitance DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage High-Impedance Leakage Current High-Impedance Output Capacitance VOH VOL IOL COUT ISOURCE = 200FA ISINK = 200FA V V FA pF VIH VIL VHYST IIL CIN V V V FA pF _______________________________________________________________________________________ 3 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17 ELECTRICAL CHARACTERISTICS (MAX11102/MAX11103) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD. MAX11102: fSCLK = 32MHz, 50% duty cycle, 2Msps. MAX11103: fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER POWER SUPPLY Positive Supply Voltage Digital I/O Supply Voltage Positive Supply Current (Full-Power Mode) Positive Supply Current (FullPower Mode), No Clock Power-Down Current Line Rejection TIMING CHARACTERISTICS (Note 1) Quiet Time CS Pulse Width CS Fall to SCLK Setup CS Falling Until DOUT HighImpedance Disabled Data Access Time After SCLK Falling Edge SCLK Pulse Width Low SCLK Pulse Width High Data Hold Time From SCLK Falling Edge SCLK Falling Until DOUT HighImpedance Power-Up Time tQ t1 t2 t3 t4 t5 t6 t7 t8 (Note 2) (Note 2) (Note 2) (Note 2) Figure 2, VOVDD = 2.2V - 3.6V Figure 2, VOVDD = 1.5V - 2.2V Percentage of clock period (Note 2) Percentage of clock period (Note 2) Figure 3 Figure 4 (Note 2) Conversion cycle (Note 2) 40 40 5 2.5 14 1 4 10 5 1 15 16.5 60 60 ns ns ns ns ns % % ns ns Cycle VDD VOVDD IVDD IOVDD IVDD IPD MAX11103, VAIN_ = VGND MAX11102, VAIN_ = VGND MAX11103, VAIN_ = VGND MAX11102, VAIN_ = VGND MAX11103 MAX11102 Leakage only VDD = +2.2V to +3.6V, VREF = 2.2V 1.98 1.48 1.3 0.7 10 2.2 1.5 3.6 VDD 3.3 2.6 0.33 0.22 mA FA LSB/V mA V V SYMBOL CONDITIONS MIN TYP MAX UNITS ELECTRICAL CHARACTERISTICS (MAX11105) (VDD = 2.2V to 3.6V, fSCLK = 32MHz, 50% duty cycle, 2Msps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Total Unadjusted Error DYNAMIC PERFORMANCE Signal-to-Noise and Distortion Signal-to-Noise Ratio 4 SINAD SNR fAIN = 500kHz fAIN = 500kHz 70 70.5 72.5 73 dB dB INL DNL OE GE TUE Excluding offset and reference errors No missing codes Q0.3 Q1 Q1.5 12 Q1 Q1 Q3 Q3 Bits LSB LSB LSB LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS ______________________________________________________________________________________ 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11105) (continued) (VDD = 2.2V to 3.6V, fSCLK = 32MHz, 50% duty cycle, 2Msps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth Small-Signal Bandwidth CONVERSION RATE Throughput Conversion Time Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency ANALOG INPUT Input Voltage Range Input Leakage Current Input Capacitance VAIN IILA CAIN Track Hold 0.75 x VVDD 0.25 x VVDD 0.15 x VVDD Inputs at GND or VDD 0.001 2 0.85 x VVDD 0.15 x VVDD Q1.0 4 Q1 0 0.002 20 4 VDD Q1 V FA pF fCLK 0.32 tACQ From CS falling edge 0.02 391 52 4 15 32 2 Msps ns ns ns ps MHz SYMBOL THD SFDR IMD fAIN = 500kHz fAIN = 500kHz f1 = 500.15 kHz, f2 = 499.56 kHz -3dB point SINAD > 68dB 77 CONDITIONS MIN TYP -85 85 -84 40 2.5 45 MAX -76 UNITS dB dB dB MHz MHz MHz MAX11102/03/05/06/10/11/15/16/17 DIGITAL INPUTS (SCLK, CS, CHSEL) Digital Input High Voltage Digital Input Low Voltage Digital Input Hysteresis Digital Input Leakage Current Digital Input Capacitance DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage High-Impedance Leakage Current High-Impedance Output Capacitance POWER SUPPLY Positive Supply Voltage Positive Supply Current (Full-Power Mode) VDD IVDD VAIN = VGND 2.2 3.6 2.6 V mA VOH VOL IOL COUT ISOURCE = 200FA ISINK = 200FA V V FA pF VIH VIL VHYST IIL CIN V V V FA pF _______________________________________________________________________________________ 5 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17 ELECTRICAL CHARACTERISTICS (MAX11105) (continued) (VDD = 2.2V to 3.6V, fSCLK = 32MHz, 50% duty cycle, 2Msps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER Positive Supply Current (FullPower Mode), No Clock Power-Down Current Line Rejection TIMING CHARACTERISTICS (Note 1) Quiet Time CS Pulse Width CS Fall to SCLK Setup CS Falling Until DOUT HighImpedance Disabled Data Access Time After SCLK Falling Edge SCLK Pulse Width Low SCLK Pulse Width High Data Hold Time From SCLK Falling Edge SCLK Falling Until DOUT HighImpedance Power-Up Time tQ t1 t2 t3 t4 t5 t6 t7 t8 (Note 2) (Note 2) (Note 2) (Note 2) Figure 2, VDD = +2.2V to +3.6V Percentage of clock period (Note 2) Percentage of clock period (Note 2) Figure 3 Figure 4 (Note 2) Conversion cycle (Note 2) 40 40 5 2.5 14 1 4 10 5 1 15 60 60 ns ns ns ns ns % % ns ns Cycle SYMBOL IVDD IPD Leakage only VDD = +2.2V to +3.6V CONDITIONS MIN TYP 1.48 1.3 0.7 10 MAX UNITS mA FA LSB/V ELECTRICAL CHARACTERISTICS (MAX11106) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps; CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Total Unadjusted Error Channel-to-Channel Offset Matching Channel-to-Channel Gain Matching DYNAMIC PERFORMANCE Signal-to-Noise and Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range 6 SINAD SNR THD SFDR fAIN_ = 1MHz fAIN_ = 1MHz fAIN_ = 1MHz fAIN_ = 1MHz 75 61 61 61.8 61.8 -83 -74 dB dB dB dB INL DNL OE GE TUE Excluding offset and reference errors No missing codes Q0.5 0 Q0.5 Q0.05 Q0.05 10 Q0.4 Q0.4 Q1 Q1 Bits LSB LSB LSB LSB LSB LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS ______________________________________________________________________________________ 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11106) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps; CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth Small-Signal Bandwidth Crosstalk CONVERSION RATE Throughput Conversion Time Acquisition Time Aperture Delay Aperture Jitter Serial-Clock Frequency ANALOG INPUT (AIN1, AIN2) Input Voltage Range Input Leakage Current Input Capacitance VAIN_ IILA CAIN-_ Track Hold 0 0.002 20 4 VDD + 0.05 0.005 5 0.75 x VOVDD 0.25 x VOVDD 0.15 x VOVDD Inputs at GND or VDD 0.001 2 0.85 x VOVDD 0.15 x VOVDD Q1.0 4 Q1 Q1 VREF Q1 V FA pF fCLK 0.48 tACQ From CS falling edge 0.03 260 52 4 15 48 3 Msps ns ns ns ps MHz SYMBOL IMD -3dB point SINAD > 60dB CONDITIONS f1 = 1.0003MHz, f2 = 0.99955MHz MIN TYP -82 40 2.5 45 -90 MAX UNITS dB MHz MHz MHz dB MAX11102/03/05/06/10/11/15/16/17 EXTERNAL REFERENCE INPUT (REF) Reference Input-Voltage Range Reference Input Leakage Current Reference Input Capacitance VREF IILR CREF Conversion stopped 1 V FA pF DIGITAL INPUTS (SCLK, CS, CHSEL) Digital Input-High Voltage Digital Input-Low Voltage Digital Input Hysteresis Digital Input Leakage Current Digital Input Capacitance DIGITAL OUTPUT (DOUT) Output-High Voltage Output-Low Voltage High-Impedance Leakage Current High-Impedance Output Capacitance VOH VOL IOL COUT ISOURCE = 200µA ISINK = 200µA V V FA pF VIH VIL VHYST IIL CIN V V V FA pF _______________________________________________________________________________________ 7 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17 ELECTRICAL CHARACTERISTICS (MAX11106) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps; CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER POWER SUPPLY Positive Supply Voltage Digital I/O Supply Voltage Positive Supply Current (FullPower Mode) Positive Supply Current (FullPower Mode), No Clock Power-Down Current Line Rejection TIMING CHARACTERISTICS (Note 1) Quiet Time CS Pulse Width CS Fall to SCLK Setup CS Falling Until DOUT HighImpedance Disabled Data Access Time After SCLK Falling Edge (Figure 2) SCLK Pulse Width Low SCLK Pulse Width High Data Hold Time From SCLK Falling Edge SCLK Falling Until DOUT HighImpedance Power-Up Time tQ t1 t2 t3 t4 t5 t6 t7 t8 (Note 2) (Note 2) (Note 2) (Note 2) VOVDD = 2.2V - 3.6V VOVDD = 1.5V - 2.2V Percentage of clock period (Note 2) Percentage of clock period (Note 2) Figure 3 Figure 4 (Note 2) Conversion cycle (Note 2) 40 40 5 2.5 14 1 4 10 5 1 15 16.5 60 60 ns ns ns ns ns % % ns ns Cycle VDD VOVDD IVDD IOVDD IVDD IPD Leakage only VDD = +2.2V to +3.6V, VREF = 2.2V VAIN_ = VGND VAIN_ = VGND 1.98 1.3 0.17 10 2.2 1.5 3.6 VDD 3.3 0.33 V V mA mA FA LSB/V SYMBOL CONDITIONS MIN TYP MAX UNITS ELECTRICAL CHARACTERISTICS (MAX11110/MAX11117) (VDD = 2.2V to 3.6V. MAX11110: fSCLK = 32MHz, 50% duty cycle, 2Msps. MAX11117: fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error INL DNL OE No missing codes MAX11117 MAX11110 Excluding offset and reference errors, MAX11117 Excluding offset and reference errors, MAX11110 Q0.5 Q0.3 Q0.7 Q0.15 Q1 10 Q1 Q1 Q1.65 Q1.2 Q1.4 LSB Q1 LSB Bits LSB LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS Gain Error GE Total Unadjusted Error TUE 8 ______________________________________________________________________________________ 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11110/MAX11117) (continued) (VDD = 2.2V to 3.6V. MAX11110: fSCLK = 32MHz, 50% duty cycle, 2Msps. MAX11117: fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER SYMBOL MAX11117 MAX11110 MAX11117 MAX11110 MAX11117 MAX11110 MAX11117 MAX11110 MAXX11117: f1 = 1.0003MHz, f2 = 0.99955MHz MAX11110: f1 = 500.15kHz, f2 = 499.56kHz -3dB point SINAD > 60dB 75 75 -82 40 2.5 45 MAX11117 MAX11110 MAX11117 MAX11110 tACQ From CS falling edge MAX11117 MAX11110 0.48 0.32 0 0.002 Track Hold 0.75 x VDD 0.25 x VDD 0.15 x VDD Inputs at GND or VDD 0.001 2 Q1 20 4 0.03 0.02 260 391 52 4 15 fCLK 48 32 VDD Q1 3 2 CONDITIONS MIN 59 60.5 59 60.5 TYP 61.5 61.5 61.5 61.5 -85 -85 -74 -73 MAX UNITS DYNAMIC PERFORMANCE (MAX11117: fAIN = 1MHz, MAX11110: fAIN = 0.5MHz) Signal-to-Noise and Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth Small-Signal Bandwidth CONVERSION RATE Throughput Conversion Time Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency ANALOG INPUT (AIN) Input Voltage Range Input Leakage Current Input Capacitance VAIN IILA CAIN V FA pF Msps ns ns ns ps MHz SINAD SNR THD SFDR IMD dB dB dB dB dB MHz MHz MHz MAX11102/03/05/06/10/11/15/16/17 DIGITAL INPUTS (SCLK, CS, CHSEL) Digital Input-High Voltage Digital Input-Low Voltage Digital Input Hysteresis Digital Input Leakage Current Digital Input Capacitance VIH VIL VHYST IIL CIN V V V FA pF _______________________________________________________________________________________ 9 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17 ELECTRICAL CHARACTERISTICS (MAX11110/MAX11117) (continued) (VDD = 2.2V to 3.6V. MAX11110: fSCLK = 32MHz, 50% duty cycle, 2Msps. MAX11117: fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER DIGITAL OUTPUT (DOUT) Output-High Voltage Output-Low Voltage High-Impedance Leakage Current High-Impedance Output Capacitance POWER SUPPLY Positive Supply Voltage Positive Supply Current (Full-Power Mode) Positive Supply Current (Full-Power Mode), No Clock Power-Down Current Line Rejection TIMING CHARACTERISTICS (Note 1) Quiet Time CS Pulse Width CS Fall to SCLK Setup CS Falling Until DOUT HighImpedance Disabled Data Access Time After SCLK Falling Edge SCLK Pulse Width Low SCLK Pulse Width High Data Hold Time From SCLK Falling Edge SCLK Falling Until DOUT HighImpedance Power-Up Time tQ t1 t2 t3 t4 t5 t6 t7 t8 (Note 2) (Note 2) (Note 2) (Note 2) Figure 2, VDD = +2.2V to +3.6V Percentage of clock period (Note 2) Percentage of clock period (Note 2) Figure 3 Figure 4 (Note 2) Conversion cycle (Note 2) 40 40 5 2.5 14 1 4 10 5 1 15 60 60 ns ns ns ns ns % % ns ns Cycle VDD IVDD IVDD IPD MAX11117, VAIN = VGND MAX11110, VAIN = VGND MAX11117 MAX11110 Leakage only VDD = +2.2V to +3.6V 1.98 1.48 1.3 0.17 10 2.2 3.6 3.55 2.6 V mA mA FA LSB/V VOH VOL IOL COUT 4 ISOURCE = 200µA ISINK = 200µA 0.85 x VDD 0.15 x VDD Q1.0 V V FA pF SYMBOL CONDITIONS MIN TYP MAX UNITS 10 _____________________________________________________________________________________ 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11111) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Total Unadjusted Error Channel-to-Channel Offset Matching Channel-to-Channel Gain Matching DYNAMIC PERFORMANCE Signal-to-Noise and Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth Small-Signal Bandwidth Crosstalk CONVERSION RATE Throughput Conversion Time Acquisition Time Aperture Delay Aperture Jitter Serial-Clock Frequency ANALOG INPUT (AIN1, AIN2) Input Voltage Range Input Leakage Current Input Capacitance VAIN_ IILA CAIN_ Track Hold 0 0.002 20 4 VDD + 0.05 0.005 5 Q1 VREF Q1 V FA pF fCLK 0.48 tACQ From CS falling edge 0.03 260 52 4 15 48 3 Msps ns ns ns ps MHz SINAD SNR THD SFDR IMD fAIN_ = 1MHz fAIN_ = 1MHz fAIN_ = 1MHz fAIN_ = 1MHz f1 = 1.0003MHz, f2 = 0.99955MHz -3dB point SINAD > 49dB 63 49 49 49.8 49.8 -75 67 -65 40 2.5 45 -90 -67 dB dB dB dB dB MHz MHz MHz dB INL DNL OE GE TUE Excluding offset and reference errors No missing codes 0.45 0 0.5 0.01 0.01 8 Q0.15 Q0.15 Q0.7 Q0.2 Bits LSB LSB LSB LSB LSB LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS MAX11102/03/05/06/10/11/15/16/17 EXTERNAL REFERENCE INPUT (REF) Reference Input Voltage Range Reference Input Leakage Current Reference Input Capacitance VREF IILR CREF Conversion stopped 1 V FA pF ______________________________________________________________________________________ 11 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17 ELECTRICAL CHARACTERISTICS (MAX11111) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER DIGITAL INPUTS (SCLK, CS) Digital Input High Voltage Digital Input Low Voltage Digital Input Hysteresis Digital Input Leakage Current Digital Input Capacitance DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage High-Impedance Leakage Current High-Impedance Output Capacitance POWER SUPPLY Positive Supply Voltage Digital I/O Supply Voltage Positive Supply Current (Full-Power Mode) Positive Supply Current (Full-Power Mode), No Clock Power-Down Current Line Rejection TIMING CHARACTERISTICS (Note 1) Quiet Time CS Pulse Width CS Fall to SCLK Setup CS Falling Until DOUT HighImpedance Disabled Data Access Time After SCLK Falling Edge (Figure 2) SCLK Pulse Width Low SCLK Pulse Width High Data Hold Time From SCLK Falling Edge SCLK Falling Until DOUT HighImpedance Power-Up Time tQ t1 t2 t3 t4 t5 t6 t7 t8 (Note 2) (Note 2) (Note 2) (Note 2) VOVDD = 2.2V - 3.6V VOVDD = 1.5V - 2.2V Percentage of clock period (Note 2) Percentage of clock period (Note 2) Figure 3 Figure 4 (Note 2) Conversion cycle (Note 2) 40 40 5 2.5 14 1 4 10 5 1 15 16.5 60 60 ns ns ns ns ns % % ns ns Cycle VOH VOL IOL COUT VDD VOVDD IVDD IOVDD IVDD IPD Leakage only VDD = +2.2V to +3.6V, VREF = 2.2V VAIN_ = VGND VAIN_ = VGND 1.98 1.3 0.17 10 2.2 1.5 4 3.6 VDD 3.3 0.33 ISOURCE = 200µA (Note 2) ISINK = 200µA (Note 2) 0.85 x VOVDD 0.15 x VOVDD Q1.0 V V FA pF V V mA mA FA LSB/V VIH VIL VHYST IIL CIN Inputs at GND or VDD 0.15 x VOVDD 0.001 2 0.75 x VOVDD 0.25 x VOVDD V V V Q1 FA pF SYMBOL CONDITIONS MIN TYP MAX UNITS 12 _____________________________________________________________________________________ 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11115/MAX11116) (VDD = 2.2V to 3.6V. MAX11115: fSCLK = 32MHz, 50% duty cycle, 2Msps. MAX11116: fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Total Unadjusted Error INL DNL OE GE TUE MAX11116 MAX11115 MAX11116 MAX11115 MAX11116 MAX11115 MAX11116 MAX11115 MAX11116: f1 = 1.0003MHz, f2 = 0.99955MHz MAX11115: f1 = 500.15kHz, f2 = 499.56kHz -3dB point SINAD > 49dB 63 63 49 49 49 49 Excluding offset and reference errors No missing codes Q0.45 Q0.04 Q0.75 49.5 49.5 49.5 49.5 -70 -75 66 66 -65 40 2.5 45 MAX11116 MAX11115 MAX11116 MAX11115 tACQ From CS falling edge MAX11116 MAX11115 0.48 0.32 0 0.002 Track Hold 0.75 x VDD 20 4 0.03 0.02 260 391 52 4 15 fCLK 48 32 VDD Q1 3 2 -66 -67 8 Q0.25 Q0.25 Q0.75 Q0.5 Bits LSB LSB LSB LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS MAX11102/03/05/06/10/11/15/16/17 DYNAMIC PERFORMANCE (MAX11116: fAIN = 1MHz MAX11115: fAIN = 500kHz) Signal-to-Noise and Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth Small-Signal Bandwidth CONVERSION RATE Throughput Conversion Time Acquisition Time Aperture Delay Aperture Jitter Serial-Clock Frequency ANALOG INPUT (AIN) Input Voltage Range Input Leakage Current Input Capacitance DIGITAL INPUTS (SCLK, CS) Digital Input High Voltage VIH V VAIN IILA CAIN V FA pF Msps ns ns ns ps MHz SINAD SNR THD SFDR IMD dB dB dB dB dB MHz MHz MHz ______________________________________________________________________________________ 13 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17 ELECTRICAL CHARACTERISTICS (MAX11115/MAX11116) (continued) (VDD = 2.2V to 3.6V. MAX11115: fSCLK = 32MHz, 50% duty cycle, 2Msps. MAX11116: fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER Digital Input Low Voltage Digital Input Hysteresis Digital Input Leakage Current Digital Input Capacitance DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage High-Impedance Leakage Current High-Impedance Output Capacitance POWER SUPPLY Positive Supply Voltage Positive Supply Current (FullPower Mode) Positive Supply Current (FullPower Mode), No Clock Power-Down Current Line Rejection TIMING CHARACTERISTICS (Note 1) Quiet Time CS Pulse Width CS Fall to SCLK Setup CS Falling Until DOUT HighImpedance Disabled Data Access Time After SCLK Falling Edge SCLK Pulse Width Low SCLK Pulse Width High Data Hold Time From SCLK Falling Edge SCLK Falling Until DOUT HighImpedance Power-Up Time tQ t1 t2 t3 t4 t5 t6 t7 t8 (Note 2) (Note 2) (Note 2) (Note 2) Figure 2, VDD = +2.2V to +3.6V Percentage of clock period (Note 2) Percentage of clock period (Note 2) Figure 3 Figure 4 (Note 2) Conversion cycle (Note 2) 40 40 5 2.5 14 1 4 10 5 1 15 60 60 ns ns ns ns ns % % ns ns Cycle VDD IVDD IVDD IPD MAX11116, VAIN = VGND MAX11115, VAIN = VGND MAX11116 MAX11115 Leakage only VDD = +2.2V to +3.6V 1.98 1.48 1.3 0.17 10 2.2 3.6 3.55 2.6 V mA mA FA LSB/V VOH VOL IOL COUT 4 ISOURCE = 200µA ISINK = 200µA 0.85 x VDD 0.15 x VDD Q1.0 V V FA pF SYMBOL VIL VHYST IIL CIN Inputs at GND or VDD 0.15 VDD 0.001 2 Q1 CONDITIONS MIN TYP MAX 0.25 x VDD UNITS V V FA pF Note 1: All timing specifications given are with a 10pF capacitor. Note 2: Guaranteed by design in characterization; not production tested. 14 _____________________________________________________________________________________ 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17 SAMPLE SAMPLE t1 CS t2 SCLK 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 t6 t5 DOUT HIGH IMPEDANCE t3 0 D11 (MSB) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 HIGH IMPEDANCE t8 tQUIET t4 t7 tCONVERT 1/fSAMPLE tACQ Figure 1. Interface Signals for Maximum Throughput, 12-Bit Devices t4 SCLK SCLK t7 VIH DOUT OLD DATA NEW DATA VIL DOUT VIH VIL OLD DATA NEW DATA Figure 2. Setup Time After SCLK Falling Edge Figure 3. Hold Time After SCLK Falling Edge t8 SCLK DOUT HIGH IMPEDANCE Figure 4. SCLK Falling Edge DOUT Three-State ______________________________________________________________________________________ 15 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17 µMAX Typical Operating Characteristics (MAX11103AUB+, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE MAX11102 toc01 DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE MAX11102 toc02 OFFSET ERROR vs. TEMPERATURE MAX11102 toc03 1.0 fS = 3.0Msps 1.0 fS = 3.0Msps 3 2 OFFSET ERROR (LSB) 1 0 -1 -2 0.5 INL (LSB) 0.5 DNL (LSB) 0 0 -0.5 -0.5 -1.0 0 1000 2000 3000 4000 DIGITAL OUTPUT CODE -1.0 0 1000 2000 3000 4000 DIGITAL OUTPUT CODE -3 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (˚C) GAIN ERROR vs. TEMPERATURE MAX11102 toc04 HISTOGRAM FOR 30,000 CONVERSIONS 30,000 25,000 CODE COUNT 20,000 15,000 10,000 5000 0 MAX11102 toc05 3 2 GAIN ERROR (LSB) 1 0 -1 -2 -3 35,000 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (˚C) 2046 2047 2048 2049 2050 DIGITAL CODE OUTPUT SNR AND SINAD vs. ANALOG INPUT FREQUENCY MAX11102 toc06 THD vs. ANALOG INPUT FREQUENCY fS = 3Msps -70 -80 THD (dB) MAX11102 toc07 75 fS = 3Msps 74 SNR AND SINAD (dB) SNR 73 72 71 70 0 300 600 900 1200 -60 -90 -100 -110 -120 0 300 600 900 1200 1500 fIN (kHz) SINAD 1500 fIN (kHz) 16 _____________________________________________________________________________________ 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs µMAX Typical Operating Characteristics (continued) (MAX11103AUB+, TA = +25°C, unless otherwise noted.) SFDR vs. ANALOG INPUT FREQUENCY MAX11102 toc08 MAX11102/03/05/06/10/11/15/16/17 THD vs. INPUT RESISTANCE fS = 3.0Msps fIN = 1.0183MHz MAX11102 toc09 130 fS = 3Msps 120 110 SFDR (dB) 100 90 80 70 0 300 600 900 1200 -70 -75 -80 THD (dB) -85 -90 -95 -100 1500 0 20 40 RIN (I) 60 80 100 fIN (kHz) 1MHz SINE-WAVE INPUT (16,834-POINT FFT PLOT) fS = 3.0Msps fIN = 1.0183MHz MAX11102 toc10 REFERENCE CURRENT vs. SAMPLING RATE MAX11102 toc11 0 -20 AMPLITUDE (dB) -40 200 150 IREF (µA) -60 -80 -100 -120 0 250 500 750 1000 1250 1500 FREQUENCY (kHz) AHD3 = -91.2dB AHD2 = -110.3dB 100 50 0 0 500 1000 1500 fS (ksps) 2000 2500 3000 ANALOG SUPPLY CURRENT vs. TEMPERATURE MAX11102 toc12 SNR vs. REFERENCE VOLTAGE fS = 3Msps fIN = 1.0183MHz MAX11102 toc13 3.5 3.2 2.9 2.6 VDD = 3.0V 2.3 VDD = 2.2V 2.0 VDD = 3.6V 73.5 73.0 72.5 72.0 71.5 71.0 IVDD (mA) SNR (dB) -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (˚C) 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VREF (V) ______________________________________________________________________________________ 17 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17 SOT Typical Operating Characteristics (MAX11105AUB+, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE MAX11102 toc14 DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE fS = 2.0Msps 0.5 DNL (LSB) MAX11102 toc15 1.0 fS = 2.0Msps 0.5 INL (LSB) 1.0 0 0 -0.5 -0.5 -1.0 0 1000 2000 3000 4000 DIGITAL OUTPUT CODE -1.0 0 1000 2000 3000 4000 DIGITAL OUTPUT CODE OFFSET ERROR vs. TEMPERATURE MAX11102 toc16 GAIN ERROR vs. TEMPERATURE MAX11102 toc17 3 2 OFFSET ERROR (LSB) 1 0 -1 -2 -3 2 1 GAIN ERROR (LSB) 0 -1 -2 -3 -4 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (˚C) -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (˚C) HISTOGRAM FOR 30,000 CONVERSIONS MAX11102 toc18 SNR AND SINAD vs. ANALOG INPUT FREQUENCY fS = 2.0Msps 73.0 SNR 72.5 MAX11102 toc19 35,000 30,000 25,000 CODE COUNT 20,000 15,000 10,000 5000 0 2046 2047 2048 2049 2050 DIGITAL CODE OUTPUT 73.5 SNR AND SINAD (dB) 72.0 SINAD 71.5 0 200 400 600 800 1000 fIN (kHz) 18 _____________________________________________________________________________________ 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs SOT Typical Operating Characteristics (continued) (MAX11105AUB+, TA = +25°C, unless otherwise noted.) THD vs. ANALOG INPUT FREQUENCY MAX11102 toc20 MAX11102/03/05/06/10/11/15/16/17 SFDR vs. ANALOG INPUT FREQUENCY fS = 2.0Msps 105 100 SFDR (dB) 95 90 85 80 MAX11102 toc21 -80 fS = 2.0Msps -85 -90 THD (dB) -95 -100 -105 -110 0 200 400 600 800 110 1000 0 200 400 600 800 1000 fIN (kHz) fIN (kHz) THD vs. INPUT RESISTANCE MAX11102 toc22 500kHz SINE-WAVE INPUT (16,834-POINT FFT PLOT) fS = 2.0Msps fIN = 500.122kHz MAX11102 toc23 -75 -80 -85 -90 -95 -100 0 fS = 2.0Msps fIN = 500.122kHz 0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 THD (dB) AHD3 = -96.5dB AHD2 = -92.0dB 20 40 RIN (I) 60 80 100 0 250 500 FREQUENCY (kHz) 750 1000 ANALOG SUPPLY CURRENT vs. TEMPERATURE MAX11102 toc24 SNR vs. REFERENCE VOLTAGE (VDD) fS = 2.0Msps fIN = 500.122kHz 74 SNR (dB) MAX11102 toc25 2.6 VDD = 3.6V 2.4 2.2 2.0 1.8 1.6 VDD = 3.0V 75 IVDD (mA) 73 VDD = 2.2V 72 71 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (˚C) 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDD (V) ______________________________________________________________________________________ 19 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17 Pin Configurations TOP VIEW TOP VIEW AIN1 AIN2 AGND REF VDD 1 2 3 4 5 TOP VIEW + MAX11102 MAX11103 EP* 10 9 8 7 6 SCLK DOUT OVDD CHSEL CS AIN 3 GND 2 VDD 1 + 6 CS AIN1 AIN2 AGND REF VDD 1 2 3 4 5 *CONNECT EXPOSED PAD TO GROUND PLANE. DEVICES DO NOT OPERATE WHEN EP IS NOT CONNECTED TO GROUND! PIN TDFN 1 2 — — 3 4 µMAX 1 2 — — 3 4 SOT23 — — 3 2 — — 5 6 7 8 9 10 — 20 10 — _____________________________________________________________________________________ + MAX11102 MAX11103 MAX11106 MAX11111 EP* 10 9 8 7 6 SCLK DOUT OVDD CHSEL CS MAX11105 MAX11110 MAX11115 MAX11116 MAX11117 5 DOUT 4 SCLK µMAX SOT23 TDFN Pin Description NAME AIN1 AIN2 AIN GND AGND REF FUNCTION Analog Input Channel 1. Single-ended analog input with respect to AGND with range of 0V to VREF. Analog Input Channel 2. Single-ended analog input with respect to AGND with range of 0V to VREF. Analog Input Channel. Single-ended analog input with respect to GND with range of 0V to VDD. Ground. Connect GND to the GND ground plane. Analog Ground. Connect AGND directly the GND ground plane. External Reference Input. REF defines the signal range of the input signal AIN1/AIN2: 0V to VREF. The range of VREF is 1V to VDD. Bypass REF to AGND with 10FF || 0.1FF capacitor. Positive Supply Voltage. Bypass VDD with a 10FF || 0.1FF capacitor to GND. VDD range is 2.2V to 3.6V. For the SOT23 package, VDD also defines the signal range of the input signal AIN: 0V to VDD. Active-Low Chip-Select Input. The falling edge of CS samples the analog input signal, starts a conversion, and frames the serial data transfer. Channel Select. Set CHSEL high to select AIN2 for conversion. Set CHSEL low to select AIN1 for conversion. Digital Interface Supply for SCLK, CS, DOUT, and CHSEL. The OVDD range is 1.5V to VDD. Bypass OVDD with a 10FF || 0.1FF capacitor to GND. Three-State Serial Data Output. ADC conversion results are clocked out on the falling edge of SCLK, MSB first. See Figure 1. Serial Clock Input. SCLK drives the conversion process. DOUT is updated on the falling edge of SCLK. See Figures 2 and 3. Exposed Pad (TDFN and FMAX only). Connect EP directly to a solid ground plane. Devices do not operate unless EP is connected to ground! 5 1 VDD 6 7 8 9 6 — — 5 4 EP CS CHSEL OVDD DOUT SCLK GND 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs Functional Diagrams VDD OVDD VDD MAX11102/03/05/06/10/11/15/16/17 CS SCLK CONTROL LOGIC MAX11102/MAX11103/ MAX11106/MAX11111 CS SCLK CONTROL LOGIC MAX11105/MAX11110/ MAX11115/MAX11116/ MAX11117 SAR OUTPUT BUFFER DOUT SAR OUTPUT BUFFER DOUT CHSEL AIN1 AIN2 REF AIN MUX CDAC CDAC VREF = VDD AGND GND (EP) GND Typical Operating Circuit VDD +3V AIN1 ANALOG INPUTS AIN2 AGND REF +2.5V GND (EP) MAX11102 MAX11103 MAX11106 MAX11111 OVDD VOVDD SCLK SCK CPU DOUT CS CHSEL MISO SS VDD +3V GND MAX11105 MAX11110 MAX11115 MAX11116 MAX11117 SCLK DOUT SCK MISO CPU ANALOG INPUT AIN CS SS ______________________________________________________________________________________ 21 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17 Detailed Description The MAX11102/MAX11103/MAX11105/MAX11106/MAX11110/ MAX11111/MAX11115/MAX11116/MAX11117 are fast, 12-/10-/8-bit, low-power, single-supply ADCs. The devices operate from a 2.2V to 3.6V supply and consume only 8.3mW (VDD = 3V)/5.2mW (VDD = 2.2V) at 3Msps and 6.2mW (VDD = 3V)/3.7mW (VDD = 2.2V) at 2Msps. The 3Msps devices are capable of sampling at full rate when driven by a 48MHz clock and the 2Msps devices can sample at full rate when driven by a 32MHz clock. The dual-channel devices provide a separate digital supply input (OVDD) to power the digital interface enabling communication with 1.5V, 1.8V, 2.5V, or 3V digital systems. The conversion result appears at DOUT, MSB first, with a leading zero followed by the 12-bit, 10-bit, or 8-bit result. A 12-bit result is followed by two trailing zeros, a 10-bit result is followed by four trailing zeros, and an 8-bit result is followed by six trailing zeros. See Figures 1 and 5. The dual-channel devices feature a dedicated reference input (REF). The input signal range for AIN1/AIN2 is defined as 0V to VREF with respect to AGND. The single-channel devices use VDD as the reference. The input signal range of AIN is defined as 0V to VDD with respect to GND. SAMPLE These ADCs include a power-down feature allowing minimized power consumption at 2.5FA/ksps for lower throughput rates. The wake-up and power-down feature is controlled by using the SPI interface as described in the Operating Modes section. The devices feature a 3-wire serial interface that directly connects to SPI, QSPI, and MICROWIRE devices without external logic. Figures 1 and 5 show the interface signals for a single conversion frame to achieve maximum throughput. The falling edge of CS defines the sampling instant. Once CS transitions low, the external clock signal (SCLK) controls the conversion. The SAR core successively extracts binary-weighted bits in every clock cycle. The MSB appears on the data bus during the 2nd clock cycle with a delay outlined in the timing specifications. All extracted data bits appear successively on the data bus with the LSB appearing during the 13th/11th/9th clock cycle for 12-/10-/8-bit operation. The serial data stream of conversion bits is preceded by a leading “zero” and succeeded by trailing “zeros.” The data output (DOUT) goes into high-impedance state during the 16th clock cycle. Serial Interface SAMPLE CS SCLK 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 DOUT HIGH IMPEDANCE 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 HIGH IMPEDANCE 0 SAMPLE SAMPLE CS SCLK 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 DOUT HIGH IMPEDANCE 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 HIGH IMPEDANCE Figure 5. 10-/8-Bit Timing Diagrams 22 _____________________________________________________________________________________ 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs To sustain the maximum sample rate, all devices have to be resampled immediately after the 16th clock cycle. For lower sample rates, the CS falling edge can be delayed leaving DOUT in a high-impedance condition. Pull CS high after the 10th SCLK falling edge (see the Operating Modes section). The devices produce a digital output that corresponds to the analog input voltage within the specified operating range of 0 to VREF for the dual-channel devices and 0 to VDD for the single-channel devices. The source impedance of the external driving stage in conjunction with the sampling switch resistance affects the settling performance. The THD vs. Input Resistance graph in the Typical Operating Characteristics shows THD sensitivity as a function of the signal source impedance. Keep the source impedance at a minimum for high-dynamic performance applications. Use a highperformance op amp such as the MAX4430 to drive the analog input, thereby decoupling the signal source and the ADC. While the ADC is in conversion mode, the sampling switch is open presenting a pin capacitance, CP (CP = 5pF), to the driving stage. See the Applications Information section for information on choosing an appropriate buffer for the ADC. The output format is straight binary. The code transitions midway between successive integer LSB values such as 0.5 LSB, 1.5 LSB, etc. The LSB size for singlechannel devices is VDD/2n and for dual-channel devices is VREF/2n, where n is the resolution. The ideal transfer characteristic is shown in Figure 10. The ICs offer two modes of operation: normal mode and power-down mode. The logic state of the CS signal during a conversion activates these modes. The powerdown mode can be used to optimize power dissipation with respect to sample rate. Normal Mode In normal mode, the devices are powered up at all times, thereby achieving their maximum throughput rates. Figure 7 shows the timing diagram of these devices in normal mode. The falling edge of CS samples the analog input signal, starts a conversion, and frames the serial data transfer. MAX11102/03/05/06/10/11/15/16/17 Analog Input Figure 6 shows an equivalent circuit for the analog input AIN (for single-channel devices) and AIN1/AIN2 (for dual-channel devices). Internal protection diodes D1/D2 confine the analog input voltage within the power rails (VDD, GND). The analog input voltage can swing from GND - 0.3V to VDD + 0.3V without damaging the device. The electric load presented to the external stage driving the analog input varies depending on which mode the ADC is in: track mode vs. conversion mode. In track mode, the internal sampling capacitor CS (16pF) has to be charged through the resistor R (R = 50I) to the input voltage. For faithful sampling of the input, the capacitor voltage on CS has to settle to the required accuracy during the track time. ADC Transfer Function Operating Modes VDD D1 AIN1/AIN2 AIN CP D2 SWITCH CLOSED IN TRACK MODE SWITCH OPEN IN CONVERSION MODE R CS Figure 6. Analog Input Circuit KEEP CS LOW UNTIL AFTER THE 10TH SCLK FALLING EDGE CS PULL CS HIGH AFTER THE 10TH SCLK FALLING EDGE SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DOUT HIGH IMPEDANCE VALID DATA HIGH IMPEDANCE Figure 7. Normal Mode ______________________________________________________________________________________ 23 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17 PULL CS HIGH AFTER THE 2ND AND BEFORE THE 10TH SCLK FALLING EDGE CS SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DOUT HIGH IMPEDANCE INVALID DATA INVALID DATA OR HIGH IMPEDANCE HIGH IMPEDANCE Figure 8. Entering Power-Down Mode CS SCLK DOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HIGH IMPEDANCE INVALID DATA (DUMMY CONVERSION) HIGH IMPEDANCE VALID DATA HIGH IMPEDANCE Figure 9. Exiting Power-Down Mode OUTPUT CODE 111...111 111...110 111...101 FS - 1.5 x LSB edge terminates the conversion, DOUT goes into highimpedance mode, and the device enters power-down mode. See Figure 8. Power-Down Mode In power-down mode, all bias circuitry is shut down drawing typically only 1.3FA of leakage current. To save power, put the device in power-down mode between conversions. Using the power-down mode between conversions is ideal for saving power when sampling the analog input infrequently. Entering Power-Down Mode To enter power-down mode, drive CS high between the 2nd and 10th falling edges of SCLK (see Figure 8). By pulling CS high, the current conversion terminates and DOUT enters high impedance. Exiting Power-Down Mode To exit power-down mode, implement one dummy conversion by driving CS low for at least 10 clock cycles (see Figure 9). The data on DOUT is invalid during this dummy conversion. The first conversion following the dummy cycle contains a valid conversion result. The power-up time equals the duration of the dummy cycle, and is dependent on the clock frequency. The power-up time for 3Msps operation (48MHz SCLK) is 333ns. The power-up time for 2Msps operation (32MHz SCLK) is 500ns. 000...010 000...001 000...000 0 1 2 3 2n-2 2n-1 2n ANALOG INPUT (LSB) FULL SCALE (FS): AIN1/AIN2 = REF (TDFN, µMax) AIN = VDD (SOT) n = RESOLUTION Figure 10. ADC Transfer Function To remain in normal mode, keep CS low until the falling edge of the 10th SCLK cycle. Pulling CS high after the 10th SCLK falling edge keeps the part in normal mode. However, pulling CS high before the 10th SCLK falling 24 _____________________________________________________________________________________ 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs For applications requiring lower throughput rates, the user can reduce the clock frequency (fSCLK) to lower the sample rate. Figure 11 shows the typical supply current (IVDD) as a function of sample rate (fS) for the 3Msps devices. The part operates in normal mode and is never powered down. Figure 13 pertains to the 2Msps devices. Supply Current vs. Sampling Rate The user can also power down the ADC between conversions by using the power-down mode. Figure 12 shows for the 3Msps device that as the sample rate is reduced, the device remains in the power-down state longer and the average supply current (IVDD) drops accordingly. Figure 14 pertains to the 2Msps devices. MAX11102/03/05/06/10/11/15/16/17 4 3 2 1 0 0 VDD = 3V fSCLK = VARIABLE 16 CYCLES/CONVERSION MAX11102 fig11 5 4 VDD = 3V fSCLK = VARIABLE 16 CYCLES/CONVERSION 3 IVDD (mA) 3000 IVDD (mA) 2 1 0 500 1000 1500 fS (ksps) 2000 2500 0 500 1000 fS (ksps) 1500 2000 Figure 11. Supply Current vs. Sample Rate (Normal Operating Mode, 3Msps Devices) Figure 13. Supply Current vs. Sample Rate (Normal Operating Mode, 2Msps Devices) 3.0 2.5 2.0 IVDD (mA) 1.5 1.0 VDD = 3V fSCLK = 48MHz 2.0 VDD = 3V fSCLK = 32MHz 1.5 IVDD (mA) 1.0 0.5 0.5 0 0 200 400 600 800 1000 fS (ksps) 0 0 100 200 300 400 500 fS (ksps) Figure 12. Supply Current vs. Sample Rate (Device Powered Down Between Conversions, 3Msps Devices) Figure 14. Supply Current vs. Sample Rate (Device Powered Down Between Conversions, 2Msps Devices) ______________________________________________________________________________________ 25 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17 Dual-Channel Operation The MAX11102/MAX11103/MAX11106/MAX11111 feature dual-input channels. These devices use a channelselect (CHSEL) input to select between analog input AIN1 (CHSEL = 0) or AIN2 (CHSEL = 1). As shown in Figure 15, the CHSEL signal is required to change between the 2nd and 12th clock cycle within a regular conversion to guarantee proper switching between channels. The ICs can operate with 14 cycles per conversion. Figure 16 shows the corresponding timing diagram. Observe that DOUT does not go into high-impedance mode. Also, observe that tACQ needs to be sufficiently long to guarantee proper settling of the analog input voltage. See the Electrical Characteristics table for tACQ requirements and the Analog Input section for a description of the analog inputs. Applications Information For best performance, use PCBs with a solid ground plane. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another or digital lines underneath the ADC package. Noise in the VDD power supply, OVDD, and REF affects the ADC’s performance. Bypass the VDD, OVDD, and REF to ground with 0.1FF and 10FF bypass capacitors. Minimize capacitor lead and trace lengths for best supply-noise rejection. It is important to match the settling time of the input amplifier to the acquisition time of the ADC. The conversion results are accurate when the ADC samples the input signal for an interval longer than the input signal’s worst-case settling time. By definition, settling time is the interval between the application of an input voltage step and the point at which the output signal reaches Layout, Grounding, and Bypassing 14-Cycle Conversion Mode Choosing an Input Amplifier CS SCLK CHSEL DOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DATA CHANNEL AIN2 DATA CHANNEL AIN1 Figure 15. Channel Select Timing Diagram SAMPLE SAMPLE CS SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 DOUT 0 D11 (MSB) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 tACQ 0 0 1/fSAMPLE tCONVERT Figure 16. 14-Clock Cycle Operation 26 _____________________________________________________________________________________ 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs and stays within a given error band centered on the resulting steady-state amplifier output level. The ADC input sampling capacitor charges during the sampling cycle, referred to as the acquisition period. During this acquisition period, the settling time is affected by the input resistance and the input sampling capacitance. This error can be estimated by looking at the settling of an RC time constant using the input capacitance and the source impedance over the acquisition time period. Figure 17 shows a typical application circuit. The MAX4430, offering a settling time of 37ns at 16 bits, is an excellent choice for this application. See the THD vs. Input Resistance graph in the Typical Operating Characteristics. +5V For devices using an external reference, the choice of the reference determines the output accuracy of the ADC. An ideal voltage reference provides a perfect initial accuracy and maintains the reference voltage independent of changes in load current, temperature, and time. Considerations in selecting a reference include initial voltage accuracy, temperature drift, current source, sink capability, quiescent current, and noise. Figure 17 shows a typical application circuit using the MAX6126 to provide the reference voltage. The MAX6033 and MAX6043 are also excellent choices. Choosing a Reference MAX11102/03/05/06/10/11/15/16/17 0.1µF 10µF 100pF COG 500I 3V VDD 0.1µF 10µF VOVDD OVDD 0.1µF 10µF AIN1 500I 3 5 1 MAX4430 AGND AIN1 MAX11102 MAX11103 MAX11106 MAX11111 10I -5V 470pF COG CAPACITOR VDC 4 2 0.1µF 10µF SCLK DOUT CS SCK MISO SS CPU AIN2 470pF COG CAPACITOR REF +5V 10µF CHSEL EP 0.1µF 10µF +5V 7 OUTF OUTS MAX6126 100pF COG 500I 0.1µF IN 2 1µF 0.1µF 8 AIN2 500I 4 3 5 1 MAX4430 GNDS GND NR 1 0.1µF 10I -5V 3 VDC 4 2 0.1µF 10µF Figure 17. Typical Application Circuit ______________________________________________________________________________________ 27 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17 Definitions Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. For these devices, the straight line is a line drawn between the end points of the transfer function after offset and gain errors are nulled. Integral Nonlinearity SINAD is a dynamic figure of merit that indicates the converter’s noise and distortion performance. SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset: .   SIGNAL RMS SINAD(dB) = 20 × log    (NOISE + DISTORTION) RMS    Signal-to-Noise Ratio and Distortion (SINAD) Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of ±1 LSB or less guarantees no missing codes and a monotonic transfer function. The deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, AGND + 0.5 LSB. The deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal after adjusting for the offset error, that is, VREF - 1.5 LSB. Differential Nonlinearity Offset Error Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as:  2 2 2 V 2 + V3 + V4 + V5  THD = 20 × log 2     V1   where V1 is the fundamental amplitude and V2–V5 are the amplitudes of the 2nd- through 5th-order harmonics. SFDR is a dynamic figure of merit that indicates the lowest usable input signal amplitude. SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. SFDR is specified in decibels with respect to the carrier (dBc). Full-power bandwidth is the frequency at which the input signal amplitude attenuates by 3dB for a full-scale input. Full-linear bandwidth is the frequency at which the signal-to-noise ratio and distortion (SINAD) is equal to a specified value. Any device with nonlinearities creates distortion products when two sine waves at two different frequencies (f1 and f2) are applied into the device. Intermodulation distortion (IMD) is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones, f1 and f2. The individual input tone levels are at -6dBFS. Total Harmonic Distortion Gain Error Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. Aperture Jitter Aperture delay (tAD) is the time between the falling edge of sampling clock and the instant when an actual sample is taken. SNR is a dynamic figure of merit that indicates the converter’s noise performance. For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR (dB) (MAX) = (6.02 x N + 1.76) (dB) In reality, there are other noise sources such as thermal noise, reference noise, and clock jitter that also degrade SNR. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset. Aperture Delay Spurious-Free Dynamic Range (SFDR) Signal-to-Noise Ratio (SNR) Full-Power Bandwidth Full-Linear Bandwidth Intermodulation Distortion 28 _____________________________________________________________________________________ 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs Ordering Information (continued) PART MAX11103ATB+ MAX11105AUT+ MAX11106ATB+ MAX11110AUT+ MAX11111ATB+ MAX11115AUT+ MAX11116AUT+ MAX11117AUT+ PIN-PACKAGE 10 TDFN-EP* 6 SOT23 10 TDFN-EP* 6 SOT23 10 TDFN-EP* 6 SOT23 6 SOT23 6 SOT23 BITS 12 12 10 10 8 8 8 10 SPEED (Msps) 3 2 3 2 3 2 3 3 NO. OF CHANNELS 2 1 2 1 2 1 1 1 TOP MARK +AWV +ACON +AWJ +ACOD +AWL +ACOP +ACOX +ACOY MAX11102/03/05/06/10/11/15/16/17 Note: All devices are specified over the -40°C to +125°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Chip Information PROCESS: CMOS Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 10 TDFN-EP 10 µMAX-EP 6 SOT23 PACKAGE CODE T1033+2 U10E+3 U6+1 OUTLINE NO. 21-0137 21-0109 21-0058 LAND PATTERN NO. 90-0061 90-0148 90-0175 ______________________________________________________________________________________ 29 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17 Revision History REVISION NUMBER 0 1 2 3 4 5 REVISION DATE 4/10 7/10 9/10 10/10 2/11 8/11 DESCRIPTION Initial release of the MAX11102/MAX11103/MAX11105/MAX11110/MAX11115 /MAX11116/MAX11117 Initial release of the MAX11106/MAX11111. Corrected the package code of the µMAX package in the Package Information section. Changed the typical power consumption to 2.2V in the General Description, Features, and Detailed Description sections. Update style, change voltage in Figure 17. Updated the Ordering Information and Electrical Characteristics sections. PAGES CHANGED — 1–30 29 1, 22 4, 5, 8, 9, 10, 12, 13, 14, 27 1, 4, 6, 8, 10, 12, 14, 29 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 30 © Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.